Abstract: A first and a second input generating circuits, a first and a second set of counters, and a first and a second comparison circuits are provided to test whether the frequencies of a first and a second periodic digital signal are symmetric. The first and second input generating circuits generate enable inputs for the first and second sets of counters using the first and second digital signals respectively. The first and second sets of counters count the first and second digital signals while the enable inputs are provided. The first comparison circuit monitors the first set of counters, and stops both input generating circuits from providing further enable inputs to both sets of counters, after the first set of counters reaches a predetermined level, thereby stopping both sets of counters from further counting.

Abstract: A receiver (10) for extracting complex values by reference to a local frequency reference determines the frequency offset between a local oscillator (16) and the carrier by employing a circuit (40) for determining a "phase rotation." When a record of the input signal is determined to have resulted from a predetermined reference sequence of complex values, the phase-rotation circuit (40) compares the phases of complex values extracted from this record with corresponding symbols of the reference sequence. By comparing this difference for one part of the sequence with that for another, circuitry (38, 50, 52, 53, 54) in the receiver infers the frequency offset between the transmitter reference and the receiver reference, and a complex multiplier (34) compensates for this offset by multiplying the successive complex-valued samples by a complex exponential whose frequency is the negative of the frequency offset.

Abstract: A fully-symmetric high-speed CMOS frequency synthesizer which exhibits minimum dead-zone effects is disclosed. A fully-symmetric phase-frequency detector and a fully differential charge-pump filter combined with a voltage-controlled oscillator are key elements of the invention described.

Abstract: A time measurement system for measuring time accurately with an inaccurate clock, in which two clock oscillators are compared and the momentary error of the slower clock oscillator is measured. When the error change rate of the slower clock oscillator is slow enough the fast clock oscillator can be switched off for longer time intervals. With the help of this apparatus and method of operation power can be saved in portable equipment which requires accurate time measurement.

Abstract: A damping circuit is described which includes a phase-and-frequency detector, a charge pump, a voltage-current oscillator and a capacitor. The phase-and-frequency detector generates UP and DOWN signals representative of a difference in phase between a pair of digital input signals. The charge pump varies an amount of charge carried within the capacitor in accordance with the UP and DOWN signals. The voltage controlled oscillator generates an output signal having a frequency controlled by both a voltage provided by the capacitor and by the UP and DOWN signals directly received from the phase-and-frequency detector. No analog damping resistor is required. Rather, the digital damping circuit is a digital circuit which generates adequate phase and frequency damping without a damping resistor. In this manner damping is achieved which is substantially unaffected by process parameters and operating and ambient parameters. Method embodiments of the invention are also described.