Abstract: An apparatus includes an integrated circuit that includes low side power supply circuitry that provides an output voltage for H-bridge circuitry. The low side power supply circuitry includes one transistor that provides one current to the output of the low side power supply circuitry in response to the output voltage of the low side power supply circuitry dropping below a quiescent level. The low side power supply circuitry also includes a second transistor that controls the conduction state of a third transistor, based at least in part, upon the first transistor providing the first current to the output of the low side power supply circuitry. The third transistor provides a second current to the output of the low side power supply circuitry.

Abstract: A driver for a switching device has a plurality of driver circuits for driving the switching device and a control circuit. The control circuit selectively operates the driver circuits in response to a plurality of predetermined drive modes. Alternatively, a driver for a switching device has a driver circuit and a control circuit. The driver circuit is connected to a plurality of power sources. Each of the power sources has a different voltage. The control circuit selects one of the power sources for operating the driver circuit in response to a plurality of predetermined drive modes.

Abstract: A circuit for preventing shoot-through in a high side switching transistor coupled in series with a low side switching transistor across a supply voltage, the circuit comprising a voltage reference circuit having an output providing a reference voltage which is negative with respect to the supply voltage provided to the high side switching transistor, the reference voltage being applied to the control electrode of the high side switching transistor when the high side switching transistor is off and the source of the high side switching transistor exceeds the reference voltage and the low side switching transistor is on.

Abstract: A method for driving a motor by imposing the current in the motor by means of power current mirrors is presented. This allows driving the motor in current with higher accuracy and lower electrical noise. The Hard Disk Drive application is an example where higher resolution is required for the VCM motor. Furthermore this method reduces the complexity of the system eliminating components and high performance circuits. Moreover this approach reduces the development and manufacturing cost by simplifying the testability and the analysis of the system. The intrinsic elimination of DC offset also takes out the need for the system offset calibration phase and significantly improves on the harmonic distortion of the transfer function. Furthermore this method offers the advantage of faster overall response of the system and higher efficiency.

Abstract: A low-power multi-level pulse amplitude modulation (PAM) line driver using variable resistors is disclosed for transmitting digital data over controlled-impedance transmission lines. This invention discloses the design of a multi-level PAM driver for high-speed wireline communication, with up to four times improvement in power efficiency over conventional drivers. Two key requirements for high-speed line drivers are first generating the target voltage level onto the controlled-impedance line, and second being impedance matched to the line itself to eliminate signal reflections from the transmitter back to the line. The driver in accordance with the present invention satisfies both of these requirements at very high power efficiency.

Abstract: A self-oscillating full-bridge driver IC, in which the high-side drivers each have a bootstrap capacitor, and a bootstrap circuit for pre-charging the bootstrap capacitors before starting up the oscillator or supplying control signals to the high-side drivers.

Abstract: A driver circuit that has a plurality of output elements that are switched on and off in staggered fashion by signals generated by first and second drive chains of a drive chain configuration. The first drive chain comprises “N” delay elements, each of which produces a time delay equal to tDELAY such that the total time delay produced by the first drive chain is equal to (N×tDELAY). The second drive chain comprises N+1 delay elements, “N” of which produce a time delay equal to tDELAY and one of which produces a time delay equal to ½(tDELAY). Therefore, the total time delay produced by the second drive chain is equal to ((N×tDELAY)+(½tDELAY)). The use of the delay element in the second drive that produces the time delay equal to ½(tDELAY) results in smooth transitions in the transition regions where the driver circuit output signal transitions from high to low and from low to high.

Abstract: A write driver includes two field-effect/bipolar transistors with feedbacks between the drains/collectors and gates/bases, a write/read switch connected between the drains/collectors and a positive power supply, an impedance matching circuit connected to the drains/collectors to match both differential and common mode output impedance of the write driver to an input impedance of a flex circuit, a common mode output voltage control circuit coupled to the transistors, and a differential mode output voltage control circuit coupled to the transistors.

Abstract: An electronic discharge circuit. The discharge circuit includes a first current source having first current source input and output and a current control circuit having first, second, third, and fourth control contacts. An electronic circuit element of an electronic circuit has first and second element contacts. If first control contact and first current source input are electrically connected, second control contact and first current source output are electrically connected, third control contact and first element contact are electrically connected, and fourth control contact and second element contact are electrically connected, and if the electronic circuit element is electronically charged, current discharging the electronic circuit element is limited to the current from the first current source, otherwise when so connected, current discharging the electronic circuit element is zero and current from the first current source flows into the second control contact and out the first control contact.

Abstract: A pulse-width modulation circuit converts an input signal into a pulse signal to be supplied to a switch amplifying circuit. The modulation circuit includes a comparison signal generator, an amplitude controller for modulating a comparison signal from the signal generator, and a comparator for comparing the modulated comparison signal and the input signal. The comparator outputs a signal whose level is inverted in accordance with the level of the input signal. The signal outputted from the comparator is supplied to the switch amplifying circuit.

Abstract: A system and method for measuring in real-time the current of a current mode driver circuit for writing data through a write head in tape or disk drive storage devices, the current mode driver circuit including one or more current mirror circuits for providing a current output in proportion to current through the write head during a write operation, the system comprising: device for converting the current mirror circuit current output into a first voltage; device for generating a second voltage representing a reference current; and, a device for comparing the first voltage value to the second voltage and generating an output signal indicating a ratio of the first and second voltages, the ratio being a measure of the current output of the current mirror circuit.

Abstract: A supply assembly for an LED lighting module includes a control switch for supplying a constant current to the LED lighting module. A dual switching signal composed of low frequency bursts of high frequency pulses is applied to the control switch. By varying the low frequency component of the dual switching signal, the average current through the LED lighting module may be varied in order to vary the light intensity outputted by the LED lighting module.

Abstract: An operational amplifier connected to first and second transistors of an H-bridge for sinking and sourcing current, the operational amplifier having a differential input and an output and comprising a transconductance circuit, a gain circuit, a buffer circuit, and first and second feedback networks. The transconductance circuit is connected to receive the differential input and provide an output, wherein the output is connected to the second transistor of the H-bridge. The gain circuit is connected to receive the output from the transconductance circuit, wherein the gain circuit includes a transistor that is matched to the second transistor of the H-bridge. The buffer circuit is connected between the gain circuit and the first transistor of the H-bridge. The first feedback network comprises a level shift circuit connected to the output of the operational amplifier and a clamping circuit connected between the level shift circuit and an input of the buffer circuit.

Abstract: A driving circuit for switches of direct current fan motor is disclosed. The driving circuit includes a plurality of switches, a first control circuit, and a second circuit. The switches are driven by a first pulse width modulation signal and a second pulse width modulation signal, and they are electrically connected with the direct current fan motor in a bridge manner. A third pulse width modulation signal is used to drive the first control circuit connected to at least one of the switches driven by the first pulse width modulation signal. A fourth pulse width modulation signal is used to drive the second control circuit connected to at least one of the switches driven by the second pulse width modulation signal. Especially, either the first pulse width modulation signal or the second pulse width modulation signal is selected as the third pulse width modulation signal or the fourth pulse width modulation signal.

Abstract: A write driver circuit for driving a magnetic head applicable to a variety of magnetic heads or magnetic storage media is disclosed. The circuit includes a write current generating section for generating plural types of write current for magnetizing a predetermined area of a magnetic storage medium in a predetermined direction; a switching signal generating section for generating a switching signal for switching among the write currents; a switching section for changing the direction of magnetization through the magnetic head by switching among the write currents based on the switching signal; and an overshoot current generating section for generating an overshoot current for instantaneously increasing the write current when the direction of magnetization is changed by the switching section; wherein the circuit further includes an overshoot current generation signal producing section, and is designed so that the overshoot current is generated based on an overshoot current generation signal produced thereby.

Abstract: A P-CHANNEL MOSFET is configured as a high side switch by arranging a capacitor between the P-CHANNEL MOSFET gate and a pair of push/pull transistors in a control circuit. A pull-up resistor is connected with the high side supply, one leg of the capacitor and with the gate of the P-CHANNEL MOSFET. In a two-phase electrical drive circuit, a pair of P-CHANNEL MOSFETS is connected with the high side supply and a pair of N-CHANNEL MOSFETS is connected with the low side supply.

Abstract: A pulse width modulation scheme allows the creation of a unipolar pulse width modulated output signal. Two switching circuits (104, 204), preferably different legs of an inverter circuit, can operate to not only modulate an input voltage but also to reverse the polarity of the PWM output signal. Both switching circuits can be configured to accomplish both features, thus the switching load is spread out across all four switches.

Abstract: A circuit arrangement for a resistor of high linearity that can be produced in integrated technology and be controlled by the current (Io1, Io2), which circuit arrangement is constructed from two pairs of transistors comprising transistors (T1 . . . T4) of the same junction type connected as diodes. Each pair of transistors (T1, T2 and T3, T4) has a common point of connection (D, E) that connects together the anodes of one pair of diodes and the cathodes of the other pair. The point of connection (D) of the first pair of transistors (T1, T2) is situated on their collector lines and thus connects the anodes and forms the infeed point for a first control current source (Io1). The point of connection (E) of the second pair of transistors connects the cathodes and is thus situated on their emitter lines and forms the infeed point for a second control current source (Io2).

Abstract: A gate drive integrated circuit for switching power transistors using an external controller includes a gate driving capability and low quiescent current and allows use of a bootstrap supply technique for providing the logic supply voltage. The gate driver integrated circuit detects power transistor desaturation, protecting a desaturated transistor from transient over voltages by smoothly turning off the desaturated transistor via a soft shutdown sequence. A fault control circuit of the gate driver integrated circuit manages protection of supply under-voltage and transistor desaturation and is capable of communicating with a plurality of gate driver integrated circuits in a multi-phase system using a dedicated local network.

Abstract: A zero-voltage-switching full bridge converter has first and second switching units between which a transformer is coupled. Each switching unit is composed of two MOSFETs as the switching elements and controlled by a non-overlap gate driver. For either the first switching unit or the second switching unit, the activated periods of the driving signals for the two switching elements do not overlap. Therefore, the switching loss of the full bridge converter is mitigated.

Abstract: An H-bridge driver has a drive signal generating circuit for generating a square-wave signal as a drive signal. The H-bridge driver also has a waveform shaping circuit for blunting the waveform of the drive signal at the rising and trailing edges thereof. The waveform shaping circuit has a first circuit for generating, in a rising period of the square-wave signal fed thereto, a first current having a positive peak at the center of the rising period, a second circuit for generating, in a trailing period of the square-wave signal fed thereto, a second current having a negative peak at the center of the trailing period, and a capacitor to which the first and second currents are fed. The waveform shaping circuit outputs the voltage across the capacitor as its output voltage.

Abstract: A transconductance circuit (16) and method for protecting an H-bridge power circuit (10) that provides power to a load that includes an inductive component (14) connected between one side of the inductive component (14) and a gate (25) of a low side transistor (24) of the H-bridge (10). The transconductance circuit (16) operates to pull current from the inductive component (14) to ground (30) when the inductive load (14) sources current to a body diode of the high side transistor (20). The transconductance circuit (16) creates a regulated voltage to the gate (25) of the low side transistor (24) to cause the low side transistor (24) to conduct the current away in a regulated manner from the inductor (14) and the high side transistor (20) to ground (30).

Abstract: An H-type bridge circuit includes four transistors, two resistors, and a write head. A write current supplied from a current supply circuit including a first of the transistors and resistors flows through the write head and is received in a current receiving circuit including a second of the resistors and a fourth of the transistors, and another write current supplied from a current supply circuit including the second of the transistors and the second resistor flows through the write head and is received in a current receiving circuit including the first of the resistors and the third of the transistors. Impedance of the write head matches an output impedance of the current supply circuit and matches an input impedance of the current receiving circuit.

Abstract: A system and apparatus for controlling a motor or other multi-directional load using an H-bridge circuit having self-latching, high side switches. Thyristors are used as high side switches, and arranged to self-latch. The H-bridge thyristors are also arranged to automatically discontinue the triggering gate current upon the thyristor switch closing to conduct current, which advantageously terminates the flow of gate current as soon as it is no longer required.

Abstract: A half-bridge circuit including a low-side drive module (110) and a high-side drive module (210) for driving respective lower (T1) and upper (T2) transistors. Each drive module (110, 210) is a charge trap circuit in that the low-side drive module (110) drives the low-side transistor (T1) with the charge on a capacitive load (C), and the high-side drive module (210) alternately recharges the capacitive load (C) as it is driven by a high-voltage supply. Each charge trap circuit (110, 210) also includes a diode (D1, D2) that prevents unintentional loss of charge on a gate of a driven transistor (T1, T2), and a zener diode (Z1, Z2) that clamps the gate voltage at a safe level. In this manner, the half-bridge circuit is efficiently driven without the need of an auxiliary power supply.

Abstract: A supply assembly for an LED lighting module includes a control switch for supplying a constant current to the LED lighting module. A dual switching signal composed of low frequency bursts of high frequency pulses is applied to the control switch. By varying the low frequency component of the dual switching signal, the average current through the LED lighting module may be varied in order to vary the light intensity outputted by the LED lighting module.

Abstract: A circuit for driving a current into an inductor, which circuit includes at least one main capacitor, a power supply operably connected to the main capacitor, the inductor, and at least two pairs of switches connecting the main capacitor to the inductor, whereby the connection of the main capacitor to the inductor is made in either polarity. Current is driven into the inductor by applying a current to the main capacitor, applying a voltage to the inductor from the main capacitor resulting in generation of inductive energy, and recapturing the inductive energy with the main capacitor at the end of a cycle.

Abstract: The invention relates to an integrated high power sine wave carrier circuit for outputting a low distortion high power sine wave. The circuit is used for antennas, and especially for antennas in automotive appliances. The circuit comprises a H-bridge (2) with matched power transistors (4, 6, 8, 10), a sine generator (24) for driving the H-bridge and a regulator (22) for sensing the power applied to the antenna and controlling the current amplitude of the sine wave output by the sine generator. The circuit operates under partial time-working, whereby the integration circuit is turned on or off. The circuit therefore comprises a shutdown pin, for shutting the circuit down in order to allow cooling. The partial time operation allows the circuit to be integrated on a single die.

Abstract: A high-frequency resonant sine wave DC to AC inverter suitable for use in a personal computer (PC) power supply includes a full-bridge inverter, a resonant circuit, a phase shift modulation circuit, and a resonant gate driver. The resonant gate driver provides sinusoidal gate drive signals to the full-bridge inverter enabling highly efficient operation on the inverter.

Abstract: The circuit has a push-pull end stage which acts as an amplifier stage for digital signals. The push-pull end stage has two n-channel MOS transistors which function as source followers and two p-channel MOS transistors which also function as source followers. The gate terminals of the respective n-channel MOS transistors and p-channel MOS transistors are each controlled by an operational amplifier through drivers. A voltage that determines the setpoint value of the high level of the output of the push-pull end stage is present at the non-inverting input of one operational amplifier and a voltage that determines the low level of the output of the push-pull end stage is present at the inverting input of the other operational amplifier.

Abstract: A resonant gate driver circuit suitable for driving MOS-gated power switches in high-frequency applications recovers gate drive energy stored in the gate capacitance of the power switches, resulting in substantially lossless operation. The resonant gate driver circuit provides bi-polar gate control signals that are compatible with PWM operation.

Abstract: A high density, high speed, and low power circuit scheme is presented for vector switching port applications for advanced IC design. Embodiments exhibit superior area-delay-power properties. The technique benefits a wide range of product applications ranging from high speed high bandwidth router to low power portable computing hardware. 5.0 TBPS peak traffic can be supported for an on-chip vector port.

Abstract: An inductive load driving circuit, formed in an integrated circuit device, includes first, second, third, and fourth switching transistors, and a guardring. The first switching transistor is connected between a first power supply potential point and a first output terminal. The second switching transistor is connected between the first power supply potential point and a second output terminal. The third switching transistor is connected between the first output terminal and a second power supply potential point. The fourth switching transistor is connected between the second output terminal and the second power supply potential point. One of the third switching transistor and the fourth switching transistor is turned on or off depending on a power supply direction in which power is supplied to an inductive load connected between the first output terminal and the second output terminal.

Abstract: A diode element circuit uses a junction between the base and collector of a vertical type PNP transistor as a diode, and is further designed that a reverse bias voltage is applied between base and emitter of a parasitic PNP transistor in the vertical type PNP transistor, thereby, a diode having a small leakage current and a high break down voltage is realized without necessitating an additional manufacturing process.

Abstract: A write driver to supply current to an induction load, including an H-bridge circuit coupled to the induction load to switch the current between a first current path and a second current path, said induction load operative to generate an undershoot current, and an undershoot circuit to control the undershoot current based on a comparison of a reference voltage and a flyback voltage. The undershoot circuit is connected to bases of the transistors of the lower H-bridge circuit.

Abstract: The invention provides a load driver circuit including at least one FET such as MOSFET QX, QY, and QZ, controlled by a control circuit providing gate control voltage to the load driving FET by means of a feedback loop connecting the FET and the control circuit, without utilizing any resistor connected in series with the load to detect the load current. This is done by detecting, as a measure of the load current Io, the drain-source voltage drop of the load driving FET QX-QZ by means of detection means 13, 14, and 15. Because the control circuit utilizes no resistor, but utilizes a MOSFET instead, in detecting load current Io, the invention advantageously has a compact form, requiring only a minimum space for connection with external components, cuts down significant power loss that would be otherwise entailed by a current detection resistor, is capable of detecting the load current at high precision, thereby allowing precise control of the load current, and provides an improved wide output dynamic range.

Abstract: A HDD write driver circuit (30) having two sets of boost devices (Q1, M2, and Q2, M1) which are temporarily turned on during a current reversal to boost the normal current and increase the differential transient voltage across the coil (LS) while decreasing the TRTF. During a current reversal cycle, one set of transistors is turned on while the other set is left off. The on set to pulls the node at one end of the coil substantially to the positive rail, and pulls the other node at the other end of the coil substantially to the lower rail (Vee). The boost FETs (M1, M2) are preferably large PMOS devices that must be driven hard to achieve a quick transient switching time. Advantageously, when one of the PMOS FETs (M1, M2) are on, the associated series resistor (RS) is bypassed.

Abstract: An inverter circuit has first and second input terminals adapted to be connected to the voltage. First and second switching devices are connected in series at a first junction. The first switching device connected to the first input terminal, and the second switching device adapted to be connected to one side of the load. Third and fourth switching devices connected in series at a second junction. The third switching device is connected to an opposite side of the load, and the fourth switching device connected to the second input terminal. A voltage divider is connected between the first and second input terminals and provides an output potential. A first current steering device is connected between the potential from the voltage divider and the first junction. A second current steering device is connected between the potential from the voltage divider and the second junction.

Abstract: A balanced transformer-less (BTL) power drive circuit comprises a push-pull type output transistor section connected with a main power supply PowVcc, and an input control section connected with an auxiliary power supply for providing the output transistor section with a control signal. The potential of the auxiliary power supply is selectively set equal to or above the supply potential of the main power supply, depending on the requirements for the dynamic range of the power drive circuit. In accord with the potential of the auxiliary power supply thus set, the output reference potential Vref is set to the medium of the dynamic range, thereby ensuring the linearity of the input-output characteristic of the drive circuit, irrespective of the selected level of the auxiliary power supply.

Abstract: A circuit for providing a current through a load includes a first bridge circuit connectable to the load. The first bridge circuit selectively applies a voltage across the load. A second bridge circuit is connected to the first bridge circuit and is connectable to a power supply. The second bridge circuit selectively applies voltage to terminals of the first bridge circuit.

Abstract: The invention relates to an integrated high power sine wave carrier circuit for outputting a low distortion high power sine wave. The circuit is used for antennas, and especially for antennas in automotive appliances. The circuit comprises a H-bridge (2) with matched power transistors (4, 6, 8, 10), a sine generator (24) for driving the H-bridge and a regulator (22) for sensing the power applied to the antenna and controlling the current amplitude of the sine wave output by the sine generator. The circuit operates under partial time-working, whereby the integration circuit is turned on or off. The circuit therefore comprises a shutdown pin, for shutting the circuit down in order to allow cooling. The partial time operation allows the circuit to be integrated on a single die.

Abstract: An H-bridge driver has a drive signal generating circuit for generating a square-wave signal as a drive signal. The H-bridge driver also has a waveform shaping circuit for blunting the waveform of the drive signal at the rising and trailing edges thereof. The waveform shaping circuit has a first circuit for generating, in a rising period of the square-wave signal fed thereto, a first current having a positive peak at the center of the rising period, a second circuit for generating, in a trailing period of the square-wave signal fed thereto, a second current having a negative peak at the center of the trailing period, and a capacitor to which the first and second currents are fed. The waveform shaping circuit outputs the voltage across the capacitor as its output voltage.

Abstract: A circuit arrangement, provided for driving a load by two transistors connected in series with the load, comprises a first transistor (M1) provided with a control input adapted to receive a first control signal, and with a conductive path to be controlled in dependence on the first control signal, the current flowing via the conductive path being limited to a first maximum value (Ilim(M1). Further the circuit arrangement comprises a second transistor (M2) provided with a control input adapted to receive a second control signal, and with a conductive path to be controlled in dependence on the second control signal, the current flowing via the conductive path being limited to a second maximum value (Ilim(M2). The first maximum value (Ilim(M1) is larger than the second maximum value (Ilim(M2). The load (R) is connected in series with the conductive paths of the first and second transistors (M1,M2).

Abstract: The bridge circuit for switching high currents has n (n=a natural integer) lowside and highside switches (T1 to T4) in the form of vertically structured MOS transistors on two separate chips. The highside switch is formed using DMOS technology. The lowside switches are formed using common-source technology with the source arranged on the rear side of the chip and the drain arranged on the front side of the chip. The drain is connected to the source of the associated highside switch.

Abstract: An inverter circuit has first and second input terminals adapted to be connected to the voltage. First and second switching devices are connected in series at a first junction. The first switching device connected to the first input terminal, and the second switching device adapted to be connected to one side of the load. Third and fourth switching devices connected in series at a second junction. The third switching device is connected to an opposite side of the load, and the fourth switching device connected to the second input terminal. A voltage divider is connected between the first and second input terminals and provides an output potential. A first current steering device is connected between the potential from the voltage divider and the first junction. A second current steering device is connected between the potential from the voltage divider and the second junction.

Abstract: A write driver for an inductive load includes load terminals for connection to an inductive load, and an impedance-matched driver circuit responsive to first and second control signals to supply a drive current through the load in respective first and second directions. The inductive load includes an inductive write head and a transmission line of predetermined impedance connected to the write head for connection to the first and second load terminals. Ringing is suppressed by the impedance-matching of the driver circuit to the transmission line connecting the load to the terminals.

Abstract: One end of a current source transistor is connected to a standard power source (VDD), and the gate of the first current source transistor is applied with a bias potential B1 for stabilizing fluctuations in current. The gate of a current source transistor is connected to the other end of the current source transistor, and the other end of the current source transistor is connected to GND. Output NMOS transistors are connected in series between the current source transistors. Output NMOS transistors are connected in series between the current source transistors, while the output NMOS transistors are connected in parallel with said the output NMOS transistors. An output terminal is provided between the output NMOS transistors, and an output terminal is provided between the output NMOS transistors. A terminal resistance is provided between the output terminals. Output NMOS transistors and NMOS transistors, which compose clamp circuits, are provided at both ends of the terminal resistance.

Abstract: In a write driver circuit for switching the direction of a write current passing through a magnetic head or the like having an inductance component, an H-shaped bridge circuit is formed by using four NPN transistors in order to switch the write current at a high speed. Four switching means for controlling the base potentials of the four NPN transistors are provided and two switching means for rapidly decreasing the base potential of one of the two NPN transistors on the power source side, which is turned off when the write current passing through the magnetic head is switched are provided, thereby widening a voltage difference occurring between both terminals of the magnetic head.

Abstract: An impedance matching circuit for a write driver matches the differential impedance of the winding of the write head and the transmission line to the write head. The impedance matching circuit includes a resistor connected between a node and a current switch of the write driver. The resistor has an impedance value matching the differential impedance value of the transmission line and head. During quiescent or steady state operation, the write driver provides a DC write current in a selected direction through the winding, and the resistor matches the differential impedance of the head and transmission line. During switching to reverse direction of write current through the winding, however, the resistor dampens voltage swings at the node to minimize current undershoot. Optionally, a capacitor is in parallel with the resistor to short-circuit the resistor during switching to improve the rise-time characteristics of the current reversal, but at a sacrifice of the impedance characteristics during switching.

Abstract: A write current driving circuit in which drains of the transistors A1 and B1 are commonly connected to the base of the transistor T1, drains of the transistors C1 and D1 are commonly connected to the base of the transistor T2, inverted signal of the input signal into the transistors C1 and D1 is inputted into the transistors A1 and B1. Therefore, the transistors T1 and T2 can speedily be switched ON/OFF with suppressed power consumption. Transistors A2, C2 and transistors B2, D2 are connected in parallel with the transistors A1, C1 and NMOS transistors B1, D1 respectively, and the transistors A2, C2, B2, and D2 are turned ON only for a specified period of time immediately after the transistors T1 and T2 are switched ON/OFF.