Abstract: A circuit and method to drive an H-bridge circuit are disclosed. The H-bridge circuit uses NMOS transistors for both the upper and lower sets of transistors. An inductive head is coupled between the terminals of the transistors. When a logic signal is received, one of the upper transistors is driven. The upper transistor selected to be driven is responsive to the logic signal. A corresponding lower transistor is also driven, forcing current through the inductive head in a first direction. The driving circuit for the lower transistors includes a programmable circuit structured to capacitively couple the output of the driving circuit to a pull-up voltage, thereby allowing the amount of current forced through the inductive head to be maximized for optimum data transfer. Within the programmable voltage boost circuit are several logic gates, each coupled to a capacitor of differing value.

Abstract: A current detection circuit having a voltage conversion section for converting current flowing to a load to a voltage; an amplifier section having an operational amplifier for amplifying the voltage converted by the voltage conversion section; a constant current circuit section having a constant current circuit connected to an input of the operational amplifier; and a current detection section for detecting a load current from a voltage amplified by the amplifier section. The constant current circuit section shifts the input offset voltage to the operational amplifier of the amplifier section. As a result, a dead zone in which a load current cannot be detected due to the input offset voltage of the operational amplifier can be eliminated.

Abstract: An integrated full bridge circuit includes four transistors divided into two series-connected pairs of transistors each forming a half bridge circuit. Resistor elements each connect a respective one of the pairs of transistors to a reference potential. Other resistor elements are each connected to a respective one of two separate supply terminals inside a housing. Each of the other resistor elements is connected to one of the transistors of a respective one of the pairs of transistors at a junction. Driver transistors each have a load path with two connections and a type complementary to the transistors connected to the other resistor elements. One of the connections is connected upstream of the control terminal of a respective one of the transistors connected to the other resistor elements. The other of the connections in each of the half bridge circuits is connected to the junction in the other of the half bridge circuits. The advantage is power loss reduction.

Abstract: A write driver for an inductive load includes load terminals for connection to an inductive load, and a driver circuit responsive to first and second control signals to supply a drive current through the load in respective first and second directions. A voltage-mode H-bridge connected to the load terminals is operable to selectively supply a voltage across the load terminals and head. Program means operates the voltage-mode H-bridge for a predetermined time period following initiation of the respective first and second control signal to provide a voltage across the load terminals which quickly raises the write current to a steady state condition. Ringing is suppressed by employing an impedance-matched H-bridge for the driver circuit, the impedance-matched H-bridge having an impedance matched to the impedance of a transmission line connecting the load to the terminals.

Abstract: A power amplifier has an amplifier module and a pole changer module connected to the amplifier module, and during the operation of the power amplifier an amplifier current flows in a single current direction between the amplifier module and the pole changer module. The pole changer module optionally provides the amplifier current with unchanged current direction or with reversed current direction, as output current of the power amplifier. A nuclear spin tomography apparatus contains at least one such power amplifier. Such a power amplifier exhibits the required efficiency quantitatively and qualitatively, with low outlay and low cost.

Abstract: A method for improving the efficiency of H-bridge electrical switching devices that drive a capacitive load such as electroluminescent lamps, liquid crystal devices and piezoelectric transducers. The method provides for discharge steps that first discharge the capacitive load to a difference in voltage potential of zero (0) volts before re-charging from the opposite side. By implementing the method, the DC power supply will only be required to charge the capacitive load from zero (0) volts to +Vcs volts, rather than +Vcs volts to -Vcs volts as in prior art. With less energy required from the DC power supply to accomplish the same result, a more efficient switching network is achieved.

Abstract: A write driver in an H configuration for magnetic inductive write heads characterized by having both arms in the bottom half of the driver conduct current all the time, with only the top devices being switched. In this configuration there is no need to synchronize the switching of the top and bottom halves of the H-driver. Furthermore, the device half being switched can be optimized for speed independent of the properties of the other H-driver half.

Abstract: A circuit for switching between supply voltages and in particular for non-volatile flash memory devices and of the type comprising a first and a second circuit branch each incorporating a pair of transistors connected in series provides that at least one branch of the circuit be structured with a bridge circuit made up of P-channel MOS transistors. The bridge is made of a first and a second pairs of transistors connected between a first supply voltage reference and a common node. The first pair comprises transistors bigger than the transistors of the second pair while between the transistors making up the second pair is inserted a pair of resistors. Between the pair of resistors there is an interconnection node connected to a corresponding interconnection node between the transistors of the first pair.

Abstract: A voltage boosting circuit for an "H-driver," providing for each "pull-up" switch in the H-driver a switching shunt that charges a capacitor from a supply voltage when the "pull-up" switch is open and couples the capacitor directly to the write head when the "pull-up" switch is closed. The side of the capacitor which is not directly coupled to the write head is coupled to the data signal (or its inverse, in the case of the capacitor for the otherwise identical circuit serving the parallel half of the "H-driver") through a buffer which sets the voltage at the signal level (or its inverse), thereby dumping the charge to the write head and elevating the voltage of the write head significantly above the supply voltage. The identical circuit serving the parallel half of the "H-driver" similarly boosts the negative going transition voltage.

Abstract: A circuit (10) and method for limiting output currents in a circuit having at least two output drivers (12,14) with outputs (16,18) on which first and second out-of-phase output currents are produced includes a current source (34) and a first current mirror (28). The first current mirror (28) has a first side (30) connected to sense a current in the output drivers and has a second side (32) connected to the current source (34). A magnitude of the current in the output drivers (12,14) produces a proportional voltage at a connection (52) between the second side (32) and the current source (34). First and second control transistors (40,42) are each connected to provide a control current to control respective output currents of the drivers (12,14), the first and second control transistors (40,42) being connected to receive an input signal (46) to pass the control current.

Abstract: A current detecting resistor is inserted in an H-bridge circuit constructed to cause the flow of a current to an inductive load in both forward and reverse directions by four semiconductor switching elements and flywheel diodes respectively connected in reverse parallel to the semiconductor switching elements. An inductive load driving method and an H-bridge circuit control device prevent an erroneous operation caused by noise generated at the current detecting resistor. When a current flowing through the inductive load is controlled by a detection voltage generated by the current detecting resistor, the value of the detection voltage is ignored immediately after the connection of the inductive load to a power source. There is no risk that an erroneous operation is caused by a rush current and/or a through current.

Abstract: A driving circuit has first and second output terminals for connection with a load, for supplying the load with a constant voltage changing in polarity at predetermined timing, through the output terminals. A bridge circuit has first and second output nodes connected, respectively, to the first and second output terminals. A selector circuit selectively drives a plurality of current changeover switching elements of the bridge circuit. First and second differential amplifier circuits have first input terminals supplied with a predetermined reference voltage and second input terminals connected, respectively, to the first and second output nodes, and a common output terminal. A switching circuit selectively connects the first and second differential amplifier circuits to a power source in response to selective driving of the current changeover switching elements by the selector circuit.

Abstract: A troubleshooting circuit for locating malfunctions while driving an electric load by means of a bridge stage (M1, M2, M3, M4) which is connected between ground (GND) and the power supply (+VCC) in series with first and second resistors (Rsl, Rsh), respectively. First (COMP1) and second (COMP2) threshold comparators are coupled to the first resistor to sense a short-circuit to battery (+VCC) and an open-load condition, respectively. Coupled to the second resistor is a third threshold comparator (COMP3) adapted to sense a short-circuit to ground. The output signals from the comparators are sampled through flip-flops (FF1, FF2, FF3, FF4, FF5, FF6) upon a transistor in the bridge being switched to the off state.

Abstract: A write driver, having a pair of head pins for connection to a write head, includes two push-pull buffer circuits connected respectively between first and second pull-up resistors and the control nodes of first and second upper drive transistors. The buffer circuits selectively charge and discharge the inherent capacitances of the upper drive transistors, thereby accelerating their turn on and turn off without diminishing head swing. Moreover, connecting the buffer circuits between the pull-up resistors and the upper transistors effectively isolates, or buffers, the pull-up resistors from the self-inductance voltages of the write head, reducing glitching in the write-head output signal.

Abstract: A half-bridge circuit where the transistors comprising the half-bridge are electronically interlocked--precluding cross-conduction; and high-side voltage generation and logic level translation are integral to the interlock mechanism.

Abstract: An "H" type amplifier circuit uses at least two current mirrors for alternately feeding current into the load in one direction and the other direction. In order to accelerate the turn-on of the current mirrors, a capacitance is associated with each of the two current mirrors. Each capacitance is alternately coupled in parallel with the input of its associated current mirror when this current mirror delivers current, and is coupled to the supply voltage terminals when this current mirror delivers no current. The operation is effected by means of a set of switches.

Abstract: A field relaxation region of the second conductivity type is formed between the base region and a drain electrode contact portion at which the drain region contacts with a drain electrode but distanced from both the base region and the drain electrode contact portion and the field relaxation region is also separated via the drain region from the laterally extending portion of the semiconductor isolation region to form a drain current channel region between the field relaxation region and the laterally extending portion of the semiconductor isolation region and further the field relaxation region is electrically connected via an interconnection to the source region and the vertically extending portion of the semiconductor isolation region so that the field relaxation region and the semiconductor isolation region have the same potential as the source region whereby if the lateral MOS field effect transistor is reverse-biased by a voltage, then a first space charge region is formed which extend from a first p-n

Abstract: A rectifying device comprising of a SRMOS, an inductor, and a control circuit is disclosed. The SRMOS has a gate, a drain, and a source. The gate of the SRMOS is connected to the output of the control circuit. The inductor is connected to the drain of the SRMOS. The control circuit uses two sense traces for determining the voltage (or current) passing between the inductor (that is connected to the drain) and the source of the SRMOS. Upon sensing a forward characteristic (voltage or current), the SRMOS forward biases to allow current to flow through the SRMOS. Upon sensing a reverse characteristic (voltage or current), the SRMOS reverse biases to cut off any current flow. Hysteresis is used in setting the forward biasing threshold voltage and the reverse biasing threshold voltage for the SRMOS. In reverse biasing and forward biasing the SRMOS, V.sub.gs is stepped (or curved) controlled to avoid false turn ON/OFF of the SRMOS.

Abstract: A phase current reconstruction circuit (10) senses and reconstructs a phase current in a phase bridges (12A). An amplifier (32) in a phase current reconstruction element (22) amplifies a voltage signal across a sensing resistor (18). The amplified voltage signal is transmitted to a sample and hold circuit (34), which reconstructs the phase current in the phase bridge (12A). An over-current comparator (36) compares the amplified voltage signal with a predetermined reference voltage to detect an over-current in the phase bridge(12A). If the over-current in the phase bridge (12A) is detected, an over-current latch (38) interrupts the pulse width modulation signal from a microcontroller (26) to a power switch (16A) in the phase bridge (12A), thereby switching off and protecting the power switch (16A) from damage that may be caused by the over-current.

Abstract: When an IGBT element (9) is turned off and an IGBT element (19) is turned on, capacitors (1, 2) are charged by a current successively passing through the capacitor (1), a resistive element (4), a diode (5), the capacitor (2) and an intermediate wire (32) from a high-potential dc bus (30). At the same time, a capacitor (11) is discharged by a current successively passing through a diode (17), a resistive element (16) and the capacitor (11) from a low-potential dc bus (31) to flow to the intermediate wire (32). When the IGBT element (9) is turned on and the IGBT element (19) is turned off, on the other hand, the capacitors (11, 12) are charged and the capacitor (1) is discharged. The above is so repeated as to maintain source voltages of driving circuits (8, 18) at values exceeding constant levels. Thus, a power circuit for a driving circuit is formed by a simple circuit element.

Abstract: A power stage of quasi-complementary symmetry, including a common-source FET and a common-drain FET, with a reduced absorption of current under the conditions of high impedance of the output. The driving node of the upper (common-drain) transistor from is decoupled from the output node of the stage, preventing the current generator Id, which discharges the control node, from absorbing current from the load connected to the output stage, during a phase of high output impedance. This is preferably realized by using a field effect transistor which has its gate connected to the output node of the stage, and is connected to provide the current drawn from the discharge generator of the driving node of the upper common-drain transistor, absorbing it from the supply node VDD instead of absorbing it from the voltage overdriven node Vb. This alternative solution avoids excessive loading of the high-voltage supply, and is particularly useful when the overdriven node Vb drives multiple output stages.

Abstract: A write driver control circuit controls the voltage level input to a switch circuit, providing increased range for head voltage swings and fast current switching, providing a write driver circuit with a variable voltage level which tracks the write current, as well as temperature and process variations, but which is independent of power supply voltages.

Abstract: An electrical current-switching driver circuit is provided for switching current through an inductive memory write head on a memory storage device. The driver circuit provides means for reducing distortion in the output current waveform and for minimizing occurrences of breakdown in the switching transistors in the circuit. The circuit uses AC coupling circuitry and small DC holding currents to linearize the current transition during switching transients, thereby eliminating discontinuities which would otherwise appear in the head current output waveform, midway through the switching transients.

Abstract: A write driver for a magnetic transducer having a three-terminal inductive coil includes first and second voltage sources, a write current source, and a switching network having first and second switching transistors connected between the second voltage source and the respective first and second taps. The switching network responds to respective first and second inputs to switch the write current between respective first and second taps. Active pull-down subcircuits operate to alternately supply base current to the respective first and second switching transistors to charge parasitic capacitances of the respective switching transistors and to alternately sink base current from the respective switching transistors to discharge parasitic capacitances.

Abstract: In a half-bridge output stage employing a complementary pair of output power transistors, each driven through an integrating stage for controlling the slew-rate, a single integration capacitance is conveniently shared by the two integrating stages that drive the power transistors. A pair of switches connect the single integrating capacitance to the input of either one of the two integrating stages and are controlled by a pair of nonoverlapping signals that have a certain advance with respect to the pair of logic signals that drive the half-bridge stage. In the case of a driving system of a multi-phase machine, the two configuring switches of the single integration capacitor may be driven by a pair of control signals that drive a different phase winding of the multi-phase machine, thus eliminating the need for dedicated circuitry for generating said pair of anticipated signals to control the configuration switches.

Abstract: This is a detector system comprised of a differential driver circuit, a driver output stage and splitter circuit and a multiplexor. The driver circuit employs a bridge circuit that converts input logic voltages to lower voltage differential outputs by utilizing a pair of current switch transistors coupled to the bridge circuit. The bridge circuit is comprised of cross coupled transistors whose inputs are coupled to matched true and complement input logic voltages that swing between zero volts and the power supply voltage. The bridge transistors convert the differential logic input voltage swings to smaller values that are compatible with driving the splitter and multiplexor circuits coupled thereto. The driver circuit and the splitter circuit share the driver output transistors which are arranged in parallel pairs.