Abstract: A switching converter circuit for switching one end of an inductor therein between plural voltages according to a pulse width modulation (PWM) signal to convert an input voltage to an output voltage. The switching converter circuit has a driver circuit including a high side driver, a low side driver, a high side sensor circuit, and a low side sensor circuit. The high side sensor circuit is configured to sense a gate-source voltage of a high side metal oxide semiconductor field effect transistor (MOSFET), to generate a low side enable signal for enabling the low side driver to switch a low side MOSFET according to the PWM signal. The low side sensor circuit is configured to sense a gate-source voltage of a low side MOSFET, to generate a high side enable signal for enabling the high side driver to switch a high side MOSFET according to the PWM signal.

Abstract: According to the present disclosure, a bidirectional switch circuit includes a first semiconductor device including a first backside electrode electrically connected to a first pattern and a first upper surface electrode, a second semiconductor device including a second backside electrode electrically connected to a second pattern and a second upper surface electrode, a first diode including a first cathode electrode electrically connected to the first pattern and a first anode electrode, a second diode including a second cathode electrode electrically connected to the first pattern and a second anode electrode, first wiring electrically connecting the first upper surface electrode and the second anode electrode and second wiring electrically connecting the second upper surface electrode and the first anode electrode, wherein the first upper surface electrode, the second upper surface electrode, the first anode electrode and the second anode electrode are electrically connected to each other.

Abstract: A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.

Abstract: Devices having one primary transistor, or a plurality of primary transistors in parallel, protect electrical circuits from overcurrent conditions. Optionally, the devices have only two terminals and require no auxiliary power to operate. In those devices, the voltage drop across the device provides the electrical energy to power the device. A third or fourth terminal can appear in further devices, allowing additional overcurrent and overvoltage monitoring opportunities. Autocatalytic voltage conversion allows certain devices to rapidly limit or block nascent overcurrents.

Abstract: A wiring of a semiconductor switch having a gate, a collector or a drain, and an emitter or a source, includes a first arrangement having a first capacitor connected in series with a parallel connection having a first resistor and a first diode. The first arrangement is connected between the gate and the collector or drain, wherein the first diode is connected away from the gate in a flow direction. A second arrangement is connected in parallel with the first arrangement and includes a second capacitor connected in series with a parallel connection having a second resistor and a second diode, wherein the second diode lies toward the gate in the flow direction.

Abstract: A bidirectional flat clamp device includes a first device node and a second device node. The bidirectional flat clamp device also includes a first switch and a second switch coupled in series between the first and second device nodes. The bidirectional flat clamp device also includes at least one switch driver coupled to the first and second switches. The bidirectional flat clamp device also includes a first current path between the first and second device nodes, the first current path having a first diode, a voltage sensor circuit, and a second diode. The bidirectional flat clamp device also includes a second current path between the first and second device nodes, the second current path having a third diode, the voltage sensor circuit, and a fourth diode.

Abstract: According to one aspect of embodiments, a drive circuit of a normally-ON transistor includes: a normally-OFF transistor that includes a main current path connected in serial to a main current path of the normally-ON transistor; and a buffer circuit that supplies, to a gate of the normally-ON transistor, a control signal for controlling turning ON and OFF of the normally-ON transistor, whose high-voltage side and low-voltage side are biased by a bias voltage supplied from a power source unit.

Abstract: An example method may include generating an alternating current (AC) output at a power source within a borehole in a subterranean formation. An electrical component may receive a direct current (DC) output from a converter circuit coupled to the power source and the electrical component. One or more measurements corresponding to the power source, the converter circuit, the electrical component, or a protection circuit coupled to the converter circuit may be received. Blocking devices within the protection circuit may be selectively caused to block current flow in the converter circuit based, at least in part, on the one or more received measurements.

Abstract: An example system comprises: a power transistor comprising a gate, a first terminal, and a second terminal; a transistor comprising a gate, a first terminal, and a second terminal coupled to the gate of the power transistor; a capacitive divider coupled to the first terminal of the power transistor and the gate of the transistor; and a resistive divider coupled to the first terminal of the power transistor and the gate of the transistor.

Abstract: A semiconductor device according to an embodiment is a semiconductor device including: a normally-off transistor having a first source, a first drain, and a first gate; a normally-on transistor having a second source electrically connected to the first drain, a second drain, and a second gate; a first capacitor having a first end and a second end, the second end electrically connected to the second gate; a first diode having a first anode electrically connected between the second end and the second gate, and a first cathode; a first resistor electrically connected between the first end and the first gate; a second diode having a second anode electrically connected to the first end, and a second cathode electrically connected to the first gate, the second diode provided in parallel to the first resistor; a gate drive circuit electrically connected to the first resistor and the second anode, a reference potential wiring being connected to the gate drive circuit and the first source; and a second capacitor havin

Abstract: A switching unit of an embodiment includes a first switching element of normally-on type, a second switching element of normally-off type having a non-reference potential side conductive terminal connected to a reference potential side conductive terminal of the first switching element, a resistive element having one end connected to a conduction control terminal of the first switching element; a series capacitor connected between the other end of the resistive element and a conduction control terminal of the second switching element; and a diode having an anode connected to the other end of the resistive element and a cathode connected to a common junction of the first switching element and the second switching element.

Abstract: A semiconductor device includes a first transistor and a second transistor connected in series between a first voltage source and a second voltage source. A diode is connected between a gate of the first transistor and the second voltage source. A capacitor is connected to the gate of the first transistor. A first driver is connected to the gate of the first transistor through the capacitor. A second driver is connected to a gate of the second transistor. A threshold voltage of the second transistor is higher than a threshold voltage of the first transistor.

Abstract: An integrated circuit includes a power transistor and a drive circuit. The drive circuit includes at least one drive transistor. The power transistor and the at least one drive transistor are integrated in a common semiconductor body. The power transistor includes at least one transistor cell with a source region, a body region, a drift region, a drain region, and a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric. The at least one drive transistor includes active device regions integrated in a well-like structure comprising dielectric sidewall layers.

Abstract: A circuit includes first and second semiconductor switches each having a load path and control terminal and their load paths connected in series. At least one of the first and second switches includes a first semiconductor device having a load path and a control terminal, the control terminal coupled to the control terminal of the switch. A plurality of second semiconductor devices each have a load path between a first load terminal and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices. One of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device.

Abstract: A switching unit of an embodiment includes a first switching element of normally-on type, a second switching element of normally-off type having a non-reference potential side conductive terminal connected to a reference potential side conductive terminal of the first switching element, a series capacitor connected between a conduction control terminal of the first switching element and a conduction control terminal of the second switching element, and a diode having an anode connected to the conduction control terminal of the first switching element and a cathode connected to a common junction of the first switching element and the second switching element.

Abstract: The present invention provides a GOA circuit with forward-backward scan function. In the GOA unit circuit of every stage, the pull-up controlling module comprises two thin film transistors respectively controlling the forward, backward scans. With proper received signals, as the thin film transistor controlling the forward scan is on, the GOA circuit performs forward scan from the GOA unit circuit of the first stage to the GOA unit circuit of the last stage, and as the thin film transistor controlling the backward scan is on, the GOA circuit performs backward scan from the GOA unit circuit of the last stage to the GOA unit circuit of the first stage. Thurs, the GOA circuit possessing functions of forward scan and backward scan at the same time can be achieved to expand the application field of the GOA circuit.

Abstract: Various solid-state circuit breakers and related circuits are presented herein. These include, among other things, a common node bidirectional solid-state circuit breaker (BDSSCB) having diodes connected between terminals of its switches, a shunt voltage actuated driver (SVAD) circuit for use with a BDSSCB, a SVAD circuit for use with a unidirectional solid-state circuit breaker (UDSSCB), a bipolar current actuated driver (BCAD) for use with a BDSSCB, and a multi-directional solid-state circuit breaker (MDSSCB).

Abstract: According to one aspect, a transistor gate drive comprises a first input configured to be coupled to a DC voltage source, a second input configured to receive a control signal, a third input configured to couple to a ground connection, a transformer, a first switch configured to couple the first input to a first end of a primary winding of the transformer in response to receipt of the control signal, and to decouple the first input from the first end of the primary winding in response to the receipt of the control signal, a second switch configured to couple a second end of the primary winding to the third input in response to receipt of the control signal, and to decouple the second end of the primary winding from the third input in response to the receipt of the control signal.

Abstract: A radio frequency (RF) coil assembly for use in magnetic resonance includes a radio frequency coil (42, 100) and an electronic switch (28) which switches between open and closed states to detune and tune the coil to a preselected resonance frequency. Each electronic switch includes at least one field effect transistor (FET) (70) and a bias network (72).

Abstract: The invention relates to a control device (1) employed in a switched electrical power supply system to control a DC/DC converter of said switched electrical power supply system, said control device comprising a first input terminal (A) and a second input terminal (B), a first transistor (T1) connected via its source to the second input terminal (B) and a second transistor (T2) furnished with a gate (G) and connected via its drain (D) to the first input terminal (A), and via its source (S) to the first transistor (T1), the control device comprising a control assembly connected to the gate (G) of the second transistor (T2) and to the second input terminal (B) and comprising a capacitor (Ca) and a first Zener diode (Dz1) connected in series to said capacitor (Ca) and a second Zener diode (Dz2) connected between the gate (G) and the source (S) of the second transistor (T2).

Abstract: An apparatus for an integrated clock gating cell is provided. The apparatus includes a logic gate that receives an unbuffered enable signal (E), a scan test enable signal (SE), and outputs an inverted enable signal (EN); a first transmission gate that receives E, SE, and EN; a second transmission gate that is connected to the first transmission gate and receives a clock signal (CK) and an enabled and inverted clock signal (ECKN); a first transistor having terminals connected to a power supply voltage (VDD), an output of the logic gate, and the first transmission gate respectively; a second transistor including terminals connected to the first transmission gate and VDD respectively; and a latch including terminals connected to the second transmission gate and the second transistor respectively.

Abstract: The invention relates to a control device intended to be employed in a switched electrical power supply system, said system being able in particular to be employed in a variable speed drive to power its electronics. The control device comprises a first transistor intended to receive control signals originating from a control unit and a second transistor connected in series with the first transistor and provided with a floating-control gate.

Abstract: A power voltage generating apparatus supplies a power voltage to a plurality of pixel circuits of a display apparatus. The power voltage generating apparatus includes: a high voltage converter to generate a high voltage; a low voltage converter to generate a low voltage; a switching circuit to alternately output the high voltage and the low voltage at a power voltage terminal as the power voltage; and a discharging unit coupled to the power voltage terminal and configured to discharge the power voltage terminal until a voltage output is converted from the high voltage to the low voltage by using the switching circuit.

Abstract: A circuit arrangement includes a first semiconductor device having a load path and a number of second semiconductor devices. Each second semiconductor device has a control terminal and a load path between a first load terminal and a second load terminal. The second semiconductor devices have their load paths connected in series and connected in series with the load path of the first semiconductor device. Each of the second semiconductor devices has a load terminal of one of the first semiconductor device and of one of the second semiconductor devices associated thereto and a voltage limiting element coupled between the control terminal of one of the second semiconductor devices and the load terminal associated with that one of the second semiconductor devices.

Abstract: The disclosure presented herein provides example embodiments of systems for accurate multiplexing. The systems and methods presented may be suitable for non-limiting examples of analog to digital conversion with a switched input voltage (for a switched capacitor application) or any circuit with high voltage/high accuracy voltage multiplexing. In an example embodiment, pulsed current sources may be implemented to rapidly turn on and turn off the selected and unselected multiplexer ports while maintaining relatively low power consumption. A Kelvin input port may allow a high voltage input to be accurately sensed by avoiding a voltage drop associated with a selected pass gate p-channel FET channel resistance and parasitic wire resistance. The Kelvin input port biases the gate of a pass FET structure whose body terminals are allowed to remain floating.

Abstract: An electronic circuit includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a load path and an internal voltage divider with a voltage divider tap. The second semiconductor device includes a load path and a control node. The first semiconductor device and the second semiconductor device have their load paths connected in series. The voltage divider tap of the first semiconductor device is coupled to the control node of the second semiconductor device.

Abstract: An integrated circuit includes a plurality of transistors. The transistors are electrically connected in series and with their respective gates tied together. The transistors are implemented within a transistor array. The transistors are electrically connected between a first reference terminal and a second reference terminal. A non-dominator part of the transistors adjacent to the first reference terminal are implemented at corner regions of the transistor array.

Abstract: A traveling wave amplifier including differential circuits to suppress the backward wave effect is disclosed. The differential amplifier includes two cascade units providing a switching transistor, a static cascade transistor, and a dynamic cascade transistor connected in series. The dynamic cascade transistor provides a feedback circuit to feed the collector output to the base input thereof through a resistive divider in lower frequencies and a capacitive divider in high frequencies.

Abstract: Systems and methods are provided for a power supply. A first output stage is configured to supply power from a power source at a target voltage to a device in an integrated circuit in response to a power demand of the device. Load detector circuitry is configured to detect a load resulting from operation of the device, and a supplemental output stage is configured to selectively supply supplemental power from the power source to the device, in addition to the power provided by the first output stage, in response to detection of an additional load resulting from operation of the device.

Abstract: A high-voltage switching device is formed by: connecting a number of normally-on transistors, such as JFETs, in series with each other, where the drain of each transistor is connected to the source of the next; connecting the chain of normally-on transistors in series with a normally-off switch component, such as a MOSFET, where the drain of the normally-off switch component is connected to the source of the first transistor in the chain in the chain; and, for each transistor, connecting a voltage-clamping device, such as a diode, with the anode of the voltage-clamping device connected to the source of the transistor and the cathode of the voltage-clamping device connected to the gate of the next transistor in the chain.

Abstract: The present invention provides an ESD protection circuit including a discharge transistor, a first switch, a second switch, a third switch and a fourth switch. The discharge transistor forms a discharge path between a first voltage terminal and a second voltage terminal. The first switch selectively provides voltage at the first voltage terminal to a control terminal of the discharge transistor. The second switch selectively provides voltage at the second voltage terminal to the control terminal of the discharge transistor. The third switch selectively provides voltage at the first voltage terminal to a substrate of the discharge transistor. The fourth switch selectively provides voltage at second voltage terminal to the substrate of the discharge transistor.

Abstract: The present disclosure includes circuits and methods for wideband biasing. In one embodiment, an amplifiers includes a cascode transistor between an input and an output of the amplifier. The cascode transistor receives a bias from a bias circuit comprising a resistor between the power supply and a first node, a resistor between the first node and a reference voltage, and a capacitor between the power supply and the first node. The power supply may be a modulated power supply, which is coupled through the bias circuit to a capacitance at the control terminal of the cascode transistor. An inductor is configured between a terminal of the cascode transistor and the power supply. The inductor may isolate the output from the modulated supply signal.

Abstract: A high-voltage switching device is formed by: connecting a number of normally-on transistors, such as JFETs, in series with each other, where the drain of each transistor is connected to the source of the next; connecting the chain of normally-on transistors in series with a normally-off switch component, such as a MOSFET, where the drain of the normally-off switch component is connected to the source of the first transistor in the chain in the chain; and, for each transistor, connecting a voltage-clamping device, such as a diode, with the anode of the voltage-clamping device connected to the source of the transistor and the cathode of the voltage-clamping device connected to the gate of the next transistor in the chain.

Abstract: A high voltage switch of a nonvolatile memory device includes a depletion type NMOS transistor configured to switch a second driving voltage in response to an output signal of the high voltage switch; at least one inverter configured to convert a voltage of an input signal of the high voltage switch into a first driving voltage or a ground voltage, wherein the first and second driving voltages are received from an external device; and a PMOS transistor configured to transfer the second driving voltage provided to a first terminal of the PMOS transistor from the depletion type NMOS transistor to a second terminal of the PMOS transistor as the output signal in response to an output of the at least one inverter, wherein the output of the at least one inverter is transferred to a gate terminal of the PMOS transistor.

Abstract: A circuit includes a pulsed-latch circuit. The pulsed-latch circuit includes a first plurality of transistors. One or more of the first plurality of transistors is length-of-diffusion (LOD) protected.

Abstract: Disclosed herein are cascode switching circuits that include a normally-on semiconductor device, a normally-off semiconductor device, and a gate driver. The normally-on semiconductor device and said normally-off semiconductor device each has a gate terminal, a drain terminal and a source terminal. The gate driver has a first output and a second output, the first output of said gate driver is coupled to said gate terminal of said normally-on semiconductor device, the second output of said gate driver is coupled to said gate terminal of said normally-off semiconductor device, and the drain terminal of said normally-off semiconductor device is coupled to said source terminal of said normally-on semiconductor device so that a current path is formed through said normally-on semiconductor device and said normally-off semiconductor device. Methods of making and using such circuits, and other various aspects of such circuits are also disclosed.

Abstract: An integrated circuit chip includes a first input port, a first output port, and first and second transistors electrically coupled in series across the first input port. The second transistor is also electrically coupled across the first output port and is adapted to provide a path for current flowing through the first output port when the first transistor is in its non-conductive state. The integrated circuit chip additionally includes first driver circuitry for driving gates of the first and second transistors to cause the transistors to switch between their conductive and non-conductive states. The integrated circuit chip further includes first controller circuitry for controlling the first driver circuitry such that the first and second transistors switch between their conductive and non-conductive states to at least substantially maximize an amount of electric power extracted from an electric power source electrically coupled to the first input port.

Abstract: Radio-frequency (RF) switch circuits are disclosed providing uniform voltage swing across a transmit switch for improved device performance. A switching circuit includes a switch having field effect transistors (FETs) defining an RF signal path between the input port and the output port, the switch configured to be capable of being in a first state corresponding to the input and output ports being electrically connected so as to allow passage of the RF signal therebetween, and a second state corresponding to the input and output ports being electrically isolated. The switching circuit includes a voltage distribution circuit configured to reduce voltage distribution variation across the switch, including one or more elements coupled to a selected body node of one or more FETs so as to reduce voltage distribution variation across the switch when the switch is in the first state and encountered by an RF signal at the input port.

Abstract: According to an embodiment, a solid-state switching device includes a high-voltage switching transistor including a source, a drain and a gate, and being adapted for switching a high voltage on the basis of a switching signal, and a switching driver circuit operationally connected to the high-voltage switching transistor, the switching driver circuit including a low-voltage driver transistor including a source, a drain and a gate, connected in series to the high-voltage switching transistor and being adapted for transferring the switching signal to the high-voltage switching transistor, wherein the high-voltage switching transistor is arranged source-down on top of the drain of the low-voltage driver transistor.

Abstract: In a voltage detecting circuit, a transistor is configured as a P-type MOSFET, and includes a source connected with an input terminal, a gate connected with a ground voltage terminal and a drain connected with an output terminal. A transistor is configured as a P-type MOSFET, and includes a gate and a source connected with the output terminal and a drain connected with the ground terminal. Gate width and gate length of the transistor and gate width and gate length of the transistor are adjusted so that source-drain current flowing between the source and the drain of the transistor becomes equal to source-drain current flowing between the source and the drain of the transistor when the voltage applied to the input terminal is set to be preset trigger voltage. This configuration accomplishes detecting that the input voltage exceeds the trigger voltage with simple configuration.

Abstract: Disclosed herein is a switch for turning on/off the connection between a first terminal and a second terminal. The switch includes a first transistor circuit configured from two transistors connected in series between the first terminal and the second terminal; and a second transistor circuit having a gate terminal connected to source terminals of the two transistors and a source terminal connected to gate terminals of the two transistors. The connection between the first terminal and the second terminal is changed over between on and off states by changing over a potential to the source terminal of the second transistor circuit between high and low levels.

Abstract: Radio-frequency (RF) switch circuits are disclosed providing improved switching performance. An RF switch system includes at least one field-effect transistor (FET) disposed between a first node and a second node, each having a respective source, drain, gate, and body. The system includes a coupling circuit including a first path and a second path, the first path being between the respective source or the respective drain and the respective gate of the at least one FET, the second path being between the respective source or the respective drain and the respective body of the at least one FET. The coupling circuit may be configured to allow discharge of interface charge from either or both of the coupled gate and body.

Abstract: There is provided a radio frequency switch circuit including a first switch circuit unit connected between a first node connected to a first signal port and a common node connected to a common port, and operated according to a first control signal, a second switch circuit unit connected between a second node connected to a second signal port and the common node and operated according to a second control signal having a phase opposite to that of the first control signal, a first shunt circuit unit connected between the second node and a common source node and operated according to the first control signal, a second shunt circuit unit connected between the first node and the common source node, and a source voltage generating unit generating a source voltage, wherein the source voltage is lower than a high level of the first control signal and higher than a ground potential.

Abstract: A radio frequency (RF) switch which comprises an RF domain section having a plurality of RF switching elements. A DC domain section is provided having circuitry configured for controlling the RF switching elements in response to one or more control signals. A resistive load is provided between the RF domain section and the DC domain section. A bypass circuit is configured for selectively bypassing at least a portion of the resistive load.

Abstract: A semiconductor device includes an internal high voltage terminal supplied with an internal high voltage, an internal negative voltage terminal supplied with an internal negative voltage, a monitoring pad suitable for monitoring the internal high and negative voltages, a first switch suitable for controlling electrical connection between the high voltage terminal and the monitoring pad and including two or more transistors coupled in series, and a second switch suitable for controlling electrical connection between the negative voltage terminal and the monitoring pad and including two or more transistors coupled in series.

Abstract: The present invention discloses a semiconductor switch comprising a switching unit. Said switching unit includes: a transistor having a drain, a gate and a source; a drain bias resistor coupled to the drain; a drain bias selecting circuit to couple the drain bias resistor with a first or a second drain bias according to the transistor's state; a gate bias resistor coupled to the gate; a gate bias selecting circuit to couple the gate bias resistor with a first or a second gate bias according to the transistor's state; a source bias resistor coupled to the source; and a source bias selecting circuit to couple the source bias resistor with a first or a second source bias according to the transistor's state, wherein the first and second drain biases are different, the first and second gate biases are different, and the first and second source biases are different.

Abstract: A circuit for a phase connection of an inverter includes upper and lower bridge halves and respectively associated upper and lower bridge segments. Each bridge half has an outer switch and an inner switch connected in series. Each bridge segment has a diode and the inner switch of the associated bridge half connected in series. An output of the circuit is respectively connected to upper and lower potentials through the outer switches and is further connected to a center potential applied between the upper and lower potentials through each of the upper and lower bridge segments. Each bridge half further has a parallel power switch. The parallel switch of each bridge half is connected in parallel to the series-connected outer and inner switches of the bridge half. The output of the circuit is further respectively connected to the upper and lower potentials through the parallel switches.

Abstract: According to an embodiment, a solid-state switching device includes a high-voltage switching transistor including a source, a drain and a gate, and being adapted for switching a high voltage on the basis of a switching signal, and a switching driver circuit operationally connected to the high-voltage switching transistor, the switching driver circuit including a low-voltage driver transistor including a source, a drain and a gate, connected in series to the high-voltage switching transistor and being adapted for transferring the switching signal to the high-voltage switching transistor, wherein the high-voltage switching transistor is arranged source-down on top of the drain of the low-voltage driver transistor.

Abstract: An electronic circuit includes a reverse-conducting IGBT and a driver circuit. A first diode emitter efficiency of the reverse-conducting IGBT at a first off-state gate voltage differs from a second diode emitter efficiency at a second off-state gate voltage. A driver terminal of the driver circuit is electrically coupled to a gate terminal of the reverse-conducting IGBT. In a first state the driver circuit supplies an on-state gate voltage at the driver terminal. In a second state the driver circuit supplies the first off-state gate voltage, and in a third state the driver circuit supplies the second off-state gate voltage at the driver terminal. The reverse-conducting IGBT may be operated in different modes such that, for example, overall losses may be reduced.

Abstract: This document discusses, among other things, a switching device and method configured to receive a signal at a signal input, to provide the signal at an output in a first state without an applied voltage at a first control input, and to isolate the signal from the output in a second state with an applied voltage at the first control input. In an example, the switching device can include first, second, and third transistors, wherein the source of the first transistor is coupled to the drain of the second transistor and to the gate of the third transistor, wherein the signal input is coupled to the drain of the first transistor and to the drain of the third transistor, and wherein the output is coupled to the source of the third transistor.