Abstract: A capacitive load driving device applies a multi-level voltage to a capacitive load to drive the capacitive load. In the capacitive load driving device, a voltage control signal generator unit generates a voltage control signal. A voltage amplifier unit amplifies a voltage of the voltage control signal. A current amplifier unit amplifies a current of an output of the voltage amplifier unit to perform charging of the capacitive load. A falling control signal generator unit generates a falling pulse having a predetermined pulse width when a width of falling of the voltage control signal exceeds a predetermined value. A switching unit performs discharging of the capacitive load in response to the falling pulse received.

Abstract: A high-frequency switching circuit module includes a high-frequency switch that includes an FET switching element and that selectively connects between a common input/output terminal and one of input/output terminals, and a matching circuit that is provided to the common input/output terminal Pc and is not provided to the input/output terminals. Although a non-selected input/output terminal of the high-frequency switch acts as a capacitor and the impedance between the common input/output terminal and a selected input/output terminal is displaced from a normal impedance, the displacement is corrected by the matching circuit connected to the common input/output terminal such that the impedance viewed from the common input/output terminal Pc to the high-frequency switch is made equal to the normal impedance. Accordingly, a high-frequency switching circuit module having a small overall size and achieving impedance matching for each terminal is provided.

Abstract: A one mode of a gate driving circuit that drives a gate electrode of an electric power switching element (9), comprising drive means (6) configured to supply to the gate electrode a current in accordance with a voltage applied across the principal electrodes of the electric power switching element (9), while utilizing a voltage produced by dividing a voltage applied across the principal electrodes by use of resistors (4a, 4b). Since the drive means (6) utilizes a voltage produced by a voltage dividing resistor circuit, which divides the voltage applied across the principal electrodes of the electric power switching element (9) as a power source voltage, only an addition of the dividing resistors (4a, 4b) makes it possible to constitute the power source for the current drive means (6).

Abstract: A gate driving circuit includes cascaded stages, each including a pull-up part, a carry part, a pull-up driving part, a holding part and an inverter. The pull-up part pulls up a gate voltage to an input clock. The carry part pulls up a carry voltage to the input clock. The pull-up driving part is connected to a control terminal (Q-node) common to the carry part and the pull-up part, and receives a previous carry voltage from a previous stage to turn on the pull-up part and the carry part. The holding part holds the gate voltage at an off-voltage, and the inverter controls at least one of turning on the holding part and turning off the holding part based on an inverter clock. A high level of the inverter clock in a given horizontal period (1H) temporally precedes a high level of the input clock by a predetermined time interval.

Abstract: An electronic circuit has an output driver (DRV) for providing a driving signal (U0). The output driver has a transistor (T) with a first main terminal, a second main terminal and a control terminal coupled to receive a control signal (Vcntrl), a power supply terminal (VSS), an output terminal (OUT) for providing the driving signal (U0) that is coupled to the second main terminal, and a sensing resistor (Rm) coupled between the power supply terminal (VSS) and the first main terminal. The output driver (DRV) further has means for temporarily disabling the coupling between the control terminal and the control signal (Vcntrl) during a peak voltage across the sensing resistor (Rm). The means may have a circuit that has a unidirectional current behavior, such as a diode (D), in series with the control terminal of the transistor (T).

Abstract: The present invention relates to controlling switches in a series connection of electrical devices, in particular to a circuit arrangement, and method of operating same, in which a transistor switch (44, 54) is used to control operation of the devices (12, 14). Because the transistor switches need a gate-source voltage difference, but on the other hand are connected with their source (s) and drain (d) to the main circuit branch, this voltage difference is built up by providing a control current (Ii, I2) over e.g. a resistor (42, 52). This control current (Ii, I2) enters the main current (I), which would influence the operation of the devices, e.g. LEDs (12, 14). In order to correct this, the control current (I2) is corrected for the values of one or more upstream control currents (I2), e.g. through adapting the pulse width in pulse width modulation.

Abstract: A microchip includes at least one I/O area surrounding at least one core circuit area. The I/O area further includes a first I/O cell having at least one first post-driver device connected to a first I/O pad; a second I/O cell having at least one second post-driver device connected to a second I/O pad; and an electrostatic discharge (ESD) cluster shared by the first I/O cell and the second I/O cell for protecting the same against ESD current during an ESD event, thereby reducing a total width of the first I/O cell and the second I/O cell.

Abstract: A dual gate drain extension field effect transistor assembly comprises a first FET device having a source, a gate and a drain extension region. The first FET device's gate is electrically coupled to a constant voltage source. A second FET device has a source, a drain, and a gate, and the second FET's drain is electrically to the first FET's source.

Abstract: An integrated high side switch with multi-fault protection. When a fault condition is detected, the switch is turned off. The switch includes a pair of transistors that are connected such that the source of the first transistor is connected with the source of the second transistor. The drain of the first transistor is thus connected to the supply voltage. A first current mirror generates a current sense output. A second current mirror generates an internal current to detect an over current fault condition. The transistors in the current mirrors are connected like the switch transistors. A high voltage operational amplifier and a transistor are used as feedback to insure that the voltage at the output of the current mirrors matches the voltage at the output of the switch. This ensures that the current mirrors generate scaled versions of the current flowing through the switch.

Abstract: A semiconductor switch includes first and second normally off type FETs Q1, Q2 and a normally on type FET Q3 connected between the first normally off type FET Q1 and the second normally off type FET Q2. Further, in the semiconductor switch, the normally on type FET Q3 is connected between the first and second normally off type FETs Q1, Q2 in series.

Abstract: An integrated circuit includes at least two circuit components formed on a common semiconductor substrate. Each circuit component has a self-contained supply voltage system. Coupling circuits couple the supply voltage systems for the at least two circuit components. Each coupling circuit includes at least one transistor having a base formed by or within the substrate itself; more specifically, by or within a region of the substrate contiguous with collector doping zones and emitter doping zones of the transistor. The resistance between the transistor base and the potentials of the two supply voltage systems coupled by each of the coupling circuits is the intrinsic resistance of the substrate between the region forming the base and one of each contact doping zone conductively connected to the collector or emitter through a metallization applied to the substrate.

Abstract: A control output signal is supplied to a gate electrode of an insulated gate transistor from a control signal output terminal of a control device, however, with regard to the insulated gate transistor, a control output signal is also influenced when that transistor is short-circuited, and a signal waveform different from that in a normal operating state occurs. The short-circuit is detected by monitoring the control output signal of the insulated gate transistor, and in case of the short-circuit, the short-circuit protection of the insulated gate transistor is performed by forcing the control device to stop that control output signal.

Abstract: A low control voltage switch utilizing a plurality of field effect transistors (FETs) having a total of six gates to allow the switch to operate at a low control voltage without the need to increase device periphery or die size. Feed-forward capacitors connected between the gate and source of an uppermost FET and the gate and drain of a lowermost FET are used to reduce signal distortion and improve the linearity and harmonic noise rejection characteristics of the FETs within the switch and thus lower the harmonics of the switch.

Abstract: In a conventional semiconductor integrated circuit device, a means for preventing a backflow current has a high on-state resistance, which makes it impossible to reduce the voltage loss in normal operation. A semiconductor integrated circuit device of the invention has a first MOS transistor, a second MOS transistor provided between the first MOS transistor and a power supply terminal, and a means that, in normal operation, keeps the gate of the second MOS transistor at a predetermined potential (preferably the ground potential) and that, when a backflow current is likely, turns the second MOS transistor off. This helps prevent a backflow current while reducing the voltage loss in normal operation.

Abstract: Low-power and low-noise CDS (correlated double sampling) comparators for use with a CIS (CMOS image sensor) device are provided. A CDS comparator is constructed using one of various low-power inverters that provide decreased instantaneous transition currents at a logic threshold voltage. The use of such low-power inverters in CDS comparators enables a significant reduction in power consumption and noise in the CIS device, or other devices that implement such CDS comparators and/or inverters.

Abstract: A switching circuit is disclosed for switching high voltages and high currents, if necessary, without causing snapback or breakdown. The disclosed high voltage, high current switching circuit comprises a first set of series-connected transistors that includes a plurality of transistors to switch a high voltage without inducing snapback or breakdown; and a second set of series-connected transistors that includes one or more transistors to switch a high current. The first and second sets of series-connected transistors are connected in parallel. The gates of the second set of series-connected transistors are enabled to cause conduction through the second set of series-connected transistors. In addition, a voltage detector is connected to an output of the first and second sets of series-connected transistors. The output of the voltage detector is coupled to the enabling means.

Abstract: In a conventional semiconductor integrated circuit device, a means for preventing a backflow current has a high on-state resistance, which makes it impossible to reduce the voltage loss in normal operation. A semiconductor integrated circuit device of the invention has a first MOS transistor, a second MOS transistor provided between the first MOS transistor and a power supply terminal, and a means that, in normal operation, keeps the gate of the second MOS transistor at a predetermined potential (preferably the ground potential) and that, when a backflow current is likely, turns the second MOS transistor off. This helps prevent a backflow current while reducing the voltage loss in normal operation.

Abstract: A gradation selector circuit provided with a resistor string circuit in which resistive elements are connected in series between a high potential power source and a low potential power source and a selector circuit which is connected to the resistor string circuit, which selects one of plural analog voltages generated in the resistor string circuit according to a control signal and which outputs it to an output terminal is used. The selector circuit includes analog switching circuits that select analog voltage close to intermediate potential. The analog switching circuit includes a P-type MOS transistor to the source electrode and the back gate electrode of which the resistor string circuit is connected and a depletion type N-type MOS transistor to the source electrode of which the drain electrode of the P-type MOS transistor is connected and to the drain electrode of which an output terminal is connected.

Abstract: According to one embodiment, a locally regulated circuit regulates current flows (IREG and IRG) through the operation of a current mirror (334, 332, 326). The regulated current flows are used to self-generate a common mode voltage (V422) at node (322) and to produce the required bias signals through input stage (302 and 308) and output stage (314 and 316) in response to data input signals (D and D-complement). Cancellation of common mode voltage variation is further enhanced by generating a supplemental current in response to an error signal generated by comparing a desired common mode voltage (VCM) to the actual common mode voltage at node (322). The supplemental current conducted by either of loads (310 and 312) serves to regulate the common mode voltage at node (322).

Abstract: A first conductive transistor having a high threshold value and a second conductive transistor having a low threshold value are connected in series between a first actual power supply line supplying a power supply voltage and a virtual power supply line connected to a power supply pin of a circuit block constituted of transistors having a low threshold value. The first and second conductive transistors have polarities which are opposite to each other. A power control circuit turns on the first and second conductive transistors while the circuit block is in operation and turning off the first and second conductive transistors while the circuit block is not in operation. Therefore, subthreshold currents of the first and second conductive transistors can be suppressed. As a result of this, it is possible to reduce power consumption of the semiconductor integrated circuit during its standby period.

Abstract: The driver circuit for driving a switching transistor comprises a driver transformer for driving the switching transistor and an output stage for driving the driver transformer, and an output of the driver circuit is used for providing also said switching voltage. The switching voltage is derived advantageously from the primary winding of the driver transformer. Preferably a terminal of the primary winding of the driver transformer is directly wired to the gate electrode of the MOS transistor.

Abstract: A cascode circuit with improved withstand voltage is provided. The cascode circuit includes three or more transistors, such as MOSFET transistors. Each transistor has a control terminal, such as a gate, and two conduction terminals, such as a drain and a source. The conduction terminals are coupled in series between two output terminals, such as where the drain of each transistor is coupled to the source of another transistor. A signal input is provided to the gate for the first transistor. Two or more control voltage sources, such as DC bias voltages, are provided to the gate of the remaining transistors. The DC bias voltages are selected so as to maintain the voltage across each transistor to a level below a breakdown voltage level.

Abstract: A bi-directional solid state switch has two main transistors which are connected to each other with input to input and input referenced output to input referenced output. Each unreferenced transistor output is separately connected to an output terminal of the switch. An electrical impedance is connected between the input connection and the input referenced output connection. A driver signal is connected across the input connection and one output terminal. This circuit topology is counter-intuitive, but provides advantages which can include eliminating the need for electrical isolation, being capable of turning on or off at any time, at or between zero crossings, having a high speed of response, simplicity, reliability, cost-effectiveness, and energy-efficiency.

Abstract: An analog circuit apparatus connected to a high voltage source includes a transistor and an interface unit. The transistor has a low operation voltage smaller than the high voltage source and a breakdown voltage. The interface unit is coupled to the transistor in series for preventing the low operation voltage higher than the breakdown voltage.

Abstract: A constant current source with threshold voltage and channel length modulation includes first, second, third, fourth and fifth MOS transistors. Each of the MOS transistors has gate, first and second terminals. The first terminal of the second MOS transistor is coupled to loading impedance, and its second terminal is coupled with the first terminal of the first MOS transistor. The gate terminal and first terminal of the third MOS transistor are together coupled to the gate terminal of the second MOS transistor, and its second terminal is coupled to the first terminal of the fourth MOS transistor. The gate terminal and first terminal of the fourth MOS transistor are coupled to the gate terminal of the first MOS transistor, and its second terminal is coupled to a first reference voltage.

Abstract: A circuit for sensing a voltage across a power switch includes a transmission gate, a low pass filter and a comparator. The power switch is controlled by a control signal for turning the power switch on and off to generate a switching voltage at a first current handling terminal of the power switch. The transmission gate is turned on whenever the power switch is turned on to sample the voltage across the power switch when the power switch is turned on. The sampled voltage is filtered by the low pass filter to remove high frequency transients. Finally, the comparator compares the filtered voltage to a reference voltage. The comparator provides an output signal having a first value when the filtered voltage is less than the reference voltage. The circuit can be used as a load sensing circuit to sense the load condition under which the power switch is being operated.

Abstract: This invention relates to a high frequency switch circuit including a plurality of high frequency terminals (101, 102, 103) which input/output a high frequency signal, and a plurality of high frequency semiconductor switch sections (121, 122) which switch between these high frequency terminals. The plurality of high frequency semiconductor switch sections are isolated from each other in a DC state by a DC potential isolating section (131), and a DC potential opposite in level to a DC potential applied to a switching signal terminal (111, 112) arranged on the control side of each high frequency semiconductor switch section is applied to both or at least one of the input side and output side of each high frequency semiconductor switch section.

Abstract: A high frequency switch configured particularly with two FET switches. One end of a second FET switch is connected between an I/O port and a reception port and the other end is ground. A strip line is connected between the second FET switch and the I/O port, and has the electrical length equivalent to {fraction (1/4 )} wavelength of the high frequency signal input from a transmission port.

Abstract: A gate driver is provided for controlling a gate voltage of each of a plurality of MOS control semiconductor devices, such as IGBTs or metal oxide MOS transistors, of a semiconductor power converter in which said MOS control semiconductors are connected in series with each other, the gate driver includes a power supply line having a higher potential than a gate potential on each of said MOS control semiconductor devices when in steady ON state, and an arrangement for supplying a current from the power source line to the gate of each of said MOS control semiconductors to increase the gate voltage of the MOS control semiconductor devices when a potential difference between said power supply line and an emitter of each of said MOS control semiconductors is constant and when a collector voltage of the MOS control semiconductor device exceeds a predetermined value under ON state of the MOS control semiconductor device.

Abstract: A MOS-gated circuit, including a plurality of gated switches; and a driver circuit electrically coupled to the gated switches, the driver circuit configured to automatically prevent a simultaneous conduction of the gated switches if at least one of the gated switches is not capable of sustaining a reapplied voltage without conducting.

Abstract: The present invention is a circuit comprising two series-coupled field effect transistor (FET) devices with a resistor network coupled in parallel forming a composite device (that can be substituted directly for a single FET device). In applications such as active loads or current sources, the composite device exhibits a greater breakdown voltage and superior high-frequency characteristics. The resistor network provides optimum direct current (DC) bias for depletion mode devices and superior high-frequency loading. Bandwidth and stability are both increased. Furthermore, this circuit is compatible with depletion mode FET processes having a single fixed threshold voltage.

Abstract: A power integrated circuit includes a gate driver coupled to an output transistor having a plurality of segments. The gate driver also has a plurality of segments, each of the segments of the driver circuit being located adjacent a corresponding one of the segments of the output transistor. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).

Abstract: A configurable analog output circuit comprises a current output circuit, a voltage output circuit, and a switch circuit. The current output circuit is capable of producing a current output signal usable to control a current through an output device. The voltage output circuit is capable of producing a voltage output signal usable to control a voltage across the output device. The switch circuit is capable of switching the analog output circuit between a first mode of operation in which the current output circuit is active and a second mode of operation in which the voltage output circuit is active. The switch circuit switches the analog output circuit between the first and second modes of operation responsive to a detected characteristic of the output device.

Abstract: A high side circuit includes at least one power device having a first non-drivable terminal connected to a supply voltage, at least one load connected between a second non-drivable terminal of the power device and ground, and driving circuitry. The driving circuitry includes transistors which are connected to each other and to a higher voltage than the supply voltage in order to control the turning on and the turning off of the power device and to reduce or minimize the potential difference between the second non-drivable terminal and a drivable terminal of the power device during the turning off state to avoid the re-turning on of the same power device.

Abstract: Briefly, in accordance with one embodiment of the invention, a digital-to-analog cell includes an analog circuit that provides, at least in part, an output signal. Transistors may be coupled to the analog circuit to provide source-side switching of the analog circuit.

Abstract: In a switching arrangement, a plurality of modules are connected such that the main switching elements, FETs, are in series. Control of and power to the FETs is supplied via a single turn primary passing through a plurality of toroidal secondary transformers. A train of control pulses is applied to the single turn primary and their polarity determines whether the main FET is switched on or off, the length of the pulse train determining the pulse width and PRF of the output of the switching arrangement. The control pulses are also used to supply power to the main driver of the main FET.

Abstract: A push-pull switch including a first N-channel MOS transistor, the drain-source path of which is connected between a high voltage terminal and an output terminal, a first resistor connected between the gate of the first transistor and the high voltage, a diode having its anode connected to the output terminal and its cathode connected to the gate of the first transistor, a second N-channel MOS transistor having its drain connected to the cathode of the diode, its source connected to a reference potential, and its gate connected to a control terminal, and a second resistor connected between the gate of the second transistor and the output terminal.

Abstract: The invention relates to a method of coupling active semiconductor components, and to such a coupling, and particularly to a series-coupling of such components to enable high voltages to be controlled. According to the invention, a voltage (Vs2, Vs3, Vs3 . . . Vsn) is taken from a semiconductor component (T1, T2, T3, T4 . . . Tn-1) and applied to a controlling input of the next following semiconductor component (T2, T3, T4 . . . Tn-1) said voltage being locked at a predetermined highest value.

Abstract: According to this invention, there is provided a drive apparatus for a power device having high- and low-voltage main electrodes and a control electrode, including a circuit for decreasing a voltage of the control electrode to a voltage of the control electrode which is not higher than a threshold voltage of the power device before a voltage between the high- and low-voltage main electrodes enters an overshoot region in a case where the power device is to be turned off. Therefore, electron injection can be stopped before the voltage between the main electrodes rises, the stability of the current density can be improved, and current concentration, oscillation, and the like can be prevented to improve reliability.

Abstract: A control system for a bidirectional switch (20) is described, formed of a pair of MOFSET power transistors (210, 220) connected in anti-series, i.e. source to source or drain to drain. This control system includes means (50) allowing the state of conduction of the power transistors to be controlled, one or the other of these transistors being able to be set to the “OFF” state in order to assure the interruption of a current through the bidirectional switch (20). This control system includes coupling means (SWCPL, 510) enabling the gate of the power transistor at the “ON” state to be coupled at least temporarily with the gate of the power transistor at the “OFF” state when the bidirectional switch is switched on. This has the advantage of allowing, on the one hand, the use of high control voltages assuring a reduction in the series resistance of the power transistors, and, on the other hand, the bidirectional switch to be quickly switched on.

Abstract: An apparatus including a low voltage differential signaling (LVDS) driver circuit with on-resistance cancellation, includes a current steering circuit having an on-resistance. In order to cancel the on-resistance of the current steering circuit, the LVDS driver circuit also includes a current proportional to absolute temperature current source, a transistor having an on-resistance proportional to the on-resistance of the current steering circuit, and a voltage-to-current conversion circuit coupled to the transistor, wherein the voltage-to-current conversion circuit converts the drain-to-source voltage of the transistor into a current proportional to an output current of the LVDS driver circuit. A first resistive circuit receives the current proportional to absolute temperature and the current proportional to an output current of the LVDS driver circuit and in accordance therewith provides a first reference signal.

Abstract: When a power supply terminal (10) is grounded, a circuit (101) is in the OFF state, and a high potential is transferred from a circuit (3) to a bus line (BL), the high potential is transferred to a node (100) via the source of a transistor (P1), back gate (Nw), and transistor (P2). A NAND circuit (NA1) always outputs a control signal (VGP) of a level equal to the node (100) to the gate of the transistor (P1) to turn non-conductive the transistor (P1). Hence, a current path from a terminal (B) to a terminal (A) or from the terminal (B) to the back gate (Nw) is cut off to prevent wasteful current consumption.

Abstract: A voltage switch is provided made up of 2.5 volt process transistors which tolerate a maximum gate to source, gate to drain, or drain to source voltage of 2.7 volts. The voltage switch transistors are arranged to switch between a voltage, such as 2.5 volts, and a much higher voltage, such as 4.5 volts. In one embodiment (350), the voltage switch includes an input provided to the source of an NMOS cascode connected transistor (360). An inverter (354) connects the source of the NMOS cascode (360) to the source of another NMOS cascode (361). A cascode transistor is defined as being connected so that it is turned on and off by varying source voltage with the gate voltage fixed, rather than varying gate voltage. Gates of the cascodes (360, 361) are connected to Vcc (2.5 volts). PMOS cascode transistors (362) and (363) connect the drains of respective cascode transistors (360) and (361) to PMOS transistors (364) and (365). The PMOS transistors (364) and (365) have sources connected to 4.5 volts.

Abstract: In order to prevent an output offset voltage from occurring because of a relative difference of threshold voltage Vth between NMOS and PMOS in transmission of dc voltage, a semiconductor integrated circuit is constructed in a circuit configuration comprising a first depletion-mode N-channel MOS transistor and a first depletion-mode P-channel MOS transistor, a gate of each transistor being connected to an input terminal and a source of each transistor being connected to an output terminal, a second depletion-mode N-channel MOS transistor having W/L equal to that of the first depletion-mode P-channel MOS transistor, a drain of the transistor being connected to the output terminal and a gate and a source of the transistor being connected both to a lower-voltage-side power supply, and a second depletion-mode P-channel MOS transistor having W/L equal to that of the first depletion-mode P-channel MOS transistor, a drain of the transistor being connected to the output terminal and a gate and a source of the transist

Abstract: Disclosed is a switching circuit which has: at least one unit circuit connected in series, the unit circuit being composed of two field-effect transistors connected in series and an inductor that has one end connected to a connection point between the two field-effect transistors and another end grounded; wherein the gates of the two field-effect transistors are commonly connected and a bias voltage to control the turning on/off of the two field-effect transistors is equally applied through a resistance to the respective gates.

Abstract: An output driver circuit offers control and logic level adjustment for high speed data communications in a synchronous memory such as a synchronous dynamic random access memory (SDRAM). Level adjustment is obtained by resistive division between a termination resistor and controllable impedances between an output node and VDD and VSS power supplies. Control functions include slew rate modification of the signal at the output node, by sequentially turning on or off output transistors in response to a transition in an input signal. Different schemes of weighting the output transistors obtains different characteristics of the output signal. Load matching circuitry and voltage level forcing circuitry is described for improving high frequency operation.

Abstract: A signal processing circuit for a solid state image sensor, includes a charge detection circuit for outputting a signal output from the image sensor, a first inverting amplifier receiving the signal output, and a second inverting amplifier having a source-grounded MOS transistor having a gate connected to receive an output of the first inverting amplifier. A threshold of the MOS transistor is set to be the same as a black reference voltage in the input signal applied to the MOS transistor. Thus, a reset noise included in the signal output from the image sensor is suppressed or removed.

Abstract: A high-output voltage generating circuit that prevents transistor breakdown includes first and second switching circuits coupled to each other at a first common gate, the first common gate being connected to a first control signal, and the first and second switching circuits being connected to a common input signal; third and fourth switching circuits coupled to each other at a second common gate, the second common gate being connected to a second control signal; a signal output unit having first and second transistors coupled to each other at a third common gate, the third common gate being connected to the second control signal; a third transistor, coupled to a first voltage, receiving a first signal at a gate from the first switching circuit; a fourth transistor, coupled to the third transistor, receiving a second signal from the third switching circuit at a gate, the fourth transistor being coupled to the first transistor of the signal output unit; a fifth transistor, coupled to the second transistor of t

Abstract: A half-bridge circuit where the transistors comprising the half-bridge are electronically interlocked--precluding cross-conduction; and high-side voltage generation and logic level translation are integral to the interlock mechanism.

Abstract: A power semiconductor device (2) has a first main electrode (S) for coupling to a first supply line (3), a second main electrode (D) coupled to a first terminal (4) for connection via a load (L) to a second voltage supply line (5) and an insulated gate electrode (G) coupled to a control terminal (GT) for supplying a gate control signal to enable conduction of the power semiconductor device (2). An open-circuit detection arrangement is integrated with the power semiconductor device (2) for providing an indication that a load (L) coupled to the power semiconductor device (2) is open-circuited. The detection arrangement has a reference current (Ir) providing arrangement (7, R3, R4, R7, Q1, Q2) and a current deriving arrangement (Q3, Q4) for deriving a current (Id) dependent on the voltage at the second main electrode (D).