Abstract: The semiconductor device includes a power element which is in an on state when voltage is not applied to a gate, a switching field-effect transistor for applying first voltage to the gate of the power element, and a switching field-effect transistor for applying voltage lower than the first voltage to the gate of the power element. The switching field-effect transistors have small off-state current.

Abstract: A high-speed semiconductor integrated circuit device is achieved by adjusting an offset voltage. For example, dummy NMOS transistors MND1 (MND1a and MND1b) and MND2 (MND2a and MND2b) are connected to drain outputs of NMOS transistors MN1 and MN2 operated according to differential input signals Din_p and Din_n, respectively. The MND1 is arranged adjacent to the MN1, and a source of the MND1a and a drain of the MN1 share a diffusion layer. The MND2 is arranged adjacent to the MN2, and a source of the MND2a and a drain of the MN2 share a diffusion layer. The MND1 and the MND2 function as dummy transistors for suppressing variations in process of the MN1 and the MN2 and, and besides, they also function as means for adjusting the offset voltage by appropriately applying an offset-amount setting signal OFST to each gate to provide a capacitor to either the MN1 or the MN2.

Abstract: A circuit is provided that includes a parasitic power circuit that powers a parasitic circuit. The parasitic power circuit derives a supply voltage from an external AC or other signal suitable for use as a communications signal. A PMOS transistor or transistors is utilized to enable a supply voltage capacitor to charge substantially to the same voltage as the channel voltage of the communications signal.

Abstract: An electronic circuit for switching purposes comprises a set of at least four electronic switches. A first subset and a second subset comprise at least two electronic switches of said set, respectively. Said at least two electronic switches of said first subset are arranged in a serial connection. Said at least two electronic switches of said second subset are arranged in a serial connection. The electronic circuit comprises a first buffer connected to a first electronic switch of said first subset and a second buffer connected to a second electronic switch of said second subset. Said first buffer minimises a potential drop across said first electronic switch when in open state, and said second buffer minimises a potential drop across said second electronic switch when in open state. The electronic circuit further comprises a switched connection towards ground arranged in between the two subsets.

Abstract: A power switch circuit providing voltage to an output port is provided. The switch circuit includes a single power supply, a switch unit, a controlling unit, and a logic unit. The switch unit is connected between the single power supply and an output port and capable of being turned on and off alternatively for continuing or discontinuing power from the single power supply to the output port; the single power supply provides power to the output port. The controlling unit is configured for generating a voltage controlling signal and transmitting the voltage controlling signal to the logic unit. The logic unit receives and inverts the voltage controlling signal, and outputs the inverted voltage controlling signal to turn on or turn off the switch unit.

Abstract: A buffer circuit in accordance with an embodiment comprises output transistors connected between a first fixed voltage terminal and an output terminal, and gate control transistors connected between a second fixed voltage terminal and a gate of one of the output transistors or between two of gates of the output transistors. The output transistors are configured to turn on to change a voltage of the output terminal. The gate control transistors are configured to apply a gate voltage to the gates of the output transistors. A gate of each of the gate control transistors is applied with a certain voltage, such that when a source of each of the gate control transistors changes from a first potential to a second potential, a potential difference between the gate and the source attains a threshold voltage or greater, whereby each of the gate control transistors is turned on.

Abstract: An electronic circuit for switching purposes comprises a set of at least four electronic switches. A first subset and a second subset comprise at least two electronic switches of said set, respectively. Said at least two electronic switches of said first subset are arranged in a serial connection. Said at least two electronic switches of said second subset are arranged in a serial connection. The electronic circuit comprises a first buffer connected to a first electronic switch of said first subset and a second buffer connected to a second electronic switch of said second subset. Said first buffer minimises a potential drop across said first electronic switch when in open state, and said second buffer minimises a potential drop across said second electronic switch when in open state. The electronic circuit further comprises a switched connection towards ground arranged in between the two subsets.

Abstract: A transmission gate circuit includes a first transmission gate, having a first switching device, coupled in series with a second transmission gate, having a second switching device, and control circuitry which places the first transmission gate and the second transmission gate into a conductive state to provide a conductive path through the first transmission gate and the second transmission gate. When the voltage of the first terminal is above a first voltage level and outside a safe operating voltage area of at least one of the first and second switching device, the first switching device remains within its safe operating voltage area and the second switching device remains within its safe operating voltage area.

Abstract: A power semiconductor module includes a normally on, controllable first power semiconductor switch including at least one first power semiconductor chip, and a normally off, controllable second power semiconductor switch including at least one second power semiconductor chip. The load paths of the first power semiconductor switch and of the second power semiconductor switch are connected in series. The control terminals of all first power semiconductor chips are permanently electrically conductively connected to a conductor track to which no load terminal of any of the first power semiconductor chips is permanently electrically conductively connected, and to which no load terminal and no control terminal of any of the second power semiconductor chips are permanently electrically conductively connected.

Abstract: Embodiments of circuits, devices, and methods related to a radio frequency switch are disclosed. In various embodiments, a circuit may comprise a series path including a series transistor to be switched on during a first mode of operation; a shunt path including a shunt transistor to be switched off during the first mode of operation; and a return path including a return transistor to be switched on during the first mode of operation. Other embodiments may also be described and claimed.

Abstract: Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in series, each switch circuit being driven by a level shift circuit. Each switch circuit uses a group of series coupled transistors with a parallel control transistor where the number of transistors in each group may be determined by an expected switch input voltage and a maximum allowable voltage drop for each transistor. A voltage of a particular state of an enable signal is shifted up to the switch input voltage by the level shift circuits. The particular state of the enable signal turns on the voltage switch such that the switch output voltage is substantially equal to the switch input voltage.

Abstract: An analog T switch is disclosed which has high isolation in the off state. The analog T switch can include series-connected NMOS transistors having separate gate control. The gates of the NMOS transistors can be isolated from one another to improve off state isolation of the analog T switch. The analog switch can include series-connected PMOS transistors having separate gate control. The gates of the PMOS transistors can be isolated from one another to improve off state isolation of the analog T switch. The analog T switch can include a substrate voltage control circuit that controls the voltage of the substrate regions in which the PMOS transistors are formed. The substrate voltage control circuit can isolate the substrate regions of the PMOS transistors from one another in the off state to improve off state isolation of the analog T switch.

Abstract: Provided is an SPDT switch having improved isolation characteristics in an RF band. The SPDT switch includes a serial switching unit, a current sink unit, a switching isolation unit, and a DC blocking unit. The serial switching unit includes first and second HBTs. The current sink unit sinks a current flowing from a common input terminal to each of first and second output terminals of the serial switching unit. The switching isolation unit causes an unselected output terminal of the first and second output terminals to be electrically isolated from the common input terminal when the serial switching unit operates. The DC blocking unit blocks a DC between the first HBT and the first output terminal and a DC between the second HBT and the second output terminal. Accordingly, it is possible to provide better insertion-loss and isolation characteristics in higher frequency bands than typical switches.

Abstract: A double pole double throw switch device is provided. The device includes a first path circuit, a second path circuit, a third path circuit and a fourth path circuit. The first terminals of the first and second path circuits are coupled to a first port, and the second terminals of the first and second path circuits are respectively coupled to a third port and a fourth port. The first terminals of the third and fourth path circuits are coupled to a fourth port, and the second terminals of the third and fourth path circuits are respectively coupled to the second port and the third port. Each path circuit includes a switch module and a functional switch circuit. When a switch module is turned on, its corresponding functional switch circuit is turned off, and when the switch module is turned off, its corresponding functional switch circuit is turned on.

Abstract: The present invention provides a semiconductor device of a bi-directional analog switch having a high linearity and a low electric power loss. An ultrasonic diagnostic apparatus having a high degree of detection accuracy, comprising the semiconductor device, is also provided. A semiconductor device of a bi-directional analog switch, comprising a switch circuit capable of switching ON or OFF bi-directionally, and built-in driving circuits for the switch circuit, wherein the driving circuit is connected to first and second power supplies, and a first power supply voltage is higher than a maximum voltage of a signal applied to an input/output terminal of the switch circuit, a second power supply voltage is lower than a minimum voltage of a signal applied to an input/output terminal of the switch circuit, and the driving circuit comprises a Zener diode and a p-type MOSFET connected in series between the first power supply and the switch circuit.

Abstract: The present invention is directed to reduce increase in the level of a harmonic signal of an RF (transmission) Tx output signal at the time of supplying an RF Tx signal to a bias generation circuit of an antenna switch. A semiconductor integrated circuit includes an antenna switch having a bias generation circuit, a Tx switch, and an antenna switch having a bias generation circuit, a transmitter switch, and a receiver (Rx) switch. The on/off state of a transistor of a Tx switch coupled between a Tx port and an I/O port is controlled by a Tx control bias. The on/off state of the transistors of the Rx switch coupled between the I/O port and a receiver (Rx) port is controlled by an RX control bias. A radio frequency (RF) signal input port of the bias generation circuit is coupled to the Tx port, and a negative DC output bias generated from a DC output port can be supplied to a gate control port of transistors of the Rx switch.

Abstract: A system includes a voltage pump to generate a first pump voltage from an analog voltage signal. The system further includes switching pad to receive an analog signal from an external source and route the analog signal to analog processing circuitry over one or more analog signal busses based on the first pump voltage and the analog voltage signal.

Abstract: This invention features a high voltage multiplexer element including a voltage to current converting input resistance connected to the input of the element, first and second MOSFET switches connected in series between the input resistance and the output of the multiplexer element, and a third MOS switch connected between the junction of the first and second MOSFET switches and a voltage equal to or less than the supply; the first MOSFET switch being drain engineered and having drain-source breakdown voltage higher than the supply.

Abstract: In the field of electronic technologies, a power supply selector and a power supply selection method are provided. The power supply selector includes: a first selection module, configured to select a power supply from multiple candidate power supplies; a control module, coupled to the first selection module, and configured to use the power supply selected by the first selection module as a power supply, and compare voltages of the multiple candidate power supplies to generate a control signal of each candidate power supply; and a second selection module, coupled to the control module, and configured to select a power supply for output in the multiple candidate power supplies under the control of the control signal of each candidate power supply. The technical solution is used to select a power supply from multiple candidate power supplies.

Abstract: In a first aspect, an RF switch includes a main transistor and a gate-to-source shorting circuit. When the RF switch is turned off, the gate-to-source shorting circuit is turned on to short the source and gate of the main transistor together, thereby preventing a Vgs from developing that would cause the main transistor to leak. When the RF switch is turned on, the gate-to-source shorting circuit is turned off to decouple the source from the gate. The gate is supplied with a digital logic high voltage to turn on the main transistor. In a second aspect, an RF switch includes a main transistor that has a bulk terminal. When the RF switch is turned off, the bulk is connected to ground through a high resistance. When the RF switch is turned on, the source and bulk are shorted together thereby reducing the threshold voltage of the main transistor.

Abstract: Embodiments of circuits, devices, and methods related to a radio frequency switch are disclosed. In various embodiments, a circuit may comprise a series path including a series transistor to be switched on during a first mode of operation; a shunt path including a shunt transistor to be switched off during the first mode of operation; and a return path including a return transistor to be switched on during the first mode of operation. Other embodiments may also be described and claimed.

Abstract: An output stage includes a system input and a system output, a first transistor having a first control input and a first controlled path, and a second transistor having a second control input and a second controlled path. The second controlled path is in series with the first controlled path and the system output. A first current-controlled voltage source has an input that is electrically connected to the system input. The first current-controlled voltage source has an output that is electrically connected to the first control input of the first transistor. A second current-controlled voltage source has an input that is electrically connected to the system input. The second current-controlled voltage source has an output that is electrically connected to the second control input of the second transistor.

Abstract: An analog switch includes a transistor whose source connected to a signal input and whose drain is connected to a signal output. An output of a gate control circuit is connected to the transistor gate. A first input of the gate control circuit is connected to the source of the transistor. The gate control circuit responds to a logic transition of an enable signal received at a second input by pre-charging a substantially constant gate-to-source voltage across the transistor. This voltage is stored by a gate-to-source connected capacitor. In one steady-state logic condition of the enable signal, the gate control circuit operates to turn off the transistor. In another steady-state logic condition of the enable signal, the gate control circuit permits the signal received at the signal input to drive the gate of the transistor with a voltage offset by the substantially constant gate-to-source voltage stored on the capacitor.

Abstract: A high frequency switching circuit, including a high frequency switching element. The high frequency switching element including a first channel terminal and a second channel terminal, wherein the high frequency switching element is configured to switchably route a high frequency signal via a channel path between the first channel terminal and the second channel terminal. The high frequency switching circuit further includes a power detection circuit, wherein the power detection circuit is configured to obtain a first measurement signal from the first channel terminal and a second measurement signal from the second channel terminal, and to combine the first measurement signal and the second measurement signal to derive, in dependence on both the first measurement signal and the second measurement signal, a power signal describing a power value of the high frequency signal routed via the channel path of the high frequency switching element.

Abstract: A semiconductor device with less power consumption and an electronic appliance using the same. The semiconductor device of the invention is supplied with a first potential from a high potential power source and a second potential from a low potential power source. Upon input of a first signal to an input node, an output node outputs a second signal. With the semiconductor device of the invention, a potential difference of the second signal can be controlled to be smaller than a potential difference between the first potential and the second potential, thereby power consumption required for charging/discharging wires can be reduced.

Abstract: A high voltage switch circuit of a semiconductor device includes a buffer circuit configured to output a control signal in response to an input signal and a boost circuit configured to output a block selection signal to an output terminal by connecting a current path between a voltage supply node and the output terminal in response to the control signal, and to block the current path in case where the control signal falls from a high voltage level to a low voltage level.

Abstract: A method of driving an array of switches comprising supplying the same drive signal to a first drive terminal of a plurality of the switches of an array and supplying second drive signals to a second drive terminal of each of the plurality of switches, the second drive signal supplied to a first of the switches being of a form selected to close the first switch, the form of the second drive signal supplied to the remaining switches being selected to prevent false activation of those switches.

Abstract: A single pole multi throw switch comprises a first switching unit, a second switching unit coupled to a common port and comprising a parasitic off state capacitance, and a matching unit. The matching unit may be coupled between the first switching unit and the common port, wherein the matching unit is configured to contribute, in conjunction with the parasitic off state capacitance of the second switching unit, to an impedance match if the first switching unit is active and the second switching unit is inactive.

Abstract: A dynamically self-bootstrapping circuit for a switch features a resistor in series with the control node of the switch. A bypass switch connects a control node to ground. When the switch is in an off-state, the bypass switch is enabled.

Abstract: An isolation circuit is provided. The isolation circuit is coupled to an output and an input node and includes a first set, a second switch set, and a body bias voltage generator. The first switch set couples a switch control node to a second voltage when a first voltage is at a first voltage level, and couples the switch control node to the input node when the first voltage is at a second voltage level. The second switch set couples the output node to the input node when the first voltage is at the first voltage level, and isolates the output node from the input node when the first voltage is at the second voltage level. The body bias voltage generator selectively provides a higher one of the first voltage and a voltage on the input node to a body of the second switch set.

Abstract: A component with a functionally-configurable circuit arrangement, has a first switch group with a voltage-dependent switching on or off of a data line and at least one second switch group generating two discrete output voltages separated by an increase in voltage and the switch states for the discrete output voltages may be stored in non-volatile memory. The switching on or off of the data line is determined by the switch state of the first switch group and a third switch group (11) is provided to increase the voltage increase between the first switch group (17) and the second switch group (3).

Abstract: Switches with variable control voltages and having improved reliability and performance are described. In an exemplary design, an apparatus includes a switch, a peak voltage detector, and a control voltage generator. The switch may be implemented with stacked transistors. The peak voltage detector detects a peak voltage of an input signal provided to the switch. In an exemplary design, the control voltage generator generates a variable control voltage to turn off the switch based on the detected peak voltage. In another exemplary design, the control voltage generator generates a variable control voltage to turn on the switch based on the detected peak voltage. In yet another exemplary design, the control voltage generator generates a control voltage to turn on the switch and attenuate the input signal when the peak voltage exceeds a high threshold.

Abstract: A radio frequency semiconductor switching device (S) is formed on an MMIC structure (C) including a switching circuit element (12) having four semiconductor switching units (68, 70) with each adapted for receiving a gate control signal. A level shift circuit (10) generates a biasing voltage signal communicated of the switching units (68, 70) for biasing the switching units (68), and provides an output that swings between approximately one diode drop above ground and a negative voltage to bias the switching circuit elements (68 and 70) for reduced loss. The level shift circuit (10) is responsive to an externally provided control signal (58). The switching units (68, 70) are formed into a grouping of at least, a first and a second set (76, 78) of interconnected semiconductor switching units (68, 70) with each set (76, 78) having gates of at least two of the interconnected switching units (68, 70) connected with the level shift circuit output (60, 62).

Abstract: A method for controlling a switch based on transistors is disclosed. A switching circuit for switching a signal from an input port to an output port thereof is provided. A shunting circuit for switchably shunting the signal from the input port to ground is also provided. A control signal is generated for biasing a control port of the shunting circuit and an approximately complimentary control signal is generated for biasing of the switching circuit to either shunt a signal received at the input port or to switch the signal to the output port. A further bias signal for biasing a port within the switching circuit along the signal path between the input port and the output port is also provided.

Abstract: A semiconductor switch is provided with a main element having reverse conductivity and serving as a voltage-driven switching element having a high withstand voltage, an auxiliary element serving as a voltage-driven switching element having a withstand voltage lower than that of the main element, and a high-speed freewheel diode having a withstand voltage equal to that of the main element, wherein a negative pole of the main element is connected to a negative pole of the auxiliary element to define the positive pole of the main element as a positive pole terminal and the positive pole of the auxiliary element as a negative pole terminal, and the high-speed freewheel diode is parallel-connected between the positive pole terminal and the negative pole terminal so that a direction from the negative pole terminal toward the positive pole terminal constitutes a forward direction.

Abstract: A device capable of bidirectional on-off switching control of an electric circuit. Included is a normally-on HEMT connected between a pair of terminals of the device. A normally-off MOSFET of relatively low antivoltage strength is connected between the HEMT and one of the pair of terminals, and another similar MOSFET between the HEMT and the other of the terminal pair. A diode is connected in inverse parallel with each MOSFET, and two other diodes are connected between the gate of the HEMT and the pair of terminals respectively. The switching device as a whole is normally off.

Abstract: A semiconductor relay of the invention includes first and second signal terminals, a substrate, a first switch circuit and a control circuit. The substrate includes signal patterns for forming a signal line between the first and second signal terminals. The first switch circuit has a semiconductor switch used to make or break the connection between the first and second signal terminals. The control circuit has a control IC for controlling the first switch circuit. The control IC is mounted on a land of the substrate. The land has a size corresponding to the control IC. A part or all of the land is included in a part of the signal patterns.

Abstract: An amplified signal switching system comprises a plurality of transducers, and a switch operable for diverting amplified transient signals to selected transducers and preventing the amplified transient signals from being sent to non-selected transducers, wherein the amplified transient signals are AC or acoustic signals, wherein the plurality of transducers comprise a plurality of speakers, and wherein the plurality of transducers are isolated from one another. The switching system further comprises an amplifier operable for sending the amplified transient signals to the switch. The switch selectively turns the amplified transient signals on and off to the selected transducers in order to prevent the non-selected transducers from receiving the amplified transient signals. Moreover, the switch minimizes signal distortion in the selected transducers, and alternatively, the switch eliminates signal output to the non-selected transducers.

Abstract: An object is to provide a conduction switching circuit, an operation method of a conduction switching circuit, and a conduction switching circuit block, which can prevent a leakage of a high frequency signal without insertion loss of a reactance. A conduction switching circuit includes a first MOSFET, a second MOSFET connected to the first MOSFET via a first node, and a first control terminal connected to the first node. The first MOSFET and the second MOSFET are provided so as to be electrically connected in series at ON state. The first control terminal is configured to apply a voltage to the first node so that capacitance of the first MOSFET and the second MOSFET is decreased when the first MOSFET and the second MOSFET are OFF state.

Abstract: An embodiment of the invention relates to a switching system that includes a depletion-mode semiconductor device, such as a silicon carbide device, coupled in series with an enhancement-mode semiconductor device, such as a silicon field effect transistor, so that a controller can be configured to disable conductivity of the series arrangement of the two switches during a transient operating condition. During normal high-frequency switching operation, the controller persistently enables the enhancement-mode device to conduct while intermittently enabling the depletion-mode device to conduct. The controller disables the enhancement-mode device to conduct during a transient operating condition such as start up or during a fault, thereby providing circuit protection during such transients. The switching system preserves low loss switching characteristics of the depletion-mode device in a high-frequency switching circuit.

Abstract: A packaged switching device for power applications includes at least one pair of power MOSFET transistor dies connected between upper and lower power source rail leads, a high side one of the pair of MOSFET transistor dies being connected to the upper power source rail lead and a low side one of the pair of MOSFET transistor dies being connected to the lower power source rail lead. At least one of the MOSFET transistor dies is configured for vertical current flow therethrough and has a source electrode at a backside thereof.

Abstract: A switch circuit device with improved insertion loss characteristics and isolation characteristics is provided. The switch circuit of the present invention includes a plurality of n-ch MOSFETs whose gates are connected together and whose drains and sources are connected in series, a p-ch MOSFET whose gate is connected to the gates of the plurality of n-ch MOSFETs and whose drain is connected to the source and drain of at least one pair of adjacent n-ch MOSFETs, and a voltage changing circuit for applying a low voltage to the source of the p-ch MOSFET while a high-level control voltage is applied to the gate of the p-ch MOSFET, and a high voltage to the source of the p-ch MOSFET while a low-level control voltage is applied to the gate of the p-ch MOSFET.

Abstract: Disclosed is a circuit arrangement comprising feedback protection for switching the current flow in power applications. Said circuit arrangement comprises two serially connected MOSFETs (1, 2) on the conductor branch that is to be switched. Said MOSFETs are connected such that the inverse diodes thereof are arranged opposite each other regarding the PN junction.

Abstract: A pad circuit includes a pad, a gate driving circuit, a voltage selection circuit, and an ESD detection/avoiding circuit. The gate driving circuit is used to discharge the ESD induced current. The ESD detection/avoiding circuit is used to isolate the ESD induced voltage. The voltage selection circuit selects a higher voltage from a power/ground terminal and the pad and outputs it to the gate driving circuit, so that the pad circuit can be used for the programming and 1/0 operations.

Abstract: A semiconductor device includes a first switching device including a first electrode coupled with a first node, a second electrode coupled with a second node, and a first control electrode controlling connection between the first and second electrodes; a second switching device including a third electrode coupled with the second node, a fourth electrode coupled with the second node, and a second control electrode controlling the connection between the third electrode and the fourth electrode; and a first control circuit controlling a substrate voltage of the second switching device.

Abstract: In the case of an electronic circuit, comprising a drive unit, which generates at least one drive signal, two or more power semiconductor switches each having a first and a second main terminal, which power semiconductor switches can be switched synchronously by the drive signal, the first and the second main terminals of the power semiconductor switches in each case being electrically connected in parallel among one another, for each of the power semiconductor switches a first and a second electrically conductive connection for connection to the drive unit, a uniform dynamic current division between the power semiconductor switches is achieved according to the invention by virtue of the fact that a first inductance is provided in each of the first electrically conductive connections, and a second inductance is provided in each of the second electrically conductive connections, the first inductance being coupled to the second inductance for each of the power semiconductor switches.

Abstract: A power switching circuit in CMOS technology has a power MOS transistor and a driver stage. The power MOS transistor is operated at a higher supply voltage in excess of its maximum allowable gate-source voltage; and the driver stage of the level shifter is operated at a lower supply voltage substantially lower than the supply voltage for the power MOS transistor. The driver stage includes a pair of driver MOS transistors coupled in series between a higher supply voltage rail and a reference potential rail, and at an interconnection node coupled to the gate of the power MOS transistor. The gates of the driver MOS transistors are AC-coupled to drive signals of mutually opposite phase; and the gates of the driver MOS transistors are each connected to the higher voltage supply rail through a respective parallel connection of a first resistor and a second resistor connected in series with a non-linear component.

Abstract: A stacked MOS configuration for use in short channel length analog circuit technologies is provided. The stacked MOS configuration comprises a plurality of short-channel MOS transistors coupled in series and sharing a common gate terminal. In an embodiment, a first peripheral transistor provides a drain terminal for the stacked MOS configuration. A second peripheral transistor provides a source terminal for the stacked MOS configuration. Adjacent transistors in the stacked MOS configuration are connected in a drain-to-source configuration.

Abstract: A monolithic interface circuit for providing a voltage, from a control circuit supplied by a supply voltage referenced to a reference voltage, to a terminal likely to be at a high voltage with respect to the reference voltage, comprising a high-voltage N-channel MOS transistor having its gate intended to receive a control signal referenced to the reference voltage and having its source intended to be connected to the reference voltage, and a high-voltage PNP transistor having its base connected to the drain of the MOS transistor, having its emitter intended to receive the supply voltage and having its collector intended to provide a voltage to the terminal likely to be at a high voltage.

Abstract: An embodiment of the invention relates to a switching system that includes a depletion-mode semiconductor device, such as a silicon carbide device, coupled in series with an enhancement-mode semiconductor device, such as a silicon field effect transistor, so that a controller can be configured to disable conductivity of the series arrangement of the two switches during a transient operating condition. During normal high-frequency switching operation, the controller persistently enables the enhancement-mode device to conduct while intermittently enabling the depletion-mode device to conduct. The controller disables the enhancement-mode device to conduct during a transient operating condition such as start up or during a fault, thereby providing circuit protection during such transients. The switching system preserves low loss switching characteristics of the depletion-mode device in a high-frequency switching circuit.