Abstract: A signal-receiving and signal-processing unit connected to one or several conductors is configured to transmit information-carrying signals in the form of voltage pulses. The conductor is connected to a transistor in a signal-receiving circuit to affect a current by using variations in the voltage pulses and the voltage value of a pulse. The current is in the form of pulses that pass through the transistor. The current is generated by the voltage pulse variations and voltage level. The current is given a signal-adapted information-carrying form by a signal-processing circuit. The transistor in the signal-receiving circuit is coordinated with at least one other transistor so that together they form a current mirror circuit.

Abstract: A buffer circuit, such as for use with a low voltage hearing aid, is disclosed. The hearing aid comprises a microphone, a receiver and an amplifier. The amplifier is disposed between the microphone and the receiver. The buffer circuit has a MOS device including a well terminal and a gate terminal equipotentially coupled together to reduce the effective threshold voltage of the MOS device, thereby reducing the gate-to-source voltage of the MOS device. This permits a greater linear output signal range for the amplifier.

Abstract: A bi-directional ring bus structure is formed on an integrated circuit from a conductive bus and M X:1 multiplexer modules (where M is an integer .gtoreq.2), coupled in a point-to-point configuration. Each module is associated with an input/output port that can communicate with the bus. Each module has an output port (Dout), and arbitration ("ARB") port, and X input ports ("LOCALout", "Din1", "Din2", . . . "Din[X-1]"). The Dout output port of an M.sub.i module is coupled, via a portion of conductive bus, to [X-1] input ports on an adjacent D.sub.i+1 module. Thus, module M.sub.0 's Dout.sub.0 output port is coupled to [X-1] input ports on module M.sub.1, module M.sub.1 's Dout.sub.1 port is coupled to [X-1] input ports of module M.sub.2, and so forth. The modules are X:1 in that the output port of each module is coupled to a chosen one of that module's X INPUT ports, as determined by the state of an arbitration select signal (ARB) coupled to the module's arbitration port.

Abstract: A circuit and method for reducing voltage error when charging and discharging a storage capacitor (44) through a transmission gate (43). The storage capacitor (44) stores or holds a voltage coupled through the transmission gate (43) when the transmission gate (43) is disabled. The circuit comprises a clock generation circuit (47) providing complementary clock signals for enabling and disabling the transmission gate (43) and a charge negating transmission gate (46). The clock generation circuit (47) provides the complementary clock signals simultaneously to the transmission gates (43, 46). Alternate paths for dissipating channel charge of the transistors which comprise the transmission gate (43) are not formed by providing the complementary clock signals simultaneously. The channel charge is then canceled by the charge negating transmission gate (46) reducing voltage error on the storage capacitor (44).

Abstract: A high speed CMOS current switching circuit suitable for use in digital to analog converters for graphic interfaces having high pixel clock rates, and such interfaces as may be used in portable and other battery operated or low power consumption applications. In operation, the current switching circuit normally steers an idle current to ground. If the bit of the digital to analog converter input digital signal represented by the respective source is a 1, the input signal representing the bit is delayed slightly while the current steered to ground is increased from the idle value to the full desired output current, whereupon at the end of the delay, the device coupling the output current to ground is turned off, thereby forcing the output current through an output device. A low power current steering circuit which can perform dynamic current steering without affecting switching speed performance is also disclosed.

Abstract: An output driver circuit for preventing the emission of high-frequency signals, including two MOS output transistors (M2, M1) which are connected in series between the supply voltage (Vcc) and ground, and two capacitors (C1, C2) which are arranged between the output node (N1) and the gate of a respective output transistor. The voltages on the gates of the output transistors are quickly increased to the conductivity threshold before a transition occurs on the output, whereby acceleration circuits supply the gates of the output transistors with high currents. During the transition of the output signal, the acceleration circuits are switched off and smaller currents are applied to the gates of the output transistors; the capacitances (C1, C2), being connected in phase opposition, prevent excessively fast variation of the voltage on the output node.

Abstract: The coupled switching transistors of the digital current switch are connected to a controlled current source. Load resistors of the current switch are formed as controlled resistors. The L-level produced by a reference current branch is compared with a predetermined level by means of a regulating device which includes the reference current branch and a compensator, and the controlled resistor or the controlled current source are adjusted such that the L-level is equal to the predetermined level.

Abstract: A switch circuit for a charge pump circuit is disclosed. The switch circuit has a first transistor for conducting current and is controlled by a second, third, and fourth transistor. The second transistor protects the first transistor for excessive gate-to-drain voltage. The third transistor receives the signal for switching the switch circuit and also serves as a cascoding transistor for protecting the fourth transistor from excessive gate-to-drain voltage. Consequently, the switch circuit can withstand high gate-to-drain voltages and has increased reliability. The switch also has a turn-off circuit to facilitate the depletion of charge on the control element of the first transistor. The switch circuit also has a zener diode to insure that excessive voltage is not applied across the gate-to drain of the first transistor.

Abstract: An electronic switch for sampling a signal. A small switch is placed in parallel with a large switch. The large switch is opened first. Any residual charge from the large switch is compensated by a low impedance path through the small switch. Speed is maximized by providing high current capacity through the large switch. Noise is minimized by leaving only residual charge from the small switch. Example embodiments are provided for sampling both voltage and current signals.

Abstract: An analog switch includes first and second thin film field effect transistors having their gate connected in common to a control terminal. Current paths of the first and second thin film field effect transistors are connected in series between an input terminal and a capacitive load. A voltage adjusting capacitive element is connected to a common connection between the current paths of the first and second thin film field effect transistors.

Abstract: A semiconductor device includes an input/output terminal, an internal circuit connected to the input/output terminal, a first terminal for providing a first electrical potential, and a second terminal for providing a second electrical potential which is lower than the first electrical potential, the device further including: a first n-channel MOS transistor having a drain connected to the input/output terminal, a source connected to the second terminal, and a gate to be electrically connected to the first terminal; and a first switching element for switching between an electrically conductive state and a non-conductive state between the drain and the gate of the first n-channel MOS transistor, the switching element forming the electrically conductive state between the drain and the gate of the first n-channel MOS transistor when 1) a surge voltage lower than the first electrical potential is applied to the input/output terminal, and 2) an electrical potential difference between the drain and the gate of the f

Abstract: A high voltage circuit for an electronic erasable programmable read only memory (EEPROM) integrated circuit (IC) is implemented using lower voltage semiconductor components. In the preferred embodiment, the circuit is capable of switching a twenty-four volt signal using p-channel metal-oxide semiconductor field effect transistors (MOSFETs) with a rated breakdown voltage not exceeding twelve volts. In the preferred embodiment, the circuit switches a driver signal in response to a first control signal.

Abstract: A semiconductor memory device which is capable of reducing a delay in the conversion of an input chip enable signal having a TTL level, providing a quick chip enable access and avoiding an increase in current consumption despite the quick chip enable access. The semiconductor memory device in one embodiment includes an input buffer outputting a signal having a CMOS level in response to a chip enable signal having a TTL level, and having a plurality of transistors whose gate lengths are set to first dimensions, and a second input buffer activated in response to both another input signal having a TTL level and the signal having the CMOS level, and having a plurality of transistors whose gate lengths are set to second dimensions greater than the first dimensions.

Abstract: A semiconductor integrated circuit comprises an input signal terminal to which an input signal is supplied from an outer unit, a plurality of input voltage sensing circuits each having a different circuit threshold value and connected to the input signal terminal, for sensing whether a voltage of the input signal is higher or lower than a predetermined normal level, a power supply voltage sensing circuit for sensing whether a power supply voltage applied from another outer unit is a normal power supply voltage or a voltage different from the normal power supply voltage, a selection circuit for selecting a corresponding one from a plurality of the input voltage sensing circuits in accordance with an output of the power supply sensing circuit, and an internal circuit to which an output of a selected one of the input voltage sensing circuits is connected.

Abstract: A switched capacitor circuit includes a capacitor, a MOS switch and a timing generating circuit. The MOS switch is connected with the capacitor in series for discharging electric charges which are charged into the capacitor. The MOS switch includes a plurality of MOS transistors which are parallelly connected with each other. The timing generating circuit generates timing signals to the MOS switch so that the MOS transistors are turned on one after another in response to each timing signal. Sampling noise is reduced because an ON-state resistance of the MOS switch is transiently high.

Abstract: A high voltage circuit includes a first switching device for supplying one of a high voltage (V.sub.pp) and a low voltage (V.sub.cc) to a controlled path that includes a series connection of a control p-channel transistor and a protection p-channel transistor. A high voltage detector is utilized to determine whether V.sub.pp or V.sub.cc is applied to the controlled path. The high voltage detector also establishes a protecting condition for the protection p-channel transistor during V.sub.pp operation. On the other hand, the detector establishes a non-protecting condition during V.sub.cc operation, thereby rendering the protecting p-channel transistor transparent to circuit performance. A signal input switches the control p-channel transistor between on and off states.

Abstract: A low-input capacitance self-biased CMOS buffer amplifier (10) which buffers a low-amplitude capacitively coupled output of a sensor to subsequent output circuitry. The buffer amplifier (10) includes a buffer stage (12) which includes an input FET (16) whose gate terminal is connected to the output of the sensor. In order to eliminate the gate-to-source, gate-to-drain and gate-to-substrate capacitances of the input FET (16), various FETs are associated with the buffer stage (12) are interconnected such that the integrity of the input signal is maintained. An output FET (18) has its source terminal connected to the source terminal of the input FET (16). Additionally, a tail cascoded current source (20, 22) is connected to the source terminals of the input and output FETs (16, 18) such that the gate-to-source voltages of these two FETs (16, 18) is the same. The gate terminal and the drain terminal of the output FET (18) are connected such that the input and output FETs (16, 18) act as unit to gain amplifier.

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and also bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention.

Abstract: In a CMIS device having a semiconductor substrate including a first N-type region and a P-type region, a second P-type region is formed within the first N-type region, and a second N-type region is formed within the first P-type region. Also, a third N-type region is formed within the second P-type region, and a third N-type region is formed within the second N-type region. An N-channel transistor is formed by the first N-type region as a drain, the second P-type region as a channel, and the third N-type region as a source. A P-channel transistor is formed by the first P-type region as a drain, the second N-type region as a channel, and the third P-type region as a source.

Abstract: An inverter circuit for providing a high voltage output has an input terminal and an output terminal. The circuit further includes a first conductivity type first field effect transistor connected between a first power source line and the output terminal and having a gate electrode connected to the input terminal and second conductivity type second to (n+1)th field effect transistors connected in series between the output terminal and a ground line and having gate electrodes respectively connected to the input terminal. A voltage supply supplies (n-1) in number of second to (n)th power source voltages, whose absolute values become smaller in order, to a respective junction of the series connected second to (n+1)th transistors when the second to (n+1)th transistors are in OFF state.

Abstract: There is disclosed an integrated circuit having a buffer that includes an output driver for receiving data and for transferring the data to an output node to be placed on a bus. The buffer also includes a pull-up control device coupled to the output node. The control device is capable of being switched between a first state that couples the output node to a predetermined logic level and a second state that does not couple the output node to the predetermined logic level. Control logic coupled to the pull-up control device receives first and second logic signals to control the state of the control device. With the second logic signal in a first predetermined level, the first logic signal is capable of switching the control device to the first state when in a first predetermined state and to the second state when in a second predetermined state. The second logic signal when in a second predetermined level overrides the control of the first logic signal to maintain the control device in the second state.

Abstract: A MOS-based current-switch/driver multiplexed and coupled with a tapped delay line so as to form a generator for transmitting on unshielded, unfiltered transmission lines highly-symmetric data pulses displaying minimal transient aberrations and minimal common-mode noise. The switch/driver is a basic differential current switch incorporating two MOS output transistors controlled by a novel switching means. The novel switching means ensures the symmetry of the output signals by compensating for the turn-on/turn-off asymmetries inherent in MOS transistors. The compensation is provided by the control circuit interposed between the switch/driver inputs and the control gates of the output transistors, a control circuit which includes deliberately-skewed CMOS inverters and a pair of MOS driver-transistors associated with each output transistor. The output signals from these current generators are referenced to ground.

Abstract: A CMOS motor drive for a disk drive spindle motor. The design of the drive circuit permits the integration of power electronics together with logic or other circuitry on a single integrated circuit wafer. For each motor phase the power electronics formed on the integrated circuit wafer includes a plurality of P-type and N-type MOSFET power transistor pairs and a plurality of corresponding output bonding pads; the drain terminals of each transistor pair being connected together to its corresponding output bonding pad. The wafer is enclosed in packaging which includes an output pin for providing an electrical connection to one phase of the disk drive spindle motor, and a plurality of bond wires corresponding to the plurality of output bonding pads, each bond wire providing an electrical connection between its corresponding bonding pad and the output pin. The transistor pairs and bond wires operate in parallel, each carrying an equivalent portion of the total current output presented at the output pin.

Abstract: The present invention relates to an output circuit and a semiconductor integrated circuit. It is an object of the present invention to cut off a passage of a current through a forward parasitic diode of a transistor connected to a power supply line and a ground line at a time of suspension of output operation of the relevant circuit, and to raise an output high level to the utmost and lower an output low level to the utmost at time of normal output operation.

Abstract: An integrated circuit (40) has a low-power mode in which at least one switched inverter stage (60) of a clock amplifier (41) is disabled in response to a stop signal. The stop signal indicates that the integrated circuit (40) is in low-power mode. In one embodiment, each switched inverter stage is a complementary metal-oxide-semiconductor (CMOS) switched inverter (60), in which an additional P-channel transistor (61) is connected between the source of an inverter P-channel transistor (62) and a positive power supply voltage terminal, and in which an additional N-channel transistor (64) is connected between a source of an inverter N-channel transistor (63) and a negative power supply voltage terminal. A non-switched inverter stage (52) remains active during low-power mode to maintain a DC value of a clock input signal near a switchpoint of the clock amplifier (41).

Abstract: A low distortion CMOS switch system includes a plurality of N-channel and a plurality of P-channel transistors with their drain and source terminals connected in parallel for receiving an input signal to be switched; and a control circuit for providing a different positive drive voltage to the gate of each of the N-channel transistors and a different negative drive voltage to the gate of each of the P-channel transistors to produce substantially constant "on" resistance, R.sub.ON, throughout the range of the switched signal conducted through the drain and source terminals, and for providing the same negative drive voltage to the gate of each of the N channel transistors and the same positive drive voltage to the gate of each of the P channel transistors to turn off the transistors.

Abstract: An integrated circuit output buffer that operates at a low power supply voltage (e.g., 3.3 volts) shares an I/O bondpad with input circuitry that operates at a higher voltage (e.g., 5 volt) signal level. The higher voltage signal level is typically obtained by connection of the bondpad to a bus that is connected to one or more output buffers on other IC's that operate at the higher power supply voltage level. The inventive output buffer obtains a decreased propagation delay by the use of an additional pull-up transistor in a configuration that protects the low voltage output transistors, including the additional transistor, from the higher voltage signal levels present on the bondpad. In this manner, the output buffer may be used in applications that require the relatively low propagation delay specified for the PCI bus, for example.

Abstract: A semiconductor integrated circuit device comprising a temperature sensor including an element having a PN junction, an inverter for receiving an output of the temperature sensor, and a controller for controlling supply of an electric energy to a group of MOS integrated circuit elements on the basis of an output of the inverter, wherein the supply of the electric energy to the group of MOS integrated circuit elements is controlled on the basis of the output of the temperature sensor to automatically prevent the breakdown of the internal circuit due to excessive temperature rise by the device itself.