Abstract: Provided are a protecting device capable of safely and quickly interrupting a current path by restricting heat absorption to a lower case, and a battery pack using the same. A protecting device includes: a meltable conductor 3; and a housing 6 including a lower case 4 and an upper case 5, the housing being formed by joining the lower case 4 and the upper case 5, and the lower case 4 is provided with a recessed portion 23 having support portions 21 provided at opposing side edges of the recessed portion 23 and hollow portions 22 provided on the side edges substantially orthogonal to the side edges of the recessed portion 23 on which the support portions 21 are provided.

Abstract: A trimming method for adjusting electrical characteristics of an adjustment circuit, which is provided in a semiconductor substrate, by cutting a fuse resistor provided in the semiconductor substrate. In a case where a cutting current flows to the fuse resistor to cut the fuse resistor, at least one of switching devices provided in the semiconductor substrate is set to a conductible state to make the cutting current flow to the switching device.

Abstract: The present disclosure provides a method for forming semiconductor structures. The method includes providing a device having a substrate, a first dielectric layer over the substrate, and a first conductive feature over the first dielectric layer, the first conductive feature comprising a first metal, the first metal being a noble metal. The method also includes depositing a second dielectric layer over the first dielectric layer and covering at least sidewalls of the first conductive feature; etching the second dielectric layer to form a trench; and forming a second conductive feature in the trench. The second conductive feature comprises a second metal different from the first metal.

Abstract: The present application provides example terminal chips. One example terminal chip includes a security element, an application processor, and an interface module configured to transfer information between the application processor and the security element. The terminal chip includes a first power interface configured to receive power outside the terminal chip. A first power input port of the security element is connected to the first power interface, and at least one of the application processor or the interface module is connected to the first power interface. In the example terminal chip, a power supply port of the security element is connected to a power supply port of the application processor or the interface module of the terminal chip.

Abstract: A spiral inductor includes a spiral trace and a plurality of first projections extending along a first edge of the spiral trace. The spiral inductor may further include a plurality of second projections extending along a second edge of the spiral trace, the second edge being opposite the first edge.

Abstract: Techniques are provided for non-volatile detection of an overvoltage condition in a circuit of interest. A circuit implementing the techniques according to an embodiment includes a fuse configured to provide a non-volatile indication of an overvoltage event, the indication associated with an open state of the fuse. The circuit also includes a voltage controlled current switch coupled in series to the fuse. The voltage controlled current switch is configured to enable current flow through the fuse in response to a supply voltage exceeding a threshold value associated with the overvoltage event. The current causes the fuse to switch from a closed state to an open state providing a non-volatile record of the overvoltage event. In some embodiments, the voltage controlled current switch can be a Zener diode with a breakdown voltage based on the threshold value, or a transistor configured to switch into conducting mode at the threshold value.

Abstract: A circuit including a device including a first and second node. The device operating in at least an enabled mode and a disabled mode. The circuit including a voltage control circuit. The voltage control circuit including a current source for sourcing current to or sinking current from the first node during the disabled mode and a voltage difference detector including an output for providing an indication of a measured voltage difference between the first node and the second node. The voltage control circuit includes a current source control circuit including a first input to receive the indication of the measured voltage difference and an output to control current sourced to or sinked from the first node by the current source to limit a voltage difference between the first and second node based on a comparison between the indication of the measured voltage difference and an indication of a target voltage difference.

Abstract: The power control device reliably disconnects the current path of the failed output transistor. In particular, the power control device includes output transistors, an output terminal, bonding wires connecting the output transistors to the output terminal, output transistor driving circuits controlling the output of the output transistors, and a failure detection circuit detecting the failure of the output transistors. When the failure detection circuit detects the failure of the output transistors and outputs the failure detection signals, the output transistor drive circuits control the outputs of the output transistors so that a larger current flows through the bonding wires than when the failure is not detected.

Abstract: Provided is a circuit for generating a bias current, which includes a current generation unit including a plurality of current mirrors that generate a plurality of currents having different levels. The circuit also includes a current generation control unit that controls the generating the plurality of current having different levels in the current generation unit based on an externally input current. The circuit further includes a current supplying unit that supplies a current selected from the plurality of currents having different levels to an external device.

Abstract: A transient electronic device includes electronic elements (e.g., an SOI- or chip-based IC) and a trigger mechanism disposed on a frangible glass substrate. The trigger mechanism includes a switch that initiates a large trigger current through a self-limiting resistive element in response to a received trigger signal. The self-limiting resistive element includes a resistor portion that generates heat in response to the trigger current, thereby rapidly increasing the temperature of a localized (small) region of the frangible glass substrate, and a current limiting portion (e.g., a fuse) that self-limits (terminates) the trigger current after a predetermined amount of time, causing the localized region to rapidly cool down.

Abstract: A pyrotechnic cut-off device to be connected to an electrical circuit to cut-off, includes a pyrotechnic initiator, a first and a second conductive portion each intended to be connected to the electrical circuit, the second portion being connected in parallel with the first portion and including two conductive elements separated by an insulating segment, at least one of the conductive elements provided with a first fuse element connected in series which is configured to trip when the intensity of the current passing therethrough exceeds a first predetermined value, and a first and a second insulating protrusion, each protruding from a lower face of a movable piston and the first and the second protrusions being located respectively in front of the first portion and the insulating segment. The pyrotechnic initiator is configured to switch the cut-off device from a first current passage configuration to a second current cut-off configuration.

Abstract: Disclosed are apparatuses and methods for controlling gate-induced drain leakage current in a transistor device. An apparatus may include a first biasing circuit stage configured to provide a biasing voltage on a biasing signal line, the biasing voltage based on a current through a first resistor associated with the first biasing circuit stage, a voltage generation circuit stage coupled to the first biasing circuit stage, the voltage generation circuit stage having an output transistor that is coupled to the biasing signal line through a gate terminal of the output transistor, and an output line coupled to the voltage generation circuit stage and configured to provide an output voltage signal having a steady-state voltage that is less than a power supply voltage by an amount that corresponds to a voltage drop across the first resistor associated with the first biasing circuit stage.

Abstract: Devices and systems are provided that incorporate fusible links within the electrical traces of a battery module voltage sensing circuit. The fusible links can be integrally formed in an electric trace and provide an overcurrent protection feature for the circuit without requiring fuse elements or components that are separate from the electrical trace. Each of these fusible links include a substantially flat controlled cross-sectional area disposed along a length of the material making up the electrical trace. In an overcurrent situation, the connection between a battery management system and a battery cell may be severed by the overcurrent melting the fusible link. The electrical traces may be spaced apart from one another in the circuit such that an overcurrent situation breaking the connection between one cell and the battery management system would not affect adjacent electrical traces not having an overcurrent situation.

Abstract: Protection circuit and integrated circuit are provided. A protection circuit includes a discharge passage, configured to perform an electro-static discharge and a controller configured to blow out the electric fuse after the discharge passage fulfills electro-static discharge. The discharge passage includes an electric fuse.

Abstract: A data processing system includes an SRAM array, wherein the plurality of SRAM cells provide a physically unclonable function (PUF). A PUF evaluation engine includes a selection circuit for selecting one or more word lines coupled to the plurality of SRAM cells in response to a challenge, and a cross-coupled latch coupled to two bit lines corresponding to two different SRAM cells of the plurality of SRAM cells. The cross-coupled latch is configured to provide one of two 2-bit values depending on which of the two bit lines discharges faster upon the two different SRAM cells being selected by the selection circuit, wherein the 2-bit value is part of a digital code provided in response to the challenge.

Abstract: A circuit includes a digital-to-analog converter (DAC) having a DAC input and a DAC output. The circuit includes a reference voltage (VREF) generator having a VREF generator input, a VREF generator output, and a VREF power supply input. The VREF generator output is coupled to the DAC input. A voltage regulator has a voltage regulator input and a voltage regulator output. The voltage regulator output is coupled to the DAC. A clamp circuit has a first clamp circuit input, a second clamp circuit input, and a clamp circuit output. The first clamp circuit input is coupled to the voltage regulator input, and the clamp circuit output is coupled to the VREF power supply input. The second clamp circuit input is coupled to the voltage regulator output. The clamp circuit includes a source-follower circuit having the second clamp circuit input.

Abstract: An E-fuse burning circuit comprising: a burning directing circuit, configured to receive first input data comprising first input address and burning directing data, to generate a burning directing signal according to the burning directing data; a ring address latch, configured to latch the first input address responding to a first clock signal, and configured to output second input address responding to the first clock signal; and a control signal generating circuit, configured to generate at least one stop signal to determine whether the data in the ring address latch is shifted or not. The ring address latch applies a first number of the stages when the burning directing signal indicates a row of the E-fuse circuit is to be burned and applies a second number of the stages when the burning directing signal indicates a column of the E-fuse circuit is to be burned.

Abstract: A high speed VPP level translator circuit using thin-oxide field effect transistors (FETs) and methods of use are disclosed. The level translator includes a resistor divider and a one-shot circuit in parallel with the resistor divider. The one-shot circuit conducts to assist a transition from a first state to a second state, and is non-conducting during the transition from the second state to the first state.

Abstract: Electrical current sensing and monitoring methods include connecting a compensation circuit across a conductor having a non-linear resistance such as a fuse element. The compensation circuit injects a current or voltage to the conductor that allows the resistance of the conductor to be determined. The current flowing in the conductor can be calculated based on a sensed voltage across the conductor once the resistance of the conductor has been determined.

Abstract: An angle sensor includes a detection signal generation unit for generating detection signals, and an angle detection unit for generating a detected angle value on the basis of the detection signals. The angle detection unit includes a signal conversion unit for performing a conversion operation, and an angle operation unit for performing an angle operation. The conversion operation is to convert the detection signals into first and second operation signals. The angle operation is to calculate the detected angle value using the first and second operation signals. The conversion operation includes an operation using a correction-term-containing function which contains a correction term for reducing a first error or a second error occurring in the detected angle value. When the angle to be detected varies with a predetermined period, the first error varies with the predetermined period, whereas the second error varies with a period ½ the predetermined period.

Abstract: Semiconductor fuses with nanowire fuse links and fabrication methods thereof are presented. The methods include, for instance: fabricating a semiconductor fuse, the semiconductor fuse including at least one nanowire fuse link, and the fabricating including: forming at least one nanowire, the at least one nanowire including a semiconductor material; and reacting the at least one nanowire with a metal to form the at least one nanowire fuse link of the semiconductor fuse, the at least one nanowire fuse link including a semiconductor-metal alloy. In another aspect, a structure is presented. The structure includes: a semiconductor fuse, the semiconductor fuse including: at least one nanowire fuse link, the at least one nanowire fuse link including a semiconductor-metal alloy.

Abstract: A reference voltage generator may include a voltage division unit configured to receive an external voltage, and divide the external voltage into a plurality of divided voltages. The reference voltage generator may include reference voltage output units configured to trim the divided voltages received from the voltage division unit according to a division control signal, and output supply reference voltages. The reference voltage output units may be symmetrically arranged at both sides of the voltage division unit.

Abstract: Apparatus and methods for protection against inadvertent programming of fuse cells are provided herein. In certain configurations, a fuse system includes a fuse programming transistor, a cascode transistor, and a fuse cell electrically connected in series between a first pad and a second pad. The fuse system further includes a bias generator that controls an amount of current provided to the fuse cell based on biasing a gate of the fuse programming transistor and a gate of the cascode transistor. The fuse system further includes a fuse protection capacitor electrically connected between the first pad and the gate of the cascode transistor to prevent inadvertent programming of the fuse cell in response to an increase in voltage of the first pad relative to the second pad.

Abstract: A fusible link unit includes: a fuse element including a plurality of fusible portions arrayed in a predetermined array direction; a housing having a window portion penetrating the housing in an intersecting direction to intersect the array direction; and fusible portion covers attached to the housing. The housing holds the fuse element to locate the fusible portions inside the window portion. The fusible portion covers includes a first cover that is transparent and has a plate shape extending in the array direction and covering one opening of the window portion and a second cover that is non-transparent and having a plate shape extending in the array direction and covering the other opening of the window portion. A length of the first cover in the array direction is different from a length of the second cover in the array direction.

Abstract: A memory device may include an application chip set including a plurality of applications. The memory device may include a chip decoder configured to select one application among the applications in response to input data and a test fuse signal, and output function data so that a function to be performed by the selected application is selected.

Abstract: A method and system are used to generate random values for Physical Unclonable Function (PUF) for use in cryptographic applications. A PUF value generation apparatus comprises two dielectric breakdown based anti-fuses and at least one current limiting circuit connected between anti-fuses and power rails. Two anti-fuses are connected in parallel for value generation in programming by applying high voltage to both anti-fuses at the same time. Time for dielectric breakdown under high voltage stress is of random nature and therefore unique for each anti-fuse cell. Therefore the random time to breakdown causes one cell to break before another, causing high breakdown current through the broken cell. Once high breakdown current through one broken or programmed cell is established, a voltage drop across a current limiting circuit leads to decreased voltage across both cells, thereby slowing the time dependent breakdown process in the second cell and preventing it from breakage under programming conditions.

Abstract: A voltage regulator provides an output voltage, the voltage regulator configured to receive one of a plurality of different regulator reference voltages and a controller configured to provide a selection signal, the selection signal being used to control which of the regulator reference voltages the voltage regulator receives.

Abstract: Voltage reference circuits configured to generate a voltage reference with a programmable temperature slope are disclosed. By combining and programming a PTAT (Proportional To Absolute Temperature) voltage generation circuit and a CTAT (Complementary To Absolute Temperature) voltage generation circuit, desired temperature slope for the voltage reference is obtained. To adjust both temperature slope and offset of the voltage reference, the voltage reference circuits include a bandgap reference circuit. The bandgap reference circuit is used to create a temperature independent current, which is coupled to a programmable string of resistors and programmable string of MOSFETs to produce a desired temperature slope for the voltage reference. The desired offset of the voltage reference is obtained by the temperature-independent current into another string of programmable resistors. A circuit architecture and method to control the temperature slope and offset of the voltage reference independently is disclosed.

Abstract: A multiplexer (MUX) configured to receive a plurality of input data streams and output an output data stream via an output data line based at least in part upon a control signal, includes: a first circuit portion corresponding to a first data stream of the plurality of input data streams, comprising: a first internal node; a first control switch operable to connect the output data line to the first internal node of the first circuit portion based at least in part upon the control signal, wherein the first internal node has a value corresponding to the first data stream when the output data line is connected to the first internal node; and a first reset switch operable to connect the first internal node to a common mode voltage rail based at least in part upon the control signal to remove or reduce residual charge at the first internal node.

Abstract: Activity data is analyzed or evaluated to detect behavioral patterns and anomalies. When a particular pattern or anomaly is detected, a system may send a notification or perform a particular task. This activity data may be collected in an information management system, which may be policy based. Notification may be by way e-mail, report, pop-up message, or system message. Some tasks to perform upon detection may include implementing a policy in the information management system, disallowing a user from connecting to the system, and restricting a user from being allowed to perform certain actions. To detect a pattern, activity data may be compared to a previously defined or generated activity profile.

Abstract: The invention relates to a destruction system for destroying a functional layer, which may receive data or perform other functions, such as optical functions, for example, and a related method. The reactants may be interspersed within the functional layer or may be provided in a separate layer adjacent to the functional layer. The reactants are structured to be ignited to destroy the functionality of the functional layer and the data. Ignition may be obtained through a flame or by suitable electrical current in certain embodiments of the invention.

Abstract: A wireless Internet gateway bridges wireless devices to the Internet, e.g., via a short message service center (SMSC). The gateway provides a portal to SMPP, HTTP, TNPP, or other protocol messages using Java Remote Method Invocation (RMI) techniques. Application servers insert RMI objects containing messages in a message queue handler of the gateway. The RMI objects are queued and passed either directly to a destination delivery handler (e.g., SMPP, SMTP, HTTP or TNPP protocol handler), or passed through a generic destination interface. An SMTP handler provides direct communication of SMTP protocol messages (i.e., email) to the message queue. An SMPP link proxy module provides direct access between a local application server and the destination delivery handler. The messages are packaged into relevant messages of the particular destination protocol (e.g., SMPP), and transmitted to the relevant network element (e.g., to an SMSC).

Abstract: A semiconductor device includes, an anti-fuse element, a transistor connected via the anti-fuse element to a power source terminal which may apply a voltage to the anti-fuse element, an ESD protection element connected to the power source terminal via a node, and a first resistive element disposed in an electric path between the node and the anti-fuse element, wherein resistance of the first resistive element increases with an increase of a voltage applied to the first resistive element.

Abstract: A memory driving circuit is disclosed herein. The memory driving circuit includes a programmable current source, a reference voltage generation unit and a voltage comparator unit, The programmable current source generates a second current according to a first current. The second current flows into a memory cell, and produces a device voltage at the input of the memory cell. The reference voltage generation unit generates a crystal voltage. The voltage comparator unit compares the device voltage with the crystal voltage and sends out a control signal to control the programmable current source. The first current and the second current are adjusted by the control signal so that the shape of the current pulse of SET operation to the memory cell is well controlled.

Abstract: Apparatuses for memory repair for a memory device are described. An example apparatus includes: a non-volatile storage element that stores information; a storage latch circuit coupled to the non-volatile storage element and stores latch information; and a control circuit that, in a first repair mode, receives first repair address information, provides the first repair address information to the non-volatile storage element, and further transmits the first repair address information from the non-volatile storage element to the storage latch circuit. The control circuit, in a second repair mode, receives second repair address information and provides the second repair address information to the storage latch circuit and disables storing the second address information into the non-volatile storage element.

Abstract: The present invention discloses a resistor circuit with temperature coefficient compensation, which comprises a first series resistor composed of a first resistor and a second resistor interconnected in series, and a second parallel resistor composed of a third resistor and a fourth resistor interconnected in series, with the first series resistor and the second parallel resistor interconnected in series, wherein the first resistor and the second resistor respectively have a positive and negative temperature coefficient and make the positive and negative temperature coefficients of the first series resistor offset each other, and the third resistor and the fourth resistor respectively have a positive and negative temperature coefficient and make the positive and negative temperature coefficients of the second parallel resistor offset each other.

Abstract: Techniques for providing non-volatile antifuse memory elements and other antifuse links are disclosed herein. In some embodiments, the antifuse memory elements are configured with non-planar topology such as FinFET topology. In some such embodiments, the fin topology can be manipulated and used to effectively promote lower breakdown voltage transistors, by creating enhanced-emission sites which are suitable for use in lower voltage non-volatile antifuse memory elements. In one example embodiment, a semiconductor antifuse device is provided that includes a non-planar diffusion area having a fin configured with a tapered portion, a dielectric isolation layer on the fin including the tapered portion, and a gate material on the dielectric isolation layer. The tapered portion of the fin may be formed, for instance, by oxidation, etching, and/or ablation, and in some cases includes a base region and a thinned region, and the thinned region is at least 50% thinner than the base region.

Abstract: A sense circuit and method for use in measuring the blown or unblown state of fusible links (fuses), particularly in integrated circuits. Embodiments include at least one additional reference resistance to allow for a greater margin of error in determining the actual state of a fuse. By having two or more reference resistances that can be independently selectable, additional combinations of reference resistance values are available to compare against the resistance of a fuse being tested.

Abstract: A voltage regulator comprises a ground node, a pick-off node, a regulator branch, a load branch, and a current mirror the regulator branch and the load branch are connected in parallel between the pick-off node and the ground node; the load branch comprises one or more resistive connecting lines that are connectable in series with the load to generate a load current through the load branch; the regulator branch comprises a bias node, a resistive element, and a tap node; the bias node is arranged to provide a regulated bias voltage; the resistive element is connected between the bias node and the pick-off node; and the tap node is connected between the bias node and the resistive element. The current mirror is connected to the tap node and arranged to draw a mirror current from the tap node; the mirror current having a component that is proportional to the load current.

Abstract: A method for controlling the breakdown of an antifuse memory cell formed on a semiconductor substrate, including the steps of: applying a programming voltage; detecting a breakdown time; and interrupting the application of the programming voltage at a time following the breakdown time by a post-breakdown time.

Abstract: Activity data is analyzed or evaluated to detect behavioral patterns and anomalies. When a particular pattern or anomaly is detected, a system may send a notification or perform a particular task. This activity data may be collected in an information management system, which may be policy based. Notification may be by way e-mail, report, pop-up message, or system message. Some tasks to perform upon detection may include implementing a policy in the information management system, disallowing a user from connecting to the system, and restricting a user from being allowed to perform certain actions. To detect a pattern, activity data may be compared to a previously defined or generated activity profile.

Abstract: A circuit includes a fuse cell, a sense circuit and an output control circuit. The fuse cell includes an electrical fuse. The sense circuit is electrically coupled to the fuse cell and configured for generating a sense signal indicative of a programmed condition of the electrical fuse, at an output of the sense circuit. The output control circuit is electrically coupled to the output of the sense circuit, and the output control circuit is configured for latching the sense signal indicative of the electrical fuse having been programmed, during a read operation of the fuse cell.

Abstract: A cell bias control circuit maximizes the performance of devices in the read/write path of memory cells (magnetic tunnel junction device+transistor) without exceeding leakage current or reliability limits by automatically adjusting multiple control inputs of the read/write path at the memory array according to predefined profiles over supply voltage, temperature, and process corner variations by applying any specific reference parameter profiles to the memory array.

Abstract: Described is an apparatus comprising: a voltage level detector to monitor a first power supply node; and a voltage level protector, coupled to the voltage level detector, to protect the voltage level detector from receiving a power supply on the first power supply node above a pre-defined threshold voltage. Described is also a voltage level protector to protect a first power supply node from receiving a power supply above a pre-defined threshold voltage, the voltage level protector comprising: a first p-type device coupled to a second power supply node, the second power supply node to receive a power supply higher than the power supply on the first power supply node; and a second p-type device coupled in series to the first p-type device, the second p-type further coupled to the first power supply node, which is for coupling to a voltage level detector.

Abstract: A method of decoding, an encoded signal includes steps of receiving the encoded signal, creating a decoding signal by delaying the encoded signal by a predetermined amount of time ?, sampling the encoded signal using the decoding signal, and determining a value of each of a plurality of decoded bits represented by the encoded signal based on the sampling. Also, a method of operating a shift register wherein the shift register has an initialization state wherein a first binary symbol is stored in a first position and a second binary symbol different than the first binary symbol is stored in each of one or more intermediate positions and a last position. The method includes determining that the shift register is full responsive to detecting that the first binary symbol has been stored in either one of the intermediate positions or the last position.

Abstract: An integrated circuit device includes a pad adapted to receive a signal from an external driver. A state register is programmed with a state that indicates a voltage level to set for the pad during initialization of circuitry on the integrated circuit device responsive to the state for the pad. The voltage level may correspond to a logic low level or a logic high level. A voltage holding circuit is coupled to the pad and the state register, and is configured to force the pad to the voltage level in response to an event that causes the initialization.

Abstract: In a high-side region, a first n-diffusion region, in which a PMOS constituting a gate drive circuit is formed, and a second n-diffusion region, in which a p-diffusion region is formed, are provided on a surface layer of a p?? substrate. An NMOS constituting a gate drive circuit is formed in the p-diffusion region. A p-type isolation diffusion region at ground potential is provided between the first n-diffusion region and the second n-diffusion region, and the first re-diffusion region and the second n-diffusion region are electrically isolated. The first n-diffusion region is connected to a VB terminal at a power source potential. The second n-diffusion region is connected to a terminal at a reference or floating potential. The p-diffusion region is connected to a VS terminal at a reference potential. Accordingly, it is possible to suppress parasitic operation due to a surge, without using external components, and without element breakdown.

Abstract: The semiconductor device includes a flag signal generator, a reference voltage generator and a first buffer. The flag signal generator generates a flag signal in response to an internal command and an information code. The reference voltage generator receives a set code in response to the flag signal, and generates a reference voltage having a voltage level regulated according to the set code. The first buffer buffers the external signal in response to the reference voltage to generate an internal signal, and generates a calibration code in response to the flag signal.

Abstract: A low cost, small scale semiconductor device including a trimming circuit having a fuse resistor is disclosed. By a trimming circuit being configured of a MOSFET, a protection circuit, and a fuse resistor, it is possible to carry out a change from an open circuit state to a short circuit state by fusing the fuse resistor. Also, by the protection circuit and fuse resistor configuring the trimming circuit being formed in a two layer structure, it is possible to reduce the size of the trimming circuit, and thus it is possible to provide a low cost, small scale semiconductor device having a trimming circuit that occupies a small area.

Abstract: A stressed substrate for transient electronic systems (i.e., electronic systems that visually disappear when triggered to do so) that includes one or more stress-engineered layers that store potential energy in the form of a significant internal stress. An associated trigger mechanism is also provided that, when triggered, causes an initial fracture in the stressed substrate, whereby the fracture energy nearly instantaneously travels throughout the stressed substrate, causing the stressed substrate to shatter into multiple small (e.g., micron-sized) pieces that are difficult to detect. The internal stress is incorporated into the stressed substrate through strategies similar to glass tempering (for example through heat or chemical treatment), or by depositing thin-film layers with large amounts of stress. Patterned fracture features are optionally provided to control the final fractured particle size. Electronic systems built on the substrate are entirely destroyed and dispersed during the transience event.