Fusible Link Or Intentional Destruct Circuit Patents (Class 327/525)
  • Patent number: 10352728
    Abstract: An angle sensor includes a detection signal generation unit for generating detection signals, and an angle detection unit for generating a detected angle value on the basis of the detection signals. The angle detection unit includes a signal conversion unit for performing a conversion operation, and an angle operation unit for performing an angle operation. The conversion operation is to convert the detection signals into first and second operation signals. The angle operation is to calculate the detected angle value using the first and second operation signals. The conversion operation includes an operation using a correction-term-containing function which contains a correction term for reducing a first error or a second error occurring in the detected angle value. When the angle to be detected varies with a predetermined period, the first error varies with the predetermined period, whereas the second error varies with a period ½ the predetermined period.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: July 16, 2019
    Assignee: TDK CORPORATION
    Inventors: Kazuya Watanabe, Hiraku Hirabayashi
  • Patent number: 10332834
    Abstract: Semiconductor fuses with nanowire fuse links and fabrication methods thereof are presented. The methods include, for instance: fabricating a semiconductor fuse, the semiconductor fuse including at least one nanowire fuse link, and the fabricating including: forming at least one nanowire, the at least one nanowire including a semiconductor material; and reacting the at least one nanowire with a metal to form the at least one nanowire fuse link of the semiconductor fuse, the at least one nanowire fuse link including a semiconductor-metal alloy. In another aspect, a structure is presented. The structure includes: a semiconductor fuse, the semiconductor fuse including: at least one nanowire fuse link, the at least one nanowire fuse link including a semiconductor-metal alloy.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: June 25, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Chun Yu Wong, Jagar Singh, Ashish Baraskar, Min-hwa Chi
  • Patent number: 10296031
    Abstract: A reference voltage generator may include a voltage division unit configured to receive an external voltage, and divide the external voltage into a plurality of divided voltages. The reference voltage generator may include reference voltage output units configured to trim the divided voltages received from the voltage division unit according to a division control signal, and output supply reference voltages. The reference voltage output units may be symmetrically arranged at both sides of the voltage division unit.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: May 21, 2019
    Assignee: SK hynix Inc.
    Inventor: Young Koung Kim
  • Patent number: 10255982
    Abstract: Apparatus and methods for protection against inadvertent programming of fuse cells are provided herein. In certain configurations, a fuse system includes a fuse programming transistor, a cascode transistor, and a fuse cell electrically connected in series between a first pad and a second pad. The fuse system further includes a bias generator that controls an amount of current provided to the fuse cell based on biasing a gate of the fuse programming transistor and a gate of the cascode transistor. The fuse system further includes a fuse protection capacitor electrically connected between the first pad and the gate of the cascode transistor to prevent inadvertent programming of the fuse cell in response to an increase in voltage of the first pad relative to the second pad.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: April 9, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventors: Bo Zhou, Guillaume Alexandre Blin
  • Patent number: 10062536
    Abstract: A fusible link unit includes: a fuse element including a plurality of fusible portions arrayed in a predetermined array direction; a housing having a window portion penetrating the housing in an intersecting direction to intersect the array direction; and fusible portion covers attached to the housing. The housing holds the fuse element to locate the fusible portions inside the window portion. The fusible portion covers includes a first cover that is transparent and has a plate shape extending in the array direction and covering one opening of the window portion and a second cover that is non-transparent and having a plate shape extending in the array direction and covering the other opening of the window portion. A length of the first cover in the array direction is different from a length of the second cover in the array direction.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: August 28, 2018
    Assignee: YAZAKI CORPORATION
    Inventor: Makoto Yamaguchi
  • Patent number: 10037141
    Abstract: A memory device may include an application chip set including a plurality of applications. The memory device may include a chip decoder configured to select one application among the applications in response to input data and a test fuse signal, and output function data so that a function to be performed by the selected application is selected.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: July 31, 2018
    Assignee: SK hynix Inc.
    Inventor: Jae Bum Ko
  • Patent number: 10032521
    Abstract: A method and system are used to generate random values for Physical Unclonable Function (PUF) for use in cryptographic applications. A PUF value generation apparatus comprises two dielectric breakdown based anti-fuses and at least one current limiting circuit connected between anti-fuses and power rails. Two anti-fuses are connected in parallel for value generation in programming by applying high voltage to both anti-fuses at the same time. Time for dielectric breakdown under high voltage stress is of random nature and therefore unique for each anti-fuse cell. Therefore the random time to breakdown causes one cell to break before another, causing high breakdown current through the broken cell. Once high breakdown current through one broken or programmed cell is established, a voltage drop across a current limiting circuit leads to decreased voltage across both cells, thereby slowing the time dependent breakdown process in the second cell and preventing it from breakage under programming conditions.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: July 24, 2018
    Assignee: Synopsys, Inc.
    Inventors: Grigori Grigoriev, Roman Gavrilov, Oleg Ivanov
  • Patent number: 9971376
    Abstract: Voltage reference circuits configured to generate a voltage reference with a programmable temperature slope are disclosed. By combining and programming a PTAT (Proportional To Absolute Temperature) voltage generation circuit and a CTAT (Complementary To Absolute Temperature) voltage generation circuit, desired temperature slope for the voltage reference is obtained. To adjust both temperature slope and offset of the voltage reference, the voltage reference circuits include a bandgap reference circuit. The bandgap reference circuit is used to create a temperature independent current, which is coupled to a programmable string of resistors and programmable string of MOSFETs to produce a desired temperature slope for the voltage reference. The desired offset of the voltage reference is obtained by the temperature-independent current into another string of programmable resistors. A circuit architecture and method to control the temperature slope and offset of the voltage reference independently is disclosed.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: May 15, 2018
    Assignee: Kilopass Technology, Inc.
    Inventor: Sang-soo Lee
  • Patent number: 9971372
    Abstract: A voltage regulator provides an output voltage, the voltage regulator configured to receive one of a plurality of different regulator reference voltages and a controller configured to provide a selection signal, the selection signal being used to control which of the regulator reference voltages the voltage regulator receives.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: May 15, 2018
    Assignee: STMicroelectronics International N.V.
    Inventor: Rajesh Narwal
  • Patent number: 9954630
    Abstract: A multiplexer (MUX) configured to receive a plurality of input data streams and output an output data stream via an output data line based at least in part upon a control signal, includes: a first circuit portion corresponding to a first data stream of the plurality of input data streams, comprising: a first internal node; a first control switch operable to connect the output data line to the first internal node of the first circuit portion based at least in part upon the control signal, wherein the first internal node has a value corresponding to the first data stream when the output data line is connected to the first internal node; and a first reset switch operable to connect the first internal node to a common mode voltage rail based at least in part upon the control signal to remove or reduce residual charge at the first internal node.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: April 24, 2018
    Assignee: XILINX, INC.
    Inventor: Karthik C. Venna
  • Patent number: 9946717
    Abstract: Activity data is analyzed or evaluated to detect behavioral patterns and anomalies. When a particular pattern or anomaly is detected, a system may send a notification or perform a particular task. This activity data may be collected in an information management system, which may be policy based. Notification may be by way e-mail, report, pop-up message, or system message. Some tasks to perform upon detection may include implementing a policy in the information management system, disallowing a user from connecting to the system, and restricting a user from being allowed to perform certain actions. To detect a pattern, activity data may be compared to a previously defined or generated activity profile.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: April 17, 2018
    Assignee: NextLabs, Inc.
    Inventor: Keng Lim
  • Patent number: 9905265
    Abstract: The invention relates to a destruction system for destroying a functional layer, which may receive data or perform other functions, such as optical functions, for example, and a related method. The reactants may be interspersed within the functional layer or may be provided in a separate layer adjacent to the functional layer. The reactants are structured to be ignited to destroy the functionality of the functional layer and the data. Ignition may be obtained through a flame or by suitable electrical current in certain embodiments of the invention.
    Type: Grant
    Filed: December 3, 2007
    Date of Patent: February 27, 2018
    Inventor: Jonathan Mohler
  • Patent number: 9900754
    Abstract: A wireless Internet gateway bridges wireless devices to the Internet, e.g., via a short message service center (SMSC). The gateway provides a portal to SMPP, HTTP, TNPP, or other protocol messages using Java Remote Method Invocation (RMI) techniques. Application servers insert RMI objects containing messages in a message queue handler of the gateway. The RMI objects are queued and passed either directly to a destination delivery handler (e.g., SMPP, SMTP, HTTP or TNPP protocol handler), or passed through a generic destination interface. An SMTP handler provides direct communication of SMTP protocol messages (i.e., email) to the message queue. An SMPP link proxy module provides direct access between a local application server and the destination delivery handler. The messages are packaged into relevant messages of the particular destination protocol (e.g., SMPP), and transmitted to the relevant network element (e.g., to an SMSC).
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: February 20, 2018
    Assignee: Telecommunication Systems, Inc.
    Inventor: Richard A. Smith
  • Patent number: 9895879
    Abstract: A semiconductor device includes, an anti-fuse element, a transistor connected via the anti-fuse element to a power source terminal which may apply a voltage to the anti-fuse element, an ESD protection element connected to the power source terminal via a node, and a first resistive element disposed in an electric path between the node and the anti-fuse element, wherein resistance of the first resistive element increases with an increase of a voltage applied to the first resistive element.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: February 20, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazunari Fujii, Toshio Negishi
  • Patent number: 9865347
    Abstract: A memory driving circuit is disclosed herein. The memory driving circuit includes a programmable current source, a reference voltage generation unit and a voltage comparator unit, The programmable current source generates a second current according to a first current. The second current flows into a memory cell, and produces a device voltage at the input of the memory cell. The reference voltage generation unit generates a crystal voltage. The voltage comparator unit compares the device voltage with the crystal voltage and sends out a control signal to control the programmable current source. The first current and the second current are adjusted by the control signal so that the shape of the current pulse of SET operation to the memory cell is well controlled.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: January 9, 2018
    Assignees: Jiangsu Advanced Memory Technology Co., Ltd., ALTO MEMORY TECHNOLOGY CORPORATION
    Inventors: Fan-Yi Jien, Jia-Hwang Chang, Sheng-Tsai Huang, Jui-Jen Wu
  • Patent number: 9805849
    Abstract: The present invention discloses a resistor circuit with temperature coefficient compensation, which comprises a first series resistor composed of a first resistor and a second resistor interconnected in series, and a second parallel resistor composed of a third resistor and a fourth resistor interconnected in series, with the first series resistor and the second parallel resistor interconnected in series, wherein the first resistor and the second resistor respectively have a positive and negative temperature coefficient and make the positive and negative temperature coefficients of the first series resistor offset each other, and the third resistor and the fourth resistor respectively have a positive and negative temperature coefficient and make the positive and negative temperature coefficients of the second parallel resistor offset each other.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: October 31, 2017
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventor: Zhiyong Yuan
  • Patent number: 9805828
    Abstract: Apparatuses for memory repair for a memory device are described. An example apparatus includes: a non-volatile storage element that stores information; a storage latch circuit coupled to the non-volatile storage element and stores latch information; and a control circuit that, in a first repair mode, receives first repair address information, provides the first repair address information to the non-volatile storage element, and further transmits the first repair address information from the non-volatile storage element to the storage latch circuit. The control circuit, in a second repair mode, receives second repair address information and provides the second repair address information to the storage latch circuit and disables storing the second address information into the non-volatile storage element.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: October 31, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Hideyuki Yoko
  • Patent number: 9748252
    Abstract: Techniques for providing non-volatile antifuse memory elements and other antifuse links are disclosed herein. In some embodiments, the antifuse memory elements are configured with non-planar topology such as FinFET topology. In some such embodiments, the fin topology can be manipulated and used to effectively promote lower breakdown voltage transistors, by creating enhanced-emission sites which are suitable for use in lower voltage non-volatile antifuse memory elements. In one example embodiment, a semiconductor antifuse device is provided that includes a non-planar diffusion area having a fin configured with a tapered portion, a dielectric isolation layer on the fin including the tapered portion, and a gate material on the dielectric isolation layer. The tapered portion of the fin may be formed, for instance, by oxidation, etching, and/or ablation, and in some cases includes a base region and a thinned region, and the thinned region is at least 50% thinner than the base region.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: August 29, 2017
    Assignee: INTEL CORPORATION
    Inventors: Walid M. Hafez, Chia-Hong Jan, Curtis Tsai, Joodong Park, Jeng-Ya D. Yeh
  • Patent number: 9709620
    Abstract: A sense circuit and method for use in measuring the blown or unblown state of fusible links (fuses), particularly in integrated circuits. Embodiments include at least one additional reference resistance to allow for a greater margin of error in determining the actual state of a fuse. By having two or more reference resistances that can be independently selectable, additional combinations of reference resistance values are available to compare against the resistance of a fuse being tested.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: July 18, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Robert Mark Englekirk
  • Patent number: 9625934
    Abstract: A voltage regulator comprises a ground node, a pick-off node, a regulator branch, a load branch, and a current mirror the regulator branch and the load branch are connected in parallel between the pick-off node and the ground node; the load branch comprises one or more resistive connecting lines that are connectable in series with the load to generate a load current through the load branch; the regulator branch comprises a bias node, a resistive element, and a tap node; the bias node is arranged to provide a regulated bias voltage; the resistive element is connected between the bias node and the pick-off node; and the tap node is connected between the bias node and the resistive element. The current mirror is connected to the tap node and arranged to draw a mirror current from the tap node; the mirror current having a component that is proportional to the load current.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: April 18, 2017
    Assignee: NXP USA, Inc.
    Inventors: Sergey Sergeevich Ryabchenkov, Ivan Victorovich Kochkin
  • Patent number: 9564242
    Abstract: A method for controlling the breakdown of an antifuse memory cell formed on a semiconductor substrate, including the steps of: applying a programming voltage; detecting a breakdown time; and interrupting the application of the programming voltage at a time following the breakdown time by a post-breakdown time.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: February 7, 2017
    Assignee: STMicroelectronics SA
    Inventors: Philippe Candelier, Joel Damiens, Elise Le Roux
  • Patent number: 9558841
    Abstract: A circuit includes a fuse cell, a sense circuit and an output control circuit. The fuse cell includes an electrical fuse. The sense circuit is electrically coupled to the fuse cell and configured for generating a sense signal indicative of a programmed condition of the electrical fuse, at an output of the sense circuit. The output control circuit is electrically coupled to the output of the sense circuit, and the output control circuit is configured for latching the sense signal indicative of the electrical fuse having been programmed, during a read operation of the fuse cell.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: January 31, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sung-Chieh Lin, Kuo-Yuan Hsu, Wei-Li Liao, Chen-Ming Hung, Yun-Han Chen, Shao-Cheng Wang
  • Patent number: 9558193
    Abstract: Activity data is analyzed or evaluated to detect behavioral patterns and anomalies. When a particular pattern or anomaly is detected, a system may send a notification or perform a particular task. This activity data may be collected in an information management system, which may be policy based. Notification may be by way e-mail, report, pop-up message, or system message. Some tasks to perform upon detection may include implementing a policy in the information management system, disallowing a user from connecting to the system, and restricting a user from being allowed to perform certain actions. To detect a pattern, activity data may be compared to a previously defined or generated activity profile.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: January 31, 2017
    Assignee: NextLabs, Inc.
    Inventor: Keng Lim
  • Patent number: 9541583
    Abstract: Described is an apparatus comprising: a voltage level detector to monitor a first power supply node; and a voltage level protector, coupled to the voltage level detector, to protect the voltage level detector from receiving a power supply on the first power supply node above a pre-defined threshold voltage. Described is also a voltage level protector to protect a first power supply node from receiving a power supply above a pre-defined threshold voltage, the voltage level protector comprising: a first p-type device coupled to a second power supply node, the second power supply node to receive a power supply higher than the power supply on the first power supply node; and a second p-type device coupled in series to the first p-type device, the second p-type further coupled to the first power supply node, which is for coupling to a voltage level detector.
    Type: Grant
    Filed: May 8, 2013
    Date of Patent: January 10, 2017
    Assignee: Intel Corporation
    Inventors: Harmander Singh, Mohammad Mehedi Hasan, Abhiman Pratap Kotwal, Gianfranco Gerosa, Mohammed Hasan Taufique
  • Patent number: 9542989
    Abstract: A cell bias control circuit maximizes the performance of devices in the read/write path of memory cells (magnetic tunnel junction device+transistor) without exceeding leakage current or reliability limits by automatically adjusting multiple control inputs of the read/write path at the memory array according to predefined profiles over supply voltage, temperature, and process corner variations by applying any specific reference parameter profiles to the memory array.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: January 10, 2017
    Assignee: Everspin Technologies, Inc.
    Inventors: Dietmar Gogl, Syed M. Alam, Thomas Andre
  • Patent number: 9490028
    Abstract: A method of decoding, an encoded signal includes steps of receiving the encoded signal, creating a decoding signal by delaying the encoded signal by a predetermined amount of time ?, sampling the encoded signal using the decoding signal, and determining a value of each of a plurality of decoded bits represented by the encoded signal based on the sampling. Also, a method of operating a shift register wherein the shift register has an initialization state wherein a first binary symbol is stored in a first position and a second binary symbol different than the first binary symbol is stored in each of one or more intermediate positions and a last position. The method includes determining that the shift register is full responsive to detecting that the first binary symbol has been stored in either one of the intermediate positions or the last position.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: November 8, 2016
    Assignee: University of Pittsburgh—Of the Commonwealth System of Higher Education
    Inventors: Marlin H. Mickle, Vyasa Sai, Ajay Ogirala
  • Patent number: 9417640
    Abstract: An integrated circuit device includes a pad adapted to receive a signal from an external driver. A state register is programmed with a state that indicates a voltage level to set for the pad during initialization of circuitry on the integrated circuit device responsive to the state for the pad. The voltage level may correspond to a logic low level or a logic high level. A voltage holding circuit is coupled to the pad and the state register, and is configured to force the pad to the voltage level in response to an event that causes the initialization.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: August 16, 2016
    Assignee: Macronix International Co., Ltd.
    Inventors: Kuen-Long Chang, Ken-Hui Chen, Chin-Hung Chang, Chao-Hsin Lin
  • Patent number: 9412732
    Abstract: In a high-side region, a first n-diffusion region, in which a PMOS constituting a gate drive circuit is formed, and a second n-diffusion region, in which a p-diffusion region is formed, are provided on a surface layer of a p?? substrate. An NMOS constituting a gate drive circuit is formed in the p-diffusion region. A p-type isolation diffusion region at ground potential is provided between the first n-diffusion region and the second n-diffusion region, and the first re-diffusion region and the second n-diffusion region are electrically isolated. The first n-diffusion region is connected to a VB terminal at a power source potential. The second n-diffusion region is connected to a terminal at a reference or floating potential. The p-diffusion region is connected to a VS terminal at a reference potential. Accordingly, it is possible to suppress parasitic operation due to a surge, without using external components, and without element breakdown.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: August 9, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Masaharu Yamaji, Hiroshi Kanno
  • Patent number: 9412468
    Abstract: The semiconductor device includes a flag signal generator, a reference voltage generator and a first buffer. The flag signal generator generates a flag signal in response to an internal command and an information code. The reference voltage generator receives a set code in response to the flag signal, and generates a reference voltage having a voltage level regulated according to the set code. The first buffer buffers the external signal in response to the reference voltage to generate an internal signal, and generates a calibration code in response to the flag signal.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: August 9, 2016
    Assignee: SK hynix Inc.
    Inventor: Bok Rim Ko
  • Patent number: 9318433
    Abstract: A low cost, small scale semiconductor device including a trimming circuit having a fuse resistor is disclosed. By a trimming circuit being configured of a MOSFET, a protection circuit, and a fuse resistor, it is possible to carry out a change from an open circuit state to a short circuit state by fusing the fuse resistor. Also, by the protection circuit and fuse resistor configuring the trimming circuit being formed in a two layer structure, it is possible to reduce the size of the trimming circuit, and thus it is possible to provide a low cost, small scale semiconductor device having a trimming circuit that occupies a small area.
    Type: Grant
    Filed: April 10, 2014
    Date of Patent: April 19, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yoshiaki Toyoda
  • Patent number: 9293219
    Abstract: There is provided a non-volatile memory circuit including: plural storage element sections each including a zener zap device and a switch section that connects an anode of the zener zap device to an output terminal during data reading; and wherein cathodes of respective zener zap devices of the plural storage element sections are commonly connected so as to be connected to a power supply employed in the writing or to a power supply employed in the reading, wherein the output terminals of the plural storage element sections are commonly connected to an input terminal of a detector, an anode of each of the storage element sections being connected to a ground voltage during data writing, and wherein the switch section is switched ON during data reading so as to connect the anode of the storage element section through the output terminal to the input terminal of the detector.
    Type: Grant
    Filed: April 10, 2013
    Date of Patent: March 22, 2016
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Masayuki Otsuka
  • Patent number: 9287009
    Abstract: A repair circuit includes first and second fuse circuits, a determination circuit and an output circuit. The first fuse circuit includes a first fuse and is configured to generate a first master signal indicating whether the first fuse has been programmed. The second fuse circuit includes second fuses and is configured to generate a first address indicating whether each of the second fuses has been programmed. The determination circuit is configured to generate a detection signal based on the first master signal and the first address. The detection signal indicates whether a negative program operation has been performed on the second fuse circuit. The output circuit is configured to generate a second master signal based on the first master signal and the detection signal and generate a repair address corresponding to a defective input address based on the first address and the detection signal.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: March 15, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyu-Chang Kang, Gil-Su Kim, Je-Min Ryu, Yun-Young Lee, Kyo-Min Sohn
  • Patent number: 9117709
    Abstract: Improvement of key electrical specifications of vertical semiconductor devices, usually found in the class of devices known as discrete semiconductors, has a direct impact on the performance achievement and power efficiency of the systems in which these devices are used. Imprecise vertical device specifications cause system builders to either screen incoming devices for their required specification targets or to design their system with lower performance or lower efficiency than desired. Disclosed is an architecture and method for achieving a desired target specification for a vertical semiconductor device. Precise trimming of threshold voltage improves targeting of both on-resistance and switching time. Precise trimming of gate resistance also improves targeting of switching time. Precise trimming of a device's effective width improves targeting of both on-resistance and current-carrying capability.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: August 25, 2015
    Assignee: D3 Semiconductor LLC
    Inventor: Thomas E. Harrington, III
  • Patent number: 9062952
    Abstract: A product includes: a part including at least one component characterized as an energetic material, where the at least one component is at least partially characterized by physical characteristics of being deposited by an electrophoretic deposition process. A method includes: providing a plurality of particles of an energetic material suspended in a dispersion liquid to an EPD chamber or configuration; applying a voltage difference across a first pair of electrodes to generate a first electric field in the EPD chamber; and depositing at least some of the particles of the energetic material on at least one surface of a substrate, the substrate being one of the electrodes or being coupled to one of the electrodes.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: June 23, 2015
    Assignee: Lawrence Livermore National Security, LLC
    Inventors: Kyle T. Sullivan, Alexander E. Gash, Joshua D. Kuntz, Marcus A. Worsley
  • Patent number: 9059172
    Abstract: A fuse circuit includes a plurality of fuses, a plurality of switches and a plurality of trimming components. The fuses are coupled in parallel to a first node and a second node. The first node is coupled to an operating voltage. The switches are coupled to the second node. The trimming components are respectively disposed between the switches and a ground voltage, and coupled to the second node via the switches, respectively. When one of the trimming components is activated, the activated trimming component allows a plurality of branch currents to be generated between the first node and the second node. The branch currents respectively flow through the fuses so that one of the fuses is blown out by the branch current flowing through the one of the fuses.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: June 16, 2015
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Tuan-Kai Su, Yao-Feng Huang, Po-An Chen
  • Publication number: 20150145590
    Abstract: An integrated circuit system having an integrated circuit (IC) component which is able to have its functionality destroyed upon receiving a command signal. The system may involve a substrate with the IC component being supported on the substrate. A module may be disposed in proximity to the IC component. The module may have a cavity and a dissolving compound in a solid form disposed in the cavity. A heater component may be configured to heat the dissolving compound to a point of sublimation where the dissolving compound changes from a solid to a gaseous dissolving compound. A triggering mechanism may be used for initiating a dissolution process whereby the gaseous dissolving compound is allowed to attack the IC component and destroy a functionality of the IC component.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 28, 2015
    Inventors: Kedar G. SHAH, Satinderpall S. PANNU
  • Patent number: 9042551
    Abstract: A semiconductor structure including a device configured to receive an input data-word. The device including a logic structure configured to generate an encrypted data-word by encrypting the input data-word through an encrypting operation. The device further including an eFuse storage device configured to store the encrypted data-word as eFuse data by blowing fuses in accordance with the encrypted data-word.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: May 26, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John A. Fifield, Gerald P. Pomichter, Jr.
  • Patent number: 9024394
    Abstract: Systems and methods of the invention generally relate to altering the functionality of a non-transient electronic device. A container holding an agent is located proximal to a non-transient electronic device capable of performing at least one function. The agent is capable of rendering the device incapable of performing the at least one function. The container is configured to controllably release the agent to the electronic device in a variety of passive and active eventualities.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: May 5, 2015
    Assignee: Transient Electronics, Inc.
    Inventors: Christopher Poirier, Anthony Stewart Campbell, Carmichael S. Roberts, John A. Rogers, Winston E. Henderson
  • Publication number: 20150116028
    Abstract: A fuse circuit includes a plurality of fuses, a plurality of switches and a plurality of trimming components. The fuses are coupled in parallel to a first node and a second node. The first node is coupled to an operating voltage. The switches are coupled to the second node. The trimming components are respectively disposed between the switches and a ground voltage, and coupled to the second node via the switches, respectively. When one of the trimming components is activated, the activated trimming component allows a plurality of branch currents to be generated between the first node and the second node. The branch currents respectively flow through the fuses so that one of the fuses is blown out by the branch current flowing through the one of the fuses.
    Type: Application
    Filed: May 21, 2014
    Publication date: April 30, 2015
    Inventors: Tuan-Kai Su, Yao-Feng Huang, Po-An Chen
  • Publication number: 20150102852
    Abstract: A stressed substrate for transient electronic systems (i.e., electronic systems that visually disappear when triggered to do so) that includes one or more stress-engineered layers that store potential energy in the form of a significant internal stress. An associated trigger mechanism is also provided that, when triggered, causes an initial fracture in the stressed substrate, whereby the fracture energy nearly instantaneously travels throughout the stressed substrate, causing the stressed substrate to shatter into multiple small (e.g., micron-sized) pieces that are difficult to detect. The internal stress is incorporated into the stressed substrate through strategies similar to glass tempering (for example through heat or chemical treatment), or by depositing thin-film layers with large amounts of stress. Patterned fracture features are optionally provided to control the final fractured particle size. Electronic systems built on the substrate are entirely destroyed and dispersed during the transience event.
    Type: Application
    Filed: October 11, 2013
    Publication date: April 16, 2015
    Applicant: Palo Alto Research Center Incorporated
    Inventors: Scott J. H. Limb, Gregory L. Whiting, Sean R. Garner, JengPing Lu, Dirk DeBruyker
  • Publication number: 20150049546
    Abstract: A plurality of fuse cells includes a first fuse cell and a second fuse cell. Each of the first and second fuse cells includes a first anti-fuse and a second anti-fuse. A method of programming the fuse cells includes rupturing the first anti-fuse of the first fuse cell based on first data loaded to a program control circuit. The method includes rupturing the second anti-fuse of the first fuse cell before loading second data to the program control circuit. The second data is for rupturing the first anti-fuse of the second fuse cell or the second anti-fuse of the second fuse cell.
    Type: Application
    Filed: June 17, 2014
    Publication date: February 19, 2015
    Inventor: Ahn Choi
  • Patent number: 8941436
    Abstract: The invention pertains to a logic circuit device comprising at least one digital input furnished with a fuse (FUS) being, in the closed state, suitable for applying an electrical input voltage of the logic circuit corresponding to a first logic state from among the logic states 0 and 1, and, in the definitive open state, suitable for applying an electrical input voltage of the logic circuit corresponding to the second logic state from among the logic states 0 and 1, said fuse (FUS) being suitable for being placed definitively in the second logic state by injection of a current greater than a threshold current (CS).
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: January 27, 2015
    Assignee: THALES
    Inventor: Vincent Rochas
  • Publication number: 20150008976
    Abstract: An anti-fuse includes a single transistor formed over an active region of a semiconductor substrate and entering a fuse cut state by a threshold voltage being varied upon receiving a voltage applied thereto. The single transistor includes a device isolation film formed in the semiconductor substrate to define the active region, and a liner trap film formed between the device isolation film and the active region in such a manner that electrons are trapped in the liner trap film upon receiving the voltage.
    Type: Application
    Filed: February 27, 2014
    Publication date: January 8, 2015
    Applicant: SK HYNIX INC.
    Inventor: Sung Su KIM
  • Patent number: 8928387
    Abstract: A memory-like structure composed of variable resistor elements for use in tuning respective branches and leaves of a clock distribution structure, which may be used to compensate for chip-by-chip and/or combinatorial logic path-by-path delay variations, which may be due, for example, to physical variations in deep submicron devices and interconnections, is presented. A single system clocked scan flip-flop with the capability to perform delay test measurements is also presented. Methods for measuring combinatorial logic path delays to determine the maximum clock frequency and delays to program the variable resistors, as well as methods for calibrating and measuring the programmed variable resistors, are also presented.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: January 6, 2015
    Inventor: Laurence H. Cooke
  • Publication number: 20150002213
    Abstract: Nanoscale efuses, antifuses, and planar coil inductors are disclosed. A copper damascene process can be used to make all of these circuit elements. A low-temperature copper etch process can be used to make the efuses and efuse-like inductors. The circuit elements can be designed and constructed in a modular fashion by linking a matrix of metal columns in different configurations and sizes. The number of metal columns, or the size of a dielectric mesh included in the circuit element, determines its electrical characteristics. Alternatively, the efuses and inductors can be formed from interstitial metal that is either deposited into a matrix of dielectric columns, or left behind after etching columnar openings in a block of metal. Arrays of metal columns also serve a second function as features that can improve polish uniformity in place of conventional dummy structures. Use of such modular arrays provides flexibility to integrated circuit designers.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Edem Wornyo
  • Publication number: 20140368261
    Abstract: Semiconductor systems are provided. The semiconductor system includes a controller and a semiconductor device. The controller generates a power voltage signal. The semiconductor device generates a power-up signal in response to the power voltage signal, generates a first selection pulse, a second selection pulse and an initialization pulse signal, generates a first fuse signal for controlling an internal operation according to a cut state of a first fuse, and generates a second fuse signal for controlling the internal operation according to a cut state of a second fuse.
    Type: Application
    Filed: January 16, 2014
    Publication date: December 18, 2014
    Applicant: SK hynix Inc.
    Inventors: Sun Young HWANG, Jun Hyun CHUN
  • Patent number: 8912841
    Abstract: Semiconductor systems are provided. The semiconductor system includes a controller and a semiconductor device. The controller generates a power voltage signal. The semiconductor device generates a power-up signal in response to the power voltage signal, generates a first selection pulse, a second selection pulse and an initialization pulse signal, generates a first fuse signal for controlling an internal operation according to a cut state of a first fuse, and generates a second fuse signal for controlling the internal operation according to a cut state of a second fuse.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: December 16, 2014
    Assignee: SK Hynix Inc.
    Inventors: Sun Young Hwang, Jun Hyun Chun
  • Patent number: 8907697
    Abstract: Embodiments related to electrically characterizing a semiconductor device are provided. In one example, a method for characterizing a pin of a semiconductor device is provided, the method comprising providing a test pattern to the semiconductor device. Further, the method includes adjusting a selected electrical state of a pin of the semiconductor device and measuring a value for a dependent electrical state of the pin responsive to the selected electrical state. The example method also includes generating an electrical characterization for the pin by correlating the dependent electrical state with the selected electrical state and outputting the electrical characterization for display.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: December 9, 2014
    Assignee: Teseda Corporation
    Inventors: Jack Frost, Joseph M. Salazar
  • Patent number: 8907718
    Abstract: There is described a passive heater-and-diode multiplexing network for selective addressing of thermally-coupled and electrically-disconnected fuses within a passive device network (resistor/capacitor/inductor) or within an application circuit.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: December 9, 2014
    Assignee: Sensortechnics GmbH
    Inventors: Saed Salman, Oleg Grudin, Leslie M. Landsberger, Gennadiy Frolov, Tommy Tsang, Zhen-grong Huang
  • Publication number: 20140347120
    Abstract: Systems and methods of the invention generally relate to altering the functionality of a non-transient electronic device. A container holding an agent is located proximal to a non-transient electronic device capable of performing at least one function. The agent is capable of rendering the device incapable of performing the at least one function. The container is configured to controllably release the agent to the electronic device in a variety of passive and active eventualities.
    Type: Application
    Filed: May 21, 2014
    Publication date: November 27, 2014
    Applicant: TRANSIENT ELECTRONICS, INC.
    Inventors: Christopher Poirier, Anthony Stewart Campbell, Carmichael S. Roberts, John A. Rogers, Winston E. Henderson