Fusible Link Or Intentional Destruct Circuit Patents (Class 327/525)
  • Publication number: 20110188334
    Abstract: Provided is a fuse circuit capable of selectively using a power supply voltage for a logic operation according to an operation mode. The fuse circuit includes a mode generating circuit, a power supply voltage selection circuit, and at least one fuse unit. The mode generating circuit generates a plurality of mode signals. The power supply voltage selection circuit selects one out of a plurality of power supply voltages in response to the plurality of mode signals and outputs the selected power supply voltage to a first node. Each of the fuse units is coupled between the first node and a ground voltage and uses the selected power supply voltage as a power supply voltage for a logic operation. Thus, a semiconductor device including the fuse circuit may accurately test a connection state of a fuse.
    Type: Application
    Filed: February 3, 2011
    Publication date: August 4, 2011
    Inventors: Sang-Seok KANG, Sang-Man BYUN, Jae-Hoon JOO
  • Publication number: 20110176380
    Abstract: A plurality of fuses are arranged in pairs and configured such that each pair of fuses represents a data bit when one fuse of the pair is blown; represents an un-programmed bit when no fuse of the pair is blown; and represents a zero-ized bit when both fuses of the pair are blown. A fuse programming system programs the fuses of the pairs such that each pair represents a bit, comprising blowing a first fuse of a pair to represent a “1” bit, blowing a second fuse of a pair to represent a “0” bit, and blowing both fuses of a pair to represent a zero-ized pair, whereby if neither fuse of a pair is blown represents a null, un-programmed bit.
    Type: Application
    Filed: January 21, 2010
    Publication date: July 21, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: STEVEN R. BENTLEY, PAUL M. GRECO
  • Patent number: 7973590
    Abstract: A semiconductor device includes a first transmission line and a second transmission line disposed at different layers; a contact fuse coupled with the first transmission line and the second transmission line; a power driver configured to apply an electric stress to the contact fuse; and a fuse state output unit configured to output a fuse state signal having a logic level corresponding to an electric connection state of the contact fuse.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: July 5, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sang-Hoon Shin, Hyung-Dong Lee, Jun-Gi Choi
  • Publication number: 20110156801
    Abstract: A tamper resistant fuse design is generally presented. In this regard, an apparatus is introduced comprising a plurality of fuses in an integrated circuit device to store values and a plurality of resistors in parallel to the fuses, wherein each fuse includes a parallel resistor to provide a potential dissipation path around the fuse. Other embodiments are also described and claimed.
    Type: Application
    Filed: December 31, 2009
    Publication date: June 30, 2011
    Inventors: Xianghong Tong, Zhanping Chen, Kevin X. Zhang, Zhiyong Ma, Kevin D. Johnson, Jun He
  • Publication number: 20110140713
    Abstract: Fuse driver circuits, fuse driver testing circuitry, and methods for testing the fuse driver circuits using the testing circuitry are described. In some embodiments, the fuse driver circuit can be made using a fuse, a NMOS transistor, and a PMOS transistor. The drain of the NMOS transistor can be connected to the negative end of the fuse. The source of the NMOS transistor can be connected to ground. The drain of the PMOS transistor can be connected to a positive end of the fuse. The NMOS and PMOS transistors provide enhanced robustness to the fuse driver circuit in both undervoltage and overvoltage conditions. Other embodiments are also described.
    Type: Application
    Filed: December 10, 2010
    Publication date: June 16, 2011
    Inventors: Kenneth P. Snowdon, James Hall, William Robert Newberry, Roy Yarborough
  • Patent number: 7956671
    Abstract: In one embodiment of an e-fuse programming/re-programming circuit, the e-fuse has two short high atomic diffusion resistance conductor layers positioned on opposite sides and at a same end of a long low atomic diffusion resistance conductor layer. A voltage source is used to vary the polarity and, optionally, the magnitude of voltage applied to the terminals in order to control bi-directional flow of electrons within the long conductor layer and, thereby formation of opens and/or shorts at the long conductor layer-short conductor layer interfaces. The formation of such opens and/or shorts can be used to achieve different programming states. Other circuit structure embodiments incorporate e-fuses with additional conductor layers and additional terminals so as to allow for even more programming states. Also disclosed are embodiments of associated e-fuse programming and re-programming methods.
    Type: Grant
    Filed: July 1, 2009
    Date of Patent: June 7, 2011
    Assignee: International Business Machines Corporation
    Inventors: Michel J. Abou-Khalil, Tom C. Lee, Junjun Li, Robert J. Gauthier, Jr., Christopher S. Putnam, Souvick Mitra
  • Patent number: 7956674
    Abstract: A reservoir capacitor array circuit capable of allowing an internal voltage to be maintained stably, comprises a plurality of reservoir capacitors, each of the reservoir capacitors including a switch element which is connected between a power source voltage and a prescribed node and switched in response to a test enable signal which is enabled depending on a test mode signal or whether the fuse is cut or not, and a capacitor connected between the node and a ground voltage.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: June 7, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jong Won Lee
  • Publication number: 20110128068
    Abstract: A fuse circuit includes a control signal generation unit configured to generate a control signal that is enabled after a moment when a power-up signal is enabled, a potential control unit configured to control potentials of both ends of a fuse in response to the control signal, and a fuse output unit configured to be initialized in response to the power-up signal and output a fuse signal in response to whether the fuse is cut or not.
    Type: Application
    Filed: November 30, 2010
    Publication date: June 2, 2011
    Inventors: Sung-Soo CHI, Ki-Chang KWEAN, Woo-Young LEE
  • Patent number: 7940116
    Abstract: A fuse circuit may include a fuse section which generates a fuse control signal at an output terminal of the fuse circuit in response to a power-up signal according to a status of a fuse in the fuse section; and a current path break section which detects the status of the fuse in the fuse section prior to a trip period of the power-up signal and breaks an inrush current path created in the fuse section during the trip period based on the detected status.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: May 10, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sang-Kyun Park
  • Patent number: 7940113
    Abstract: A fuse trimming circuit includes trimming pads, a fuse resistance, an input circuit and current limit units. The fuse resistance is configured to be connected to the trimming pads and blown out by a trimming current which flows through the trimming pads. The input circuit is configured to output one of a first potential and a second potential based on whether or not the fuse resistance is blown out. The current limit units are configured to be provided on paths from one of the trimming pads through the fuse resistance to at least one of a first power line feeding the first potential and a second power line feeding said second potential, and paths from another of the trimming pads through the fuse resistance to said at least one of the first power line and the second power line.
    Type: Grant
    Filed: April 12, 2006
    Date of Patent: May 10, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Hirokazu Kawagoshi
  • Patent number: 7940115
    Abstract: A fuse circuit for a semiconductor integrated circuit includes a control unit configured to activate a fuse set control signal in response to an external command signal, and a plurality of fuse sets, each configured so that power is supplied to internal fuses in response to the activation of the fuse set control signal.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: May 10, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sun-Mo An, Shin-Ho Chu
  • Patent number: 7940114
    Abstract: A semiconductor device includes a fuse section having a plurality of fuse circuits configured to generate switch control signals; and an offset adjusting section configured to adjust an offset voltage of a differential amplifier based on the switch control signals supplied from output nodes of the plurality of fuse circuits. Each of the plurality of fuse circuits includes a fuse connected between a first power supply voltage and a cut node; a current source connected between a second power supply voltage and the output node; and a first transistor connected between the output node and the cut node and having a gate connected to the second power supply voltage.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: May 10, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Jun Fukuhara, Tsuyoshi Mitsuda
  • Publication number: 20110102067
    Abstract: A fuse device includes a fuse unit, which includes a cathode, an anode, and a fuse link coupling the cathode and the anode. A transistor includes at least a portion of the fuse unit to be used as an element of the transistor.
    Type: Application
    Filed: January 7, 2011
    Publication date: May 5, 2011
    Inventor: Deok-kee Kim
  • Patent number: 7915949
    Abstract: A method and an eFuse programming circuit for implementing resistance determination of an eFuse before initiating eFuse blow, and a design structure on which the subject circuit resides are provided. An eFuse on a chip is used to set current flow through a known resistor and measure the eFuse resistance. An applied voltage to program selected eFuses on the chip is selected responsive to an identified eFuse voltage value.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: March 29, 2011
    Assignee: International Business Machines Corporation
    Inventors: Karl Robert Erickson, Phil Christopher Felice Paone, David Paul Paulsen, John Edward Sheets, II
  • Patent number: 7911869
    Abstract: In a programmable circuit making use of fuse cells, a snapback NMOS or NPN transistor or SCR without reversible snapback capability is used as an anti-fuse, and programming comprises biasing the control electrode of the transistor to cause the transistor to go into snapback mode.
    Type: Grant
    Filed: August 5, 2005
    Date of Patent: March 22, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Peter J. Hopper, Yuri Mirgorodski
  • Patent number: 7911258
    Abstract: A semiconductor integrated circuit device including a fuse latch circuit including a fuse and a latch circuit for latching fuse data held in the fuse, a fuse counter circuit for counting the number of transfers of the fuse data, and a control circuit including a transmitter circuit for transmitting the fuse data to a memory macro connected to the control circuit, and a detour data path circuit which when the fuse data is not transferred, does not transfer the fuse data to the memory macro, and forms a detour data path for detouring the fuse data in the detour data path circuit itself.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: March 22, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Atsushi Suzuki
  • Publication number: 20110063015
    Abstract: The present invention provides a semiconductor memory device that includes: a fuse circuit having multiple fuse elements; and a fuse selection circuit connected to an internal address signal line that receives an address signal externally inputted. The fuse circuit is connected to the fuse selection circuit to receive an output from the fuse selection circuit, is supplied with an externally inputted trigger signal that permits nonvolatile recording of the fuse elements, and, in response to the output and the trigger signal, records the fuse element corresponding to the internal address signal line among the plurality of fuse elements while recording at least one of the plurality of fuse elements other than the fuse element thus recorded.
    Type: Application
    Filed: November 18, 2010
    Publication date: March 17, 2011
    Inventor: Takeshi OIKAWA
  • Patent number: 7907465
    Abstract: One-time programmable (OTP) nonvolatile fuse memory cells are disclosed that do not require decoding or addressing for reading their data content. Each fuse memory cell has its content latched at its output and available at all times and can be used, for example, for code storage memories, serial configuration memories, and as individual fuse bits for ID (identification), trimming, and other post-fabrication System-on-Chip (SoC) customization needs. Means are also provided for temporary data storage for design testing, etc. In alternative embodiments, using two differentially programmed fuses in a single memory cell, the selection and programming circuitry are merged.
    Type: Grant
    Filed: October 9, 2009
    Date of Patent: March 15, 2011
    Assignee: Kilopass Technology, Inc.
    Inventors: Jack Z. Peng, David Fong, Glen A. Rosendale
  • Patent number: 7902903
    Abstract: A circuit for electric fuses includes circuits for sensing status and programming that have separate paths for each operation. The circuit includes a plurality of electrically programmable fuses and, associated with each fuse, a switch for coupling a first terminal of the fuse to a ground supply for programming or to a comparator for sensing. The circuit uses a switched current source to supply current to the fuses for programming. The comparator senses a fuse status when a current source is switched through the fuse. The comparator compares a voltage across the fuse and associated switches to a comparison voltage across a comparison resistor and switches included for matching.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: March 8, 2011
    Assignee: Raytheon Company
    Inventors: Nick Rosik, Richard D Young, Mark E Stading, Denpol Thammanukultorn
  • Patent number: 7902902
    Abstract: The present invention relates to an anti-fuse repair control circuit which regulates transmission of a power voltage and a back-bias voltage that are converted to repair an anti-fuse to a circuit part. As such, the present invention prevents the influence of a high power voltage or a low back-bias voltage on a circuit part such as a cell, a peripheral circuit, or a core region during an anti-fuse repair. The anti-fuse repair control circuit includes an anti-fuse repair enabling part providing an anti-fuse repair enabling signal corresponding to a repair of an anti-fuse; a power voltage control part controlling transmission of a power voltage to a first circuit part according to an enablement state of the anti-fuse repair enabling signal; and a back-bias voltage control part controlling transmission of a back-bias voltage to a second circuit part according to the enablement state of the anti-fuse repair enabling signal.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: March 8, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Shin Ho Chu, Min Jung Koh
  • Patent number: 7888988
    Abstract: A fuse circuit includes a first power supply line, a second power supply line, a first current source connected between the first power supply line and an output terminal, a second current source connected between the second power supply line and the output terminal, the second current source having higher current supply capacity or current draw-out capacity than the first current source, and a fuse connected in series with the second current source between the second power supply line and the output terminal.
    Type: Grant
    Filed: August 5, 2008
    Date of Patent: February 15, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Kenji Mori, Masayuki Takori
  • Publication number: 20110032025
    Abstract: A programmable device includes a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having first and second ends, and an upper surface S; the first end (12a) is substantially wider than the second end (12b), and a metallic material is disposed on the upper surface; the metallic material being physically migratable along the upper surface responsive to an electrical current I flowable through the semiconductor material and the metallic material.
    Type: Application
    Filed: October 25, 2010
    Publication date: February 10, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: William R. Tonti, Wayne S. Berry, John A. Fifield, William H. Guthrie, Richard S. Kontra
  • Patent number: 7881032
    Abstract: A power supply controller having final test and trim circuitry. In one embodiment, a power supply controller for switched mode power supply includes a selector circuit, a trim circuit, a shutdown circuit and a disable circuit. The trim circuit includes a programmable circuit connection that can be selected by the selector circuit by toggling a voltage on an external terminal such as for example a power supply terminal, a control terminal or a function terminal of the power supply controller. The programmable circuit connection in the trim circuit can be programmed by applying a programming voltage to the external terminal. The shutdown circuit shuts down the power supply controller if the temperature rises above an over temperature threshold voltage. The shutdown circuit includes adjustment circuitry that can be used to test the shutdown circuit. The adjustment circuitry can adjust and reduce the over temperature threshold of the power supply controller.
    Type: Grant
    Filed: June 15, 2009
    Date of Patent: February 1, 2011
    Assignee: Power Integrations, Inc.
    Inventors: Balu Balakrishnan, Alex B. Djenguerian, Erdem Bircan
  • Patent number: 7880266
    Abstract: The present invention provides antifuse structures having an integrated heating element and methods of programming the same, the antifuse structures comprising first and second conductors and a dielectric layer formed between the conductors, where one or both of the conductors functions as both a conventional antifuse conductor and as a heating element for directly heating the antifuse dielectric layer during programming.
    Type: Grant
    Filed: December 3, 2007
    Date of Patent: February 1, 2011
    Assignee: International Business Machines Corporation
    Inventors: Byeongju Park, Subramanian S. Iyer, Chandrasekharan Kothandaraman
  • Publication number: 20110012629
    Abstract: After planarization of a gate level dielectric layer, a dummy structure is removed to form a recess. A first conductive material layer and an amorphous metal oxide are deposited into the recess area. A second conduct material layer fills the recess. After planarization, an electrical antifuse is formed within the filled recess area, which includes a first conductive material portion, an amorphous metal oxide portion, and a second conductive material portion. To program the electrical antifuse, current is passed between the two terminals in the pair of the conductive contacts to transform the amorphous metal oxide portion into a crystallized metal oxide portion, which has a lower resistance. A sensing circuit determines whether the metal oxide portion is in an amorphous state (high resistance state) or in a crystalline state (low resistance state).
    Type: Application
    Filed: July 15, 2009
    Publication date: January 20, 2011
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, FREESCALE SEMICONDUCTOR, INC.
    Inventors: Satya N. Chakravarti, Dechao Guo, Chuck T. Le, Byoung W. Min, Rajeevakumar V. Thekkemadathil, Keith Kwong Hon Wong
  • Publication number: 20110012668
    Abstract: A circuit for electric fuses includes circuits for sensing status and programming that have separate paths for each operation. The circuit includes a plurality of electrically programmable fuses and, associated with each fuse, a switch for coupling a first terminal of the fuse to a ground supply for programming or to a comparator for sensing. The circuit uses a switched current source to supply current to the fuses for programming. The comparator senses a fuse status when a current source is switched through the fuse. The comparator compares a voltage across the fuse and associated switches to a comparison voltage across a comparison resistor and switches included for matching.
    Type: Application
    Filed: July 14, 2009
    Publication date: January 20, 2011
    Inventors: Nick Rosik, Richard D. Young, Mark E. Stading, Denpol Thammanukultorn
  • Publication number: 20110006834
    Abstract: In some embodiments, a semiconductor device includes a fuse having a conductive portion configured to be blown when a current exceeding a rated value flows through the conductive portion, a first monitor wiring configured to monitor blowing of the conductive portion of the fuse, and a second monitor wiring configured to monitor blowing of the conductive portion of the fuse. The first monitor wiring and the second monitor wiring are connected to the conductive portion of the fuse so as to be away from a longitudinal center of the conductive portion.
    Type: Application
    Filed: July 9, 2010
    Publication date: January 13, 2011
    Applicants: SANYO ELECTRIC CO., LTD., SANYO SEMICONDUCTOR CO., LTD.
    Inventor: Hiroyuki Arai
  • Publication number: 20110001552
    Abstract: A semiconductor device includes a first transmission line and a second transmission line disposed at different layers; a contact fuse coupled with the first transmission line and the second transmission line; a power driver configured to apply an electric stress to the contact fuse; and a fuse state output unit configured to output a fuse state signal having a logic level corresponding to an electric connection state of the contact fuse.
    Type: Application
    Filed: November 10, 2009
    Publication date: January 6, 2011
    Inventors: Sang-Hoon SHIN, Hyung-Dong Lee, Jun-Gi Choi
  • Publication number: 20110001551
    Abstract: Disclosed are embodiments of an e-fuse programming/re-programming circuit. In one embodiment, the e-fuse has two short high atomic diffusion resistance conductor layers positioned on opposite sides and at a same end of a long low atomic diffusion resistance conductor layer. A voltage source is used to vary the polarity and, optionally, the magnitude of voltage applied to the terminals in order to control bi-directional flow of electrons within the long conductor layer and, thereby formation of opens and/or shorts at the long conductor layer-short conductor layer interfaces. The formation of such opens and/or shorts can be used to achieve different programming states. Other circuit structure embodiments incorporate e-fuses with additional conductor layers and additional terminals so as to allow for even more programming states. Also disclosed are embodiments of associated e-fuse programming and re-programming methods.
    Type: Application
    Filed: July 1, 2009
    Publication date: January 6, 2011
    Applicant: International Business Machines Corporation
    Inventors: Michel J. Abou-Khalil, Tom C. Lee, Junjun Li, Robert J. Gauthier, JR., Christopher S. Putnam, Souvick Mitra
  • Patent number: 7863947
    Abstract: A driving strength control circuit and a data output circuit for controlling driving strength of a data driver based on a user's demand are provided to make it possible to control the driving strength through a fuse cutting. The driving strength control circuit includes a fuse signal generating unit for generating a fuse signal based on a fuse cutting, a select signal generating unit for generating select signals in response to the fuse signal, a driving control signal generating unit for receiving set-up signals and generate driving control signals in response to the select signals, and a driving signal generating unit for driving signals by decoding the driving control signals.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: January 4, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Bok Rim Ko, Youk Hee Kim
  • Publication number: 20100321095
    Abstract: A semiconductor device (100) of the present invention has a structure in which an interlayer insulating layer (115) is formed on an uppermost wire (114), contacts (116, 117) penetrate the interlayer insulating layer (115), a lower electrode (118a) of the resistance variable element is formed on the interlayer insulating layer (115) to cover the contact (116), and resistance variable layer (119) is formed on the interlayer insulating layer (115) to cover the lower electrode (118a) and the contact (117). The contact (116) and the lower electrode (118a) serve as a first terminal, while the contact (117) serves as a second terminal.
    Type: Application
    Filed: June 8, 2009
    Publication date: December 23, 2010
    Inventors: Takumi Mikawa, Kazuhiko Shimakawa
  • Patent number: 7852697
    Abstract: In one embodiment, a integrated circuit (IC) configurable to have any one of a plurality of different feature sets, the IC including (a) one or more feature blocks adapted to be independently enabled or disabled, (b) a one-time-programmable (OTP) memory cell for each feature block, the OTP memory cell storing a value, and (c) a feature control module for each feature block, each feature control module connected between the corresponding OTP memory cell and the corresponding feature block, and adapted to enable or disable the corresponding feature block based on the value stored in the corresponding OTP memory cell. The OTP memory cells are programmed by a vendor to select the particular feature set for the IC which is to be available to a purchaser.
    Type: Grant
    Filed: February 17, 2009
    Date of Patent: December 14, 2010
    Assignee: Agere Systems Inc.
    Inventors: James L. Archibald, Kang W. Lee, Clinton H. Holder, Jr., Edwin A. Muth, Kreg D. Ulery
  • Publication number: 20100308896
    Abstract: A fuse circuit may include a fuse section which generates a fuse control signal at an output terminal of the fuse circuit in response to a power-up signal according to a status of a fuse in the fuse section; and a current path break section which detects the status of the fuse in the fuse section prior to a trip period of the power-up signal and breaks an inrush current path created in the fuse section during the trip period based on the detected status.
    Type: Application
    Filed: November 30, 2009
    Publication date: December 9, 2010
    Inventor: Sang-Kyun Park
  • Patent number: 7847587
    Abstract: A semiconductor integrated circuit has a voltage supply terminal; a first input terminal fed with a first input signal; an output terminal that outputs an output signal; a second input terminal fed with a second input signal; a first MOS transistor having one end connected to the voltage supply terminal and a gate electrode connected to the first input terminal; a second MOS transistor having one end connected to a first potential, an other end connected to the output terminal, and a gate electrode connected to the second input terminal; and a program element acting as a MOS transistor having one end connected to the other end of the second MOS transistor and an other end connected to a second potential higher than the first potential.
    Type: Grant
    Filed: March 10, 2009
    Date of Patent: December 7, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tomohiro Kobayashi
  • Publication number: 20100295605
    Abstract: A fuse circuit of a semiconductor device includes a plurality of fuse set units configured to compare an input address with address information programmed according to a fuse cutting state and a test control unit configured to enable one or more fuse set units selected based on a number of times that a selection signal is enabled in a test mode.
    Type: Application
    Filed: June 30, 2009
    Publication date: November 25, 2010
    Inventor: Seung-Lo Kim
  • Publication number: 20100290298
    Abstract: A fuse circuit or a redundancy circuit is capable of detecting a fuse with a crack. The fuse circuit includes a fuse block configured to drive an output node through a current path including a fuse in response to a fuse enable signal, and a voltage detection block configured to detect a voltage level of the output node based on a critical voltage adjusted according to a test mode signal, thereby generating a fuse condition signal.
    Type: Application
    Filed: June 26, 2009
    Publication date: November 18, 2010
    Inventors: Choung-Ki Song, Han-Sub Shin
  • Publication number: 20100290302
    Abstract: A fuse circuit includes a fuse unit configured to form a current path on a first node according to whether or not a fuse is cut; a driving current controller configured to control a potential level of the first node in response to a test signal; and an output unit configured to output a fuse state signal in response to the potential level of the first node.
    Type: Application
    Filed: June 30, 2009
    Publication date: November 18, 2010
    Inventors: Keun-Soo Song, Kwan-Weon Kim
  • Patent number: 7834659
    Abstract: E-fuses in an E-fuse memory array are programmed by applying a first programming pulse to a plurality of E-fuses to program the plurality of E-fuses to a first state; and then applying a second programming pulse to at least a selected E-fuse in the plurality of E-fuses to program the selected E-fuse to a second state.
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: November 16, 2010
    Assignee: Xilinx, Inc.
    Inventors: Hsung Jai Im, Sunhom Paak, Boon Yong Ang
  • Publication number: 20100283531
    Abstract: A fuse circuit includes a fuse having an intact state and a blown state. The fuse can be switched to the blown state by enabling a blowing current to flow through the fuse. The fuse is coupled between a first transistor and a second transistor in series. The first transistor and the second transistor are complementary transistors and operable for reducing an electrostatic discharge current flowing through the fuse. The first transistor and the second transistor are turned on to enable the blowing current to flow through the fuse.
    Type: Application
    Filed: May 8, 2009
    Publication date: November 11, 2010
    Inventors: Guo Xing LI, Songtao CHEN
  • Patent number: 7830205
    Abstract: A fuse circuit of a semiconductor integrated apparatus includes first and second fuse blocks. The first fuse block includes a first up fuse block where a first plurality of fuses are arranged and a first down fuse block where a second plurality of fuses are arranged. The second plurality of fuses comprises fewer fuses than the first plurality of fuses. The second fuse block includes a second up fuse block where a third plurality of fuses are arranged, the third plurality of fuses comprising the same number of fuses as the second plurality of fuses, and a second down fuse block that includes a fourth plurality of fuses, the fourth plurality of fuses comprising the same number of fuses as the first plurality of fuses. The first up fuse block is opposite the second up fuse block and the first down fuse block is opposite the second down fuse block.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: November 9, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Gyung Tae Kim
  • Patent number: 7816945
    Abstract: Programmable fuse-type through silicon vias (TSVs) in silicon chips are provided with non-programmable TSVs in the same chip. The programmable fuse-type TSVs may employ a region within the TSV structure having sidewall spacers that restrict the cross-sectional conductive path of the TSV adjacent a chip surface contact pad. Application of sufficient current by programming circuitry causes electromigration of metal to create a void in the contact pad and, thus, an open circuit. Programming may be carried out by complementary circuitry on two adjacent chips in a multi-story chip stack.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: October 19, 2010
    Assignee: International Business Machines Corporation
    Inventors: Kai Di Feng, Louis Lu-Chen Hsu, Ping-Chuan Wang, Zhijian Yang
  • Publication number: 20100246237
    Abstract: Programmable anti-fuse circuitry including at least one anti-fuse cell having a first anti-fuse device coupled between a supply voltage and a first node and a second anti-fuse device coupled between the first node and a ground voltage, and control logic coupled to the first node and arranged to generate a programming voltage having one of at least a first voltage level for breaking-down the first anti-fuse device but not the second anti-fuse device and coupling the first node to the supply voltage; and a second voltage level for breaking-down the second anti-fuse device but not the first anti-fuse device and coupling the first node to the ground voltage.
    Type: Application
    Filed: October 3, 2007
    Publication date: September 30, 2010
    Inventors: Bertrand Borot, Michel Zecri
  • Publication number: 20100244933
    Abstract: An electric fuse cutoff control circuit controlling cutoff of a plurality of electric fuses including: a cutoff information storage circuit adapted to store cutoff information about whether or not each of the plurality of electric fuses is cut off; a cutoff information control circuit controlling the cutoff of the plurality of electric fuses based on an output signal of the cutoff information storage circuit; and a cutoff information renewal circuit receiving an output signal of the cutoff information control circuit and renewing the cutoff information set for the cutoff information storage circuit.
    Type: Application
    Filed: March 22, 2010
    Publication date: September 30, 2010
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventor: Tatsuru MATSUO
  • Patent number: 7804352
    Abstract: Provided may be a multi-level anti-fuse and methods of fabricating and operating the same. The multi-level anti-fuse may include at least three anti-fuses having a plurality of anti-fuses connected in parallel constituting a parallel connection structure and at least one anti-fuse connected to the parallel connection structure in series, wherein the parallel connection structure may have a smaller resistance than the resistance of the anti-fuse connected in series, the plurality of anti-fuses connected in parallel may include dielectric layers having different thicknesses from one another, and the breakdown voltages of each dielectric layer may be different from one another.
    Type: Grant
    Filed: April 2, 2009
    Date of Patent: September 28, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Junghun Sung, Sangmoo Choi, Deokkee Kim, Soojung Hwang
  • Publication number: 20100232203
    Abstract: A first terminal and a second terminal of a FinFET transistor are used as two terminals of an anti-fuse. To program the anti-fuse, a gate of the FinFET transistor is controlled, and a voltage having a predetermined amplitude and a predetermined duration is applied to the first terminal to cause the first terminal to be electrically shorted to the second terminal.
    Type: Application
    Filed: March 16, 2010
    Publication date: September 16, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tao-Wen CHUNG, Po-Yao KE, Shine CHUNG, Fu-Lung HSUEH
  • Publication number: 20100225381
    Abstract: The invention relates to a semiconductor device comprising a fuse that is implemented as a bar type pattern that forms a straight line instead of a pattern that is difficult to secure a manufacturing margin. A fuse block including a plurality of fuses comprises a plurality of first connection parts, each including a blowing area, a plurality of second connection parts, wherein the plurality of the second connection parts and the plurality of the corresponding first connection parts respectively form part of the fuse, and a common connection unit configured to electrically connect the plurality of the first connection parts and the plurality of the second connection parts.
    Type: Application
    Filed: December 30, 2009
    Publication date: September 9, 2010
    Applicant: Hynix Semiconductor Inc.
    Inventor: Byung Wook BAE
  • Patent number: 7791402
    Abstract: An electrical fuse determination circuit that can speedily and reliably incorporate an electrical fuse data and improve a reliability of electrical fuse device, includes a first electrical fuse device of which one end connects with a higher voltage, a second electrical fuse device of which one end connects with a lower voltage, a set portion that puts one of the first electrical fuse device and the second electrical fuse device in a conductive state, and a determination portion that determines a voltage level of a predetermined contact point connecting the other end of the first electrical fuse device and the other end of the second electrical fuse device.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: September 7, 2010
    Assignee: Elpida Memory, Inc.
    Inventor: Hiroshi Akamatsu
  • Publication number: 20100214008
    Abstract: A method of programming a transistor-based fuse structure is provided. The fuse structure is realized in a semiconductor device having a semiconductor substrate, transistor devices formed on the semiconductor substrate, and the transistor-based fuse structure formed on the semiconductor substrate. The transistor-based fuse structure includes a plurality of transistor-based fuses, and the method begins by selecting, from the plurality of transistor-based fuses, a first target fuse to be programmed for operation in a low-resistance/high-current state, the first target fuse having a first source, a first gate, a first drain, and a first gate insulator layer between the first gate and the semiconductor substrate.
    Type: Application
    Filed: February 25, 2009
    Publication date: August 26, 2010
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Ruigang LI, David Donggang WU, James F. BULLER, Jingrong ZHOU
  • Patent number: 7764108
    Abstract: A gate of a MOS transistor connected to a fuse device in series is controlled by an AND circuit connected to the same power source as the fuse device is connected, thereby pulling down one input of the AND circuit to a ground. Thus, misprogramming of the fuse device when an LSI power source is turned ON/OFF can be prevented.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: July 27, 2010
    Assignee: Panasonic Corporation
    Inventors: Yasuhiro Agata, Masanori Shirahama, Toshiaki Kawasaki, Shinichi Sumi, Yasue Yamamoto
  • Patent number: 7760008
    Abstract: Digital trimming logic is included in a microelectronic device of a type that produces an output signal in response to an input signal and a threshold signal. Trimming logic values are produced in response to a clock signal that is applied to the device in a trimming mode. The clock signal can be applied to a device pin that is used in normal operation to provide an output signal, thus allowing the pin to serve a dual function. The trimming logic changes the trimming logic value in response to the clock signal until the trimming logic value reaches a trim value at which the threshold signal is substantially equal to the input signal. The trimming logic then stores the trim value in a non-volatile memory and enters a locked mode in which further trimming is prevented and the device is ready for normal operation.
    Type: Grant
    Filed: October 28, 2008
    Date of Patent: July 20, 2010
    Assignee: Avago Technologies ECBU IP (Singapore) Pte. Ltd.
    Inventors: Jia Peng, Kwee Chong Chang, Shan Jiang