Abstract: An anti-fuse circuit includes an anti-fuse coupled to a sensing node, a driving unit configured to rupture the anti-fuse in response to a rupture enable signal, an anti-fuse status detecting unit configured to output an anti-fuse status detecting signal in response to a voltage at the sensing node corresponding to a rupture status of the anti-fuse, and a sensing current supplying unit configured to supply sensing current to the sensing node in response to a rupture sensing signal.

Abstract: An integrated circuit, wherein a voltage-adjustable power supply circuit (42) receives a first power supply control signal (6) output by a programming power supply control circuit (41), outputs a first voltage signal to a efuse circuit (44) by a power source switching circuit (43) and outputs the first voltage signal to other functional circuits (45) of the integrated circuit, and the efuse circuit (44) receives the first voltage signal and a first programming control signal (5) output by the programming power supply control circuit (41) and burns out a corresponding efuse therein; or the voltage adjustable power supply circuit (42) receives a second power supply control signal (6) output by the programming power supply control circuit (41) and outputs a second voltage signal to other functional circuits (45) of the integrated circuit, and the efuse circuit (44) receives a second programming control signal (5) output by the programming power supply control circuit (41) and ensures a corresponding efuse therei

Abstract: An apparatus in an integrated circuit for precluding the use of extended JTAG operations. The apparatus has a JTAG control chain, a feature fuse, a level sensor, and an access controller. The JTAG control chain is configured to enable/disable the extended JTAG operations. The feature fuse is configured to indicate whether the extended JTAG features are to be disabled. The level sensor is configured to monitor an external voltage signal, and configured to indicate that the external voltage signal is at an illegal level. The access controller is coupled to the feature fuse, the level sensor, and the JTAG control chain, and is configured to determine if the feature fuse is blown, and is configured to direct the JTAG control chain to disable the extended JTAG operations if the external voltage signal is at an illegal level regardless of whether the feature fuse is blown.

Abstract: An apparatus in an integrated circuit for precluding the use of extended JTAG operations. The apparatus has a JTAG control chain, a feature fuse, and an access controller. The JTAG control chain is configured to enable/disable the extended JTAG operations. The feature fuse is configured to indicate whether the extended JTAG features are to be disabled. The access controller is coupled to the feature fuse and the JTAG control chain. The access controller determines if the feature fuse is blown, and directs the JTAG control chain to disable the extended JTAG operations.

Abstract: Various embodiments of a fuse circuit of a semiconductor apparatus are disclosed. In one exemplary embodiment, the fuse circuit may include a fuse whose electrical connection state can be changed by an electrical stress applied thereto and a plurality of self boosting units configured to perform self boosting operations under the control of a rupture enable signal. The self boosting units may also be configured to generate stress voltages and supply the generated stress voltages to the fuse. The fuse circuit may also include a precharge unit configured to supply a precharge voltage to the fuse in response to a precharge signal and a cross-coupled latching amplification unit configured to sense a change in a voltage level of the precharge voltage supplied to the fuse, with reference to a reference voltage, and output a fuse state signal.

Abstract: An electrically programmable fuse controller, a method of controlling a drive voltage of an integrated circuit (IC) and an IC incorporating the controller or the method. In one embodiment, the controller includes a VID eFuse controller configured to receive and write a voltage identifier to an associated eFuse and thereafter allow the voltage identifier to be read from the eFuse and employed to set a drive voltage of an integrated circuit associated with the VID eFuse controller.

Abstract: A fuse circuit includes a fuse having an intact state and a blown state. The fuse can be switched to the blown state by enabling a blowing current to flow through the fuse. The fuse is coupled between a first transistor and a second transistor in series. The first transistor and the second transistor are complementary transistors and operable for reducing an electrostatic discharge current flowing through the fuse. The first transistor and the second transistor are turned on to enable the blowing current to flow through the fuse.

Abstract: An electronic device with polarity reversal protected connections and irreversibly interruptible programming connections, wherein the interruption is performed through safety elements provided in the programming paths, behind which safety elements diodes are disposed which block towards ground in normal operation, so that an overload current can be passed through the safety elements and through the diodes to ground through intentional polarity reversal of the respective connections, whereby the safety elements are destroyed and the programming conductors are irreversibly interrupted.

Abstract: A method of cutting an electrical fuse including a first conductor and a second conductor, the first conductor including a first cutting target region, the second conductor branched from the first conductor and connected to the first conductor and including a second cutting target region, which are formed on a semiconductor substrate, the method includes flowing a current in the first conductor, causing material of the first conductor to flow outward near a coupling portion connecting the first conductor to the second conductor, and cutting the first cutting target region and the second cutting target region.

Abstract: A transistor-based fuse structure is realized in a semiconductor device having a semiconductor substrate, transistor devices formed on the semiconductor substrate, and the transistor-based fuse structure formed on the semiconductor substrate. The transistor-based fuse structure includes a plurality of transistor-based fuses, and the method begins by selecting, from the plurality of transistor-based fuses, a first target fuse to be programmed for operation in a low-resistance/high-current state, the first target fuse having a first source, a first gate, a first drain, and a first gate insulator layer between the first gate and the semiconductor substrate. The method applies a first set of program voltages to the first source, the first gate, and the first drain to cause breakdown of the first gate insulator layer such that current can flow from the first source to the first gate through the first gate insulator layer, and from the first gate to the first drain through the first gate insulator layer.

Abstract: An electronic fuse system includes: a pad, an electronic fuse circuit, a first switch circuit, and a control circuit. The pad is used of receiving a reference voltage. The electronic fuse circuit is used of changing a voltage level when a current signal passes. The first switch circuit coupled between the pad and the electronic fuse circuit, for controlling the first switch circuit disabled or enabled according to a switch control signal. The control circuit, coupled to the first switch circuit, for transferring the switch control signal according a control signal and a lock signal. Wherein, when the lock signal is enabled, the control signal is unable to control the control circuit to turn on the first switch circuit.

Abstract: An integrated circuit device such as a structured ASIC includes a mask-programmable portion and a post-fabrication-programmable portion. The mask-programmable portion includes circuitry that is able to read information from the post-fabrication-programmable portion and use that information to affect operation of other componentry of the mask-programmable portion. Signal timing is an example of the kind of operation that may be affected by the above-mentioned information, which may allow post-fabrication timing tuning of the device.

Abstract: A fuse circuit includes a fuse, a control pulse generation unit, and an equipotential element. The fuse is coupled between a power supply voltage terminal and a first node. The control pulse generation unit is configured to generate a control pulse including a pulse generated in a period in which a power-up period is ended. The equipotential element is configured to make the first node have the same potential as a power supply voltage in response to the control pulse.

Abstract: A fuse circuit includes a fuse information signal generation unit and an output driving unit. The fuse information signal generation unit is configured to precharge a fuse information signal in response to a precharge signal and drive the fuse information signal in response to a selection signal capable of cutting a fuse. The output driving unit configured to equally maintain potentials at both terminals of the fuse in response to a control signal.

Abstract: In one embodiment, a redundancy circuit may include a comparison unit configured to record a first repair address through fuse cutting, compare a comparison address with the first repair address, and output a comparison result signal; a first fuse enable unit configured to output a first fuse enable signal for repairing the first repair address; a second fuse enable unit configured to output a second fuse enable signal for repairing a second repair address; a first determination unit configured to output a first repair determination signal in response to receipt of the first fuse enable signal and the comparison result signal; and a second determination unit configured to output a second repair determination signal in response to receipt of an inverted signal of a value of the comparison result signal corresponding to the certain bit, remaining bits, and the second fuse enable signal.

Abstract: A fuse circuit includes an electric fuse coupled to a first voltage source; a low resistance unit coupled to the electric fuse and having a junction which is capable of breaking down; and a switching unit coupled between the low resistance unit and a second voltage source.

Abstract: A fuse circuit includes a fuse driving unit, a separation/connection unit, a voltage equalization unit, and a latching unit. The fuse driving unit is configured to drive an output terminal in response to a fuse reset signal, depending on data programmed in a fuse. The separation/connection unit is disposed between the fuse and the output terminal and configured to separate or connect the fuse from or to the output terminal in response to a control signal. The voltage equalization unit is configured to equalize both ends of the fuse to the same voltage in response to the control signal. The latching unit is configured to latch and output the output terminal driven by the fuse driving unit.

Abstract: An fusing apparatus for correcting process variation is provided. The fusing apparatus for correcting the process variation of the semiconductor device includes a fusing part including a fusing resistor fused by a current penetrating; a current driving transistor for fusing the fusing resistor by driving a fusing current according to a fusing enable signal applied; a current path part for building a current path by connecting to the fusing part, and controlling a first node voltage according to a fusing state of the fusing resistor; and a latch part for latching a second node signal inversely amplified from the first node voltage, and outputting the latch value when a power-on reset part operates in a normal mode. Using the fusing cell, the test time can be reduced and the current consumption can be greatly decreased in the fusing process.

Abstract: A fuse set includes a first row constituted by a plurality of fuses which are arranged with a first spacing; a second row including a plurality of fuses which are disposed to correspond to the fuses of the first row on the same plane, and separated from the fuses of the first row with a second spacing; and a connection part disposed between the first row and the second row and electrically connected with the plurality of fuses of the first row and the plurality of fuses of the second row, wherein the connection part and the pluralities of fuses of the first and second rows are disposed on different planes.

Abstract: A circuit adjustable after packaging includes a functional circuit supplied with a power potential and a reference potential and has at least one parameter adjustable by programming at least one programmable element and a circuit to program the programmable element of the functional circuit. The adjustable circuit also includes a limiter circuit to limit the voltage between the power supply potential and the reference potential to an adjustable limiting voltage, and a circuit to adjust the limiting voltage. After adjusting a parameter of the functional circuit, the limiting voltage of the limiter circuit is adjusted.

Abstract: Provided is a fuse circuit capable of selectively using a power supply voltage for a logic operation according to an operation mode. The fuse circuit includes a mode generating circuit, a power supply voltage selection circuit, and at least one fuse unit. The mode generating circuit generates a plurality of mode signals. The power supply voltage selection circuit selects one out of a plurality of power supply voltages in response to the plurality of mode signals and outputs the selected power supply voltage to a first node. Each of the fuse units is coupled between the first node and a ground voltage and uses the selected power supply voltage as a power supply voltage for a logic operation. Thus, a semiconductor device including the fuse circuit may accurately test a connection state of a fuse.

Abstract: A plurality of fuses are arranged in pairs and configured such that each pair of fuses represents a data bit when one fuse of the pair is blown; represents an un-programmed bit when no fuse of the pair is blown; and represents a zero-ized bit when both fuses of the pair are blown. A fuse programming system programs the fuses of the pairs such that each pair represents a bit, comprising blowing a first fuse of a pair to represent a “1” bit, blowing a second fuse of a pair to represent a “0” bit, and blowing both fuses of a pair to represent a zero-ized pair, whereby if neither fuse of a pair is blown represents a null, un-programmed bit.

Abstract: A semiconductor device includes a first transmission line and a second transmission line disposed at different layers; a contact fuse coupled with the first transmission line and the second transmission line; a power driver configured to apply an electric stress to the contact fuse; and a fuse state output unit configured to output a fuse state signal having a logic level corresponding to an electric connection state of the contact fuse.

Abstract: A tamper resistant fuse design is generally presented. In this regard, an apparatus is introduced comprising a plurality of fuses in an integrated circuit device to store values and a plurality of resistors in parallel to the fuses, wherein each fuse includes a parallel resistor to provide a potential dissipation path around the fuse. Other embodiments are also described and claimed.

Abstract: Fuse driver circuits, fuse driver testing circuitry, and methods for testing the fuse driver circuits using the testing circuitry are described. In some embodiments, the fuse driver circuit can be made using a fuse, a NMOS transistor, and a PMOS transistor. The drain of the NMOS transistor can be connected to the negative end of the fuse. The source of the NMOS transistor can be connected to ground. The drain of the PMOS transistor can be connected to a positive end of the fuse. The NMOS and PMOS transistors provide enhanced robustness to the fuse driver circuit in both undervoltage and overvoltage conditions. Other embodiments are also described.

Abstract: A reservoir capacitor array circuit capable of allowing an internal voltage to be maintained stably, comprises a plurality of reservoir capacitors, each of the reservoir capacitors including a switch element which is connected between a power source voltage and a prescribed node and switched in response to a test enable signal which is enabled depending on a test mode signal or whether the fuse is cut or not, and a capacitor connected between the node and a ground voltage.

Abstract: In one embodiment of an e-fuse programming/re-programming circuit, the e-fuse has two short high atomic diffusion resistance conductor layers positioned on opposite sides and at a same end of a long low atomic diffusion resistance conductor layer. A voltage source is used to vary the polarity and, optionally, the magnitude of voltage applied to the terminals in order to control bi-directional flow of electrons within the long conductor layer and, thereby formation of opens and/or shorts at the long conductor layer-short conductor layer interfaces. The formation of such opens and/or shorts can be used to achieve different programming states. Other circuit structure embodiments incorporate e-fuses with additional conductor layers and additional terminals so as to allow for even more programming states. Also disclosed are embodiments of associated e-fuse programming and re-programming methods.

Abstract: A fuse circuit includes a control signal generation unit configured to generate a control signal that is enabled after a moment when a power-up signal is enabled, a potential control unit configured to control potentials of both ends of a fuse in response to the control signal, and a fuse output unit configured to be initialized in response to the power-up signal and output a fuse signal in response to whether the fuse is cut or not.

Abstract: A fuse circuit may include a fuse section which generates a fuse control signal at an output terminal of the fuse circuit in response to a power-up signal according to a status of a fuse in the fuse section; and a current path break section which detects the status of the fuse in the fuse section prior to a trip period of the power-up signal and breaks an inrush current path created in the fuse section during the trip period based on the detected status.

Abstract: A semiconductor device includes a fuse section having a plurality of fuse circuits configured to generate switch control signals; and an offset adjusting section configured to adjust an offset voltage of a differential amplifier based on the switch control signals supplied from output nodes of the plurality of fuse circuits. Each of the plurality of fuse circuits includes a fuse connected between a first power supply voltage and a cut node; a current source connected between a second power supply voltage and the output node; and a first transistor connected between the output node and the cut node and having a gate connected to the second power supply voltage.

Abstract: A fuse trimming circuit includes trimming pads, a fuse resistance, an input circuit and current limit units. The fuse resistance is configured to be connected to the trimming pads and blown out by a trimming current which flows through the trimming pads. The input circuit is configured to output one of a first potential and a second potential based on whether or not the fuse resistance is blown out. The current limit units are configured to be provided on paths from one of the trimming pads through the fuse resistance to at least one of a first power line feeding the first potential and a second power line feeding said second potential, and paths from another of the trimming pads through the fuse resistance to said at least one of the first power line and the second power line.

Abstract: A fuse circuit for a semiconductor integrated circuit includes a control unit configured to activate a fuse set control signal in response to an external command signal, and a plurality of fuse sets, each configured so that power is supplied to internal fuses in response to the activation of the fuse set control signal.

Abstract: A fuse device includes a fuse unit, which includes a cathode, an anode, and a fuse link coupling the cathode and the anode. A transistor includes at least a portion of the fuse unit to be used as an element of the transistor.

Abstract: A method and an eFuse programming circuit for implementing resistance determination of an eFuse before initiating eFuse blow, and a design structure on which the subject circuit resides are provided. An eFuse on a chip is used to set current flow through a known resistor and measure the eFuse resistance. An applied voltage to program selected eFuses on the chip is selected responsive to an identified eFuse voltage value.

Abstract: In a programmable circuit making use of fuse cells, a snapback NMOS or NPN transistor or SCR without reversible snapback capability is used as an anti-fuse, and programming comprises biasing the control electrode of the transistor to cause the transistor to go into snapback mode.

Abstract: A semiconductor integrated circuit device including a fuse latch circuit including a fuse and a latch circuit for latching fuse data held in the fuse, a fuse counter circuit for counting the number of transfers of the fuse data, and a control circuit including a transmitter circuit for transmitting the fuse data to a memory macro connected to the control circuit, and a detour data path circuit which when the fuse data is not transferred, does not transfer the fuse data to the memory macro, and forms a detour data path for detouring the fuse data in the detour data path circuit itself.

Abstract: The present invention provides a semiconductor memory device that includes: a fuse circuit having multiple fuse elements; and a fuse selection circuit connected to an internal address signal line that receives an address signal externally inputted. The fuse circuit is connected to the fuse selection circuit to receive an output from the fuse selection circuit, is supplied with an externally inputted trigger signal that permits nonvolatile recording of the fuse elements, and, in response to the output and the trigger signal, records the fuse element corresponding to the internal address signal line among the plurality of fuse elements while recording at least one of the plurality of fuse elements other than the fuse element thus recorded.

Abstract: One-time programmable (OTP) nonvolatile fuse memory cells are disclosed that do not require decoding or addressing for reading their data content. Each fuse memory cell has its content latched at its output and available at all times and can be used, for example, for code storage memories, serial configuration memories, and as individual fuse bits for ID (identification), trimming, and other post-fabrication System-on-Chip (SoC) customization needs. Means are also provided for temporary data storage for design testing, etc. In alternative embodiments, using two differentially programmed fuses in a single memory cell, the selection and programming circuitry are merged.

Abstract: A circuit for electric fuses includes circuits for sensing status and programming that have separate paths for each operation. The circuit includes a plurality of electrically programmable fuses and, associated with each fuse, a switch for coupling a first terminal of the fuse to a ground supply for programming or to a comparator for sensing. The circuit uses a switched current source to supply current to the fuses for programming. The comparator senses a fuse status when a current source is switched through the fuse. The comparator compares a voltage across the fuse and associated switches to a comparison voltage across a comparison resistor and switches included for matching.

Abstract: The present invention relates to an anti-fuse repair control circuit which regulates transmission of a power voltage and a back-bias voltage that are converted to repair an anti-fuse to a circuit part. As such, the present invention prevents the influence of a high power voltage or a low back-bias voltage on a circuit part such as a cell, a peripheral circuit, or a core region during an anti-fuse repair. The anti-fuse repair control circuit includes an anti-fuse repair enabling part providing an anti-fuse repair enabling signal corresponding to a repair of an anti-fuse; a power voltage control part controlling transmission of a power voltage to a first circuit part according to an enablement state of the anti-fuse repair enabling signal; and a back-bias voltage control part controlling transmission of a back-bias voltage to a second circuit part according to the enablement state of the anti-fuse repair enabling signal.

Abstract: A fuse circuit includes a first power supply line, a second power supply line, a first current source connected between the first power supply line and an output terminal, a second current source connected between the second power supply line and the output terminal, the second current source having higher current supply capacity or current draw-out capacity than the first current source, and a fuse connected in series with the second current source between the second power supply line and the output terminal.

Abstract: A programmable device includes a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having first and second ends, and an upper surface S; the first end (12a) is substantially wider than the second end (12b), and a metallic material is disposed on the upper surface; the metallic material being physically migratable along the upper surface responsive to an electrical current I flowable through the semiconductor material and the metallic material.

Abstract: A power supply controller having final test and trim circuitry. In one embodiment, a power supply controller for switched mode power supply includes a selector circuit, a trim circuit, a shutdown circuit and a disable circuit. The trim circuit includes a programmable circuit connection that can be selected by the selector circuit by toggling a voltage on an external terminal such as for example a power supply terminal, a control terminal or a function terminal of the power supply controller. The programmable circuit connection in the trim circuit can be programmed by applying a programming voltage to the external terminal. The shutdown circuit shuts down the power supply controller if the temperature rises above an over temperature threshold voltage. The shutdown circuit includes adjustment circuitry that can be used to test the shutdown circuit. The adjustment circuitry can adjust and reduce the over temperature threshold of the power supply controller.

Abstract: The present invention provides antifuse structures having an integrated heating element and methods of programming the same, the antifuse structures comprising first and second conductors and a dielectric layer formed between the conductors, where one or both of the conductors functions as both a conventional antifuse conductor and as a heating element for directly heating the antifuse dielectric layer during programming.

Abstract: A circuit for electric fuses includes circuits for sensing status and programming that have separate paths for each operation. The circuit includes a plurality of electrically programmable fuses and, associated with each fuse, a switch for coupling a first terminal of the fuse to a ground supply for programming or to a comparator for sensing. The circuit uses a switched current source to supply current to the fuses for programming. The comparator senses a fuse status when a current source is switched through the fuse. The comparator compares a voltage across the fuse and associated switches to a comparison voltage across a comparison resistor and switches included for matching.

Abstract: After planarization of a gate level dielectric layer, a dummy structure is removed to form a recess. A first conductive material layer and an amorphous metal oxide are deposited into the recess area. A second conduct material layer fills the recess. After planarization, an electrical antifuse is formed within the filled recess area, which includes a first conductive material portion, an amorphous metal oxide portion, and a second conductive material portion. To program the electrical antifuse, current is passed between the two terminals in the pair of the conductive contacts to transform the amorphous metal oxide portion into a crystallized metal oxide portion, which has a lower resistance. A sensing circuit determines whether the metal oxide portion is in an amorphous state (high resistance state) or in a crystalline state (low resistance state).

Abstract: In some embodiments, a semiconductor device includes a fuse having a conductive portion configured to be blown when a current exceeding a rated value flows through the conductive portion, a first monitor wiring configured to monitor blowing of the conductive portion of the fuse, and a second monitor wiring configured to monitor blowing of the conductive portion of the fuse. The first monitor wiring and the second monitor wiring are connected to the conductive portion of the fuse so as to be away from a longitudinal center of the conductive portion.

Abstract: Disclosed are embodiments of an e-fuse programming/re-programming circuit. In one embodiment, the e-fuse has two short high atomic diffusion resistance conductor layers positioned on opposite sides and at a same end of a long low atomic diffusion resistance conductor layer. A voltage source is used to vary the polarity and, optionally, the magnitude of voltage applied to the terminals in order to control bi-directional flow of electrons within the long conductor layer and, thereby formation of opens and/or shorts at the long conductor layer-short conductor layer interfaces. The formation of such opens and/or shorts can be used to achieve different programming states. Other circuit structure embodiments incorporate e-fuses with additional conductor layers and additional terminals so as to allow for even more programming states. Also disclosed are embodiments of associated e-fuse programming and re-programming methods.

Abstract: A semiconductor device includes a first transmission line and a second transmission line disposed at different layers; a contact fuse coupled with the first transmission line and the second transmission line; a power driver configured to apply an electric stress to the contact fuse; and a fuse state output unit configured to output a fuse state signal having a logic level corresponding to an electric connection state of the contact fuse.

Abstract: A driving strength control circuit and a data output circuit for controlling driving strength of a data driver based on a user's demand are provided to make it possible to control the driving strength through a fuse cutting. The driving strength control circuit includes a fuse signal generating unit for generating a fuse signal based on a fuse cutting, a select signal generating unit for generating select signals in response to the fuse signal, a driving control signal generating unit for receiving set-up signals and generate driving control signals in response to the select signals, and a driving signal generating unit for driving signals by decoding the driving control signals.