Fusible Link Or Intentional Destruct Circuit Patents (Class 327/525)
  • Patent number: 8258856
    Abstract: An antifuse circuit includes a protection circuit. The antifuse circuit receives a program voltage using a non-connection (NC) pin or ball of a semiconductor device. The protection circuit prevents an unintended voltage lower than the program voltage from being applied to the antifuse circuit.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: September 4, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Cheon-An Lee, Seong-Jin Jang, Sang-Woong Shin
  • Patent number: 8253476
    Abstract: A trimmer circuit is so configured that an electronic device will break down to produce a high current to trim a fuse. The electronic device is selectively configured to have a breakdown voltage lower than an applied voltage, for the trigger of its breakdown to be controllable. In an embodiment, the electronic device is switched between two states having two breakdown voltages respectively, and the applied voltage is higher than one of the breakdown voltages and lower than the other one.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: August 28, 2012
    Assignee: Richtek Technology Copr.
    Inventor: Chia-Wei Liao
  • Patent number: 8253475
    Abstract: A fuse detecting apparatus includes a detector, a calibrator and a logical operating unit. The detector includes a detecting switch module and a detecting latch. The detecting switch module generates an initial detecting result according to first and second control signals and a status of the fuse. The detecting latch stores a voltage level of the initial detecting result or maintains its originally stored voltage level according to the initial detecting result for generating a pre-calibrating detecting signal. The calibrator includes a calibrating switch module and a calibrating latch. The calibrating switch module generates a calibrating result according to the first and second control signals. The calibrating latch stores the calibrating result and generates a calibrating signal accordingly. The logical operating unit generates a calibrated detecting signal according to the pre-calibrating detecting signal and the calibrating signal.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: August 28, 2012
    Assignee: Winbond Electronics Corp.
    Inventor: Che-Min Lin
  • Patent number: 8254198
    Abstract: Programmable anti-fuse circuitry including at least one anti-fuse cell having a first anti-fuse device coupled between a supply voltage and a first node and a second anti-fuse device coupled between the first node and a ground voltage, and control logic coupled to the first node and arranged to generate a programming voltage having one of at least a first voltage level for breaking-down the first anti-fuse device but not the second anti-fuse device and coupling the first node to the supply voltage; and a second voltage level for breaking-down the second anti-fuse device but not the first anti-fuse device and coupling the first node to the ground voltage.
    Type: Grant
    Filed: October 3, 2007
    Date of Patent: August 28, 2012
    Assignees: STMicroelectronics (Crolles 2) SAS, Freescale Semiconductor, Inc.
    Inventors: Bertrand Borot, Michel Zecri
  • Patent number: 8242831
    Abstract: A tamper resistant fuse design is generally presented. In this regard, an apparatus is introduced comprising a plurality of fuses in an integrated circuit device to store values and a plurality of resistors in parallel to the fuses, wherein each fuse includes a parallel resistor to provide a potential dissipation path around the fuse. Other embodiments are also described and claimed.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: August 14, 2012
    Assignee: Intel Corporation
    Inventors: Xianghong Tong, Zhanping Chen, Kevin X. Zhang, Zhiyong Ma, Kevin D. Johnson, Jun He
  • Publication number: 20120194260
    Abstract: Such a device is disclosed that includes a first ladder fuse for which blowing points are arranged at a first coordinate and a second ladder fuse for which blowing points are arranged at a second coordinate. When adjustment data for adjusting circuit characteristics is within a first range, a trimming operation is performed on both the first and second ladder fuses, and when the adjustment data for adjusting the circuit characteristics is within a second range, the trimming operation is performed on the second ladder fuse without performing the trimming operation on the first ladder fuse. This configuration eliminates a necessity of irradiation on the first ladder fuse with a laser when the adjustment data is within the second range.
    Type: Application
    Filed: January 25, 2012
    Publication date: August 2, 2012
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Shigeyuki NAKAZAWA
  • Patent number: 8233306
    Abstract: Methods, systems, and apparatus, including computer program products for programming memory. In one aspect, a program circuit includes a first transistive element; a second transistive element coupled to a first end of the first transistive element; a burn subcircuit, the burn subcircuit including a third transistive element coupled to a fourth transistive element, where the drain of the third transistive element is coupled to a second end of the first transistive element, and the source of the third transistive element is coupled to the drain of the fourth transistive element; and a fifth transistive element coupled in parallel to the fourth transistive element. Control logic coupled to the first transistive element, the burn subcircuit, and the fourth transistive element selectively enables the second transistive element, selectively enables the fourth transistive element, and selectively enables the fifth transistive element to enable a read mode or a program mode.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: July 31, 2012
    Assignee: Volterra Semiconductor Corporation
    Inventor: Marco A. Zuniga
  • Publication number: 20120188819
    Abstract: Systems and methods for CMOS-based MEMS programmable memories are described. In one aspect, the systems and methods provide for a programmable memory having multiple memory cells. Each memory cell includes an electrode disposed within the memory cell, and a conductor material having two ends disposed proximate to the electrode. The programmable memory provides means for applying a voltage between the electrode and the conductor material, e.g., a voltage source. The applied voltage generates an electrostatic force sufficient to permanently alter the conductor material, thereby programming the memory cell.
    Type: Application
    Filed: January 23, 2012
    Publication date: July 26, 2012
    Applicant: Baolab Microsystems SL
    Inventors: Josep Montanya Silvestre, Marco Antonio Llamas Morote
  • Patent number: 8223575
    Abstract: A multi-level electrical fuse system comprises at least one fuse box having at least one electrical fuse, a programming device serially coupled to the electrical fuse, and a variable power supply coupled to the fuse box and configured to generate two or more voltage levels.
    Type: Grant
    Filed: March 8, 2007
    Date of Patent: July 17, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Lung Lin, Jui-Jen Wu, Shine Chung, Fu-Lung Hsuen
  • Publication number: 20120176180
    Abstract: There is described a passive heater-and-diode multiplexing network for selective addressing of thermally-coupled and electrically-disconnected fuses within a passive device network (resistor/capacitor/inductor) or within an application circuit.
    Type: Application
    Filed: March 4, 2010
    Publication date: July 12, 2012
    Inventors: Salman Saed, Oleg Grudin, Leslie M. Landsberger, Gennadiy Frolov, Tommy Tsang, Zhen-grong Huang
  • Patent number: 8217710
    Abstract: The invention relates to a semiconductor device comprising a fuse that is implemented as a bar type pattern that forms a straight line instead of a pattern that is difficult to secure a manufacturing margin. A fuse block including a plurality of fuses comprises a plurality of first connection parts, each including a blowing area, a plurality of second connection parts, wherein the plurality of the second connection parts and the plurality of the corresponding first connection parts respectively form part of the fuse, and a common connection unit configured to electrically connect the plurality of the first connection parts and the plurality of the second connection parts.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: July 10, 2012
    Assignee: Hynix Semiconductor Inc
    Inventor: Byung Wook Bae
  • Patent number: 8217709
    Abstract: A semiconductor device includes a signal output unit, and a decision unit. The signal output unit includes m (?2) pieces of fuses, a NAND gate, resistance elements, and an output terminal. The decision unit decides whether n or more pieces (m?n?2) of fuses are disconnected out of the m pieces of fuses included in the signal output unit, and outputs the result of a decision. When m=n=2, the decision unit is constituted of a NOR gate having two input terminals connected to a respective end of the fuses. Thus, a H-level potential signal is output at an output terminal of the NOR gate when the decision result is affirmative. On the other hand, when the decision result is negative, a L-level potential signal is output at the output terminal.
    Type: Grant
    Filed: August 28, 2006
    Date of Patent: July 10, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroaki Ohkubo, Yasutaka Nakashiba
  • Publication number: 20120169402
    Abstract: A semiconductor device includes an electric fuse circuit and a program protective circuit. The electric fuse circuit includes a fuse element and a transistor connected together in series and placed between a program power supply and a grounding, and controlling sections. The program protective circuit is placed in parallel with the electric fuse circuit and between the program power supply and the grounding. When a surge voltage is applied between the program power supply and the grounding, the foregoing structure allows a part of a surge electric current can flow through the program protective circuit.
    Type: Application
    Filed: March 12, 2012
    Publication date: July 5, 2012
    Applicant: PANASONIC CORPORATION
    Inventors: TOSHIAKI KAWASAKI, YASUHIRO AGATA, MASANORI SHIRAHAMA, TOSHIHIRO KOUGAMI, KATSUYA ARAI
  • Publication number: 20120161855
    Abstract: An apparatus for programming an electronically programmable semiconductor fuse applies a programming current to a fuse link as a series of multiple pulses. Application of the programming current as a series of multiple short pulses provides a level of programming current sufficiently high to ensure reliable and effective electromigration while avoiding exceeding temperature limits of the fuse link.
    Type: Application
    Filed: March 6, 2012
    Publication date: June 28, 2012
    Applicant: International Business Machines Corporation
    Inventors: Dan Moy, Stephen Wu, Peter Wang, Brian W. Messenger, Edwin Soler, Gabriel Chiulli
  • Patent number: 8207783
    Abstract: An integrated circuit includes a sensing circuit, a fuse box, and a fuse bus decoder. The sensing circuit includes an output node, and the fuse box includes a plurality of switches coupled in series with a plurality of resistive elements. The fuse box is coupled to the output node of the sensing circuit from which the fuse box is configured to receive a current. The fuse bus decoder is coupled to the fuse box and includes at least one demultiplexer configured to receive a signal and in response output a plurality of control signals for selectively opening and closing the switches of the fuse box to adjust a resistance across the fuse box. A voltage of the output node of the sense amplifier is based on a resistance the fuse box and the current.
    Type: Grant
    Filed: August 16, 2010
    Date of Patent: June 26, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Li Liao, Sung-Chieh Lin, Kuoyuan Hsu
  • Publication number: 20120146710
    Abstract: Implementations are presented herein that relate to a fuse device, an integrated circuit including a fuse device, a method of implementing a fuse device and a method of programming a fuse device.
    Type: Application
    Filed: February 16, 2012
    Publication date: June 14, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Vianney Choserot, Gunther Lehmann, Franz Ungar
  • Patent number: 8193851
    Abstract: A fuse circuit of a semiconductor device includes a plurality of fuse set units configured to compare an input address with address information programmed according to a fuse cutting state and a test control unit configured to enable one or more fuse set units selected based on a number of times that a selection signal is enabled in a test mode.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: June 5, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seung-Lo Kim
  • Publication number: 20120119820
    Abstract: A fuse circuit comprises a fuse set and an enable circuit. The enable circuit is configured to receive a test mode enable signal and a power up signal to generate an enable signal and a voltage level to the fuse set for indicating whether an external supply voltage reaches a predetermined value and whether a test mode is enabled. In particular, an output signal of the fuse set is constant in the test mode, regardless of whether a fuse in the fuse set is blown or not.
    Type: Application
    Filed: November 16, 2010
    Publication date: May 17, 2012
    Applicant: Elite Semiconductor Memory Technology Inc.
    Inventor: Pei Jey Huang
  • Patent number: 8179189
    Abstract: A trimming circuit is provided. The trimming circuit had at least a trimming cell, and each of the at least trimming cell includes three current paths and a fuse. A first one of the current paths is interrupted when a second one of the current paths is uninterrupted, and the first one of the current paths is uninterrupted when the second one of the current paths is interrupted. When a trimming control signal is at an enable state, a third one of the current paths is uninterrupted, such that the fuse is blown. Based on the status of the fuse, the trimming circuit is capable of trimming an output voltage or an output current of an electric apparatus.
    Type: Grant
    Filed: March 11, 2010
    Date of Patent: May 15, 2012
    Assignee: Himax Analogic, Inc.
    Inventor: Chao-Wen Chiu
  • Publication number: 20120105136
    Abstract: A fuse system for use with a disposable component of a device may include a disposable component having at least a first lockout circuit and a second lockout circuit. The first lockout circuit may include a first fuse link, and the second lockout circuit may include a second fuse link. The fuse system may include a computing device in communication with the first lockout circuit and the second lockout circuit, and a computer-readable storage medium in communication with the computing device. The computer-readable storage medium may include one or more programming instructions for deactivating the first fuse link at a first time, and deactivating the second fuse link at a second time.
    Type: Application
    Filed: October 27, 2010
    Publication date: May 3, 2012
    Applicant: THERMALTHERAPEUTIC SYSTEMS, INC.
    Inventors: J. Michael Fausset, Michael Sturdevant, Robert Schindler, Michael Terry
  • Publication number: 20120092062
    Abstract: A semiconductor system includes a controller; a semiconductor device comprising a plurality of stacked semiconductor chips stacked over the controller, and a plurality of through-silicon vias (TSVs) configured to commonly transfer a signal to the plurality of stacked semiconductor chips; and a defect information transfer TSV configured to transfer TSV defect information sequentially outputted from at least one of the semiconductor chips to the controller, wherein the controller comprises: a plurality of first repair fuse units configured to set first fuse information based on the TSV defect information; and a plurality of first TSV selection units configured to selectively drive the TSVs in response to the first fuse information.
    Type: Application
    Filed: December 28, 2011
    Publication date: April 19, 2012
    Inventors: Jeong-Woo Lee, Hyung-Dong Lee, Sang-Hoon Shin, Hyang-Hwa Choi
  • Publication number: 20120086500
    Abstract: A fuse detecting apparatus including a detector, a calibrator and a logical operating unit is disclosed. The detector includes a detecting switch module and a detecting latch. The detecting switch module generates an initial detecting result according to a first and a second control signals and a status of the fuse. The detecting latch stores a voltage level of the initial detecting result or maintains its originally stored voltage level according to the initial detecting result for generating a pre-calibrating detecting signal. The calibrator includes a calibrating switch module and a calibrating latch. The calibrating switch module generates a calibrating result according to the first and the second control signals. The calibrating latch stores the calibrating result and generates a calibrating signal accordingly. The logical operating unit generates a calibrated detecting signal according to the pre-calibrating detecting signal and the calibrating signal.
    Type: Application
    Filed: October 8, 2010
    Publication date: April 12, 2012
    Applicant: Winbond Electronics Corp.
    Inventor: Che-Min Lin
  • Patent number: 8154942
    Abstract: Circuitry on an integrated circuit is provided that may be used to program fuses such as polysilicon fuses. Fuse programming may be performed using an elevated power supply voltage. Other circuitry on the integrated circuit may be powered using a standard power supply voltage that is less than the elevated power supply voltage. Fuse sensing may be performed using the standard power supply voltage. A control block may be used to produce a fuse programming control signal. Power-on-reset circuitry may monitor the elevated power supply voltage and may produce a corresponding elevated power supply voltage power-on-reset signal indicative of whether the elevated power supply voltage is valid. The power-on-reset circuitry may also produce a standard power supply power-on-reset signal indicative of whether the standard power supply voltage is valid. The power-on-reset signals may be used in controlling fuse programming and fuse sensing.
    Type: Grant
    Filed: November 17, 2008
    Date of Patent: April 10, 2012
    Assignee: Altera Corporation
    Inventors: Ping Xiao, Weiying Ding, Myron Wai Wong, Mario E. Guzman
  • Publication number: 20120081165
    Abstract: A high voltage tolerative inverter circuit includes a first PMOS transistor with a source connected to VDDQ and drain connected to a first node; a second PMOS transistor with a source connected to the first node and a drain connected to an output; a first NMOS transistor with a source connected to VSS and a drain connected to a second node; a second NMOS transistor with a source connected to the second node and a drain connected to the output. A gate of the first PMOS transistor is controlled by a first signal having a voltage swing between VDDQ and VSS. A gate of the first NMOS transistor and the second PMOS transistor are controlled by a second signal having a voltage swing between VDD and VSS. VDD is lower than VDDQ. A gate of the second NMOS transistor is biased with a first voltage greater than VSS.
    Type: Application
    Filed: September 30, 2010
    Publication date: April 5, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jiann-Tseng HUANG, Sung-Chieh LIN, Kuoyuan HSU, Po-Hung CHEN
  • Patent number: 8149044
    Abstract: A trimmer circuit is so configured that an electronic device will break down to produce a high current to trim a fuse. The electronic device is selectively configured to have a breakdown voltage lower than an applied voltage, for the trigger of its breakdown to be controllable. In an embodiment, the electronic device is switched between two states having two breakdown voltages respectively, and the applied voltage is higher than one of the breakdown voltages and lower than the other one.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: April 3, 2012
    Assignee: Richtek Technology Corp.
    Inventor: Chia-Wei Liao
  • Publication number: 20120075006
    Abstract: A method for controlling performance of an integrated circuit using a zero-pin serial interface is provided. The method comprises identifying a desired performance characteristic of the circuit, and transmitting a first change mode signal to the circuit on a first pin to cause the circuit to enter an instruction reception mode, with the first pin performing differently during a normal operation mode. The method also comprises transmitting a performance adjusting instruction to the circuit on a second pin when the circuit is in the instruction reception mode, with the second pin performing differently during the normal operation mode, and transmitting a second change mode signal to the circuit on the first pin to cause the circuit to enter the normal operation mode. An output performance of the circuit is compared to the desired performance characteristic, with the output performance being the performance of the circuit during the normal operation mode.
    Type: Application
    Filed: March 30, 2011
    Publication date: March 29, 2012
    Applicant: INTERSIL AMERICAS INC.
    Inventors: Hoa Vu, Ping Huang
  • Publication number: 20120068761
    Abstract: A soft clamp semiconductor device for preventing inadvertent programming of an unselected anti-fuse (AF) element comprises a MOSFET which includes a first well region disposed in a substrate. Source and drain regions are disposed in the first well region, the drain region being electrically coupled to the first capacitive plate of the AF element and the source region being electrically coupled to a second capacitive plate of the AF element. An insulated gate is disposed over a channel area of the first well region that separates the drain and source regions. A gate capacitance of the MOSFET is substantially less than a capacitance of the unselected AF element such that when a programming voltage is applied to the first capacitive plate, a current flows through the MOSFET that charges the second capacitive plate, thereby reducing a voltage build-up across the unselected AF element.
    Type: Application
    Filed: September 17, 2010
    Publication date: March 22, 2012
    Applicant: Power Integrations, Inc.
    Inventor: Sujit Banerjee
  • Patent number: 8134445
    Abstract: Electrical fuse indicators, systems and methods for detecting when fuses enter an open state involve a wireless identification element, which alerts a communication unit that the fuse has entered an open state. The wireless identification device may include an antenna. The antenna may be in contact with a fuse element, such that opening of the fuse element renders the antenna inoperable. Alternatively the antenna may be connected to the fuse element in such a manner that opening of the fuse element alters the frequency on which the antenna transmits. A logic port may also be used to detect the operational state of a fuse. Use of such indicators is compatible with existing infrastructure.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: March 13, 2012
    Assignee: Cooper Technologies Company
    Inventors: Frank Anthony Doljack, Owais M. Mughal, Hundi P. Kamath, John M. Ackermann
  • Patent number: 8119958
    Abstract: A matrix of explosive cells can include plural explosive cells formed in an array in a common substrate. Each cell can be formed as a recess filled with explosive material. An ignition device has an addressable ignition source for each cell. This matrix can be used in combination with a projectile guidance system. The projectile guidance system includes an antenna, a transceiver and a control processor. A method of guiding a projectile can include firing a projectile at a target, tracking the projectile and the target, determining a desired change in a flight path of the projectile, transmitting guidance commands to effect the desired change in the projectile's flight path to the projectile, receiving the guidance commands onboard the projectile and selectively igniting an explosive cell in a matrix of addressable explosive cells contained in a common substrate using the guidance commands.
    Type: Grant
    Filed: February 19, 2009
    Date of Patent: February 21, 2012
    Assignee: Lockheed Martin Corporation
    Inventors: Christian Adams, Kenneth S. Gurley, Tara Y. Rohter, Patrick A. Nelson
  • Publication number: 20120019310
    Abstract: A trimmer circuit is so configured that an electronic device will break down to produce a high current to trim a fuse. The electronic device is selectively configured to have a breakdown voltage lower than an applied voltage, for the trigger of its breakdown to be controllable. In an embodiment, the electronic device is switched between two states having two breakdown voltages respectively, and the applied voltage is higher than one of the breakdown voltages and lower than the other one.
    Type: Application
    Filed: September 28, 2011
    Publication date: January 26, 2012
    Applicant: RICHTEK TECHNOLOGY CORP.
    Inventor: CHIA-WEI LIAO
  • Publication number: 20120008448
    Abstract: An anti-fuse circuit includes an anti-fuse coupled to a sensing node, a driving unit configured to rupture the anti-fuse in response to a rupture enable signal, an anti-fuse status detecting unit configured to output an anti-fuse status detecting signal in response to a voltage at the sensing node corresponding to a rupture status of the anti-fuse, and a sensing current supplying unit configured to supply sensing current to the sensing node in response to a rupture sensing signal.
    Type: Application
    Filed: September 8, 2010
    Publication date: January 12, 2012
    Inventors: Hong-Jung Kim, Jin-Hee Cho
  • Publication number: 20110316615
    Abstract: An integrated circuit, wherein a voltage-adjustable power supply circuit (42) receives a first power supply control signal (6) output by a programming power supply control circuit (41), outputs a first voltage signal to a efuse circuit (44) by a power source switching circuit (43) and outputs the first voltage signal to other functional circuits (45) of the integrated circuit, and the efuse circuit (44) receives the first voltage signal and a first programming control signal (5) output by the programming power supply control circuit (41) and burns out a corresponding efuse therein; or the voltage adjustable power supply circuit (42) receives a second power supply control signal (6) output by the programming power supply control circuit (41) and outputs a second voltage signal to other functional circuits (45) of the integrated circuit, and the efuse circuit (44) receives a second programming control signal (5) output by the programming power supply control circuit (41) and ensures a corresponding efuse therei
    Type: Application
    Filed: May 6, 2010
    Publication date: December 29, 2011
    Inventors: Jiang Xiong, Hongwei Huang
  • Publication number: 20110316613
    Abstract: An apparatus in an integrated circuit for precluding the use of extended JTAG operations. The apparatus has a JTAG control chain, a feature fuse, and an access controller. The JTAG control chain is configured to enable/disable the extended JTAG operations. The feature fuse is configured to indicate whether the extended JTAG features are to be disabled. The access controller is coupled to the feature fuse and the JTAG control chain. The access controller determines if the feature fuse is blown, and directs the JTAG control chain to disable the extended JTAG operations.
    Type: Application
    Filed: June 25, 2010
    Publication date: December 29, 2011
    Applicant: VIA TECHNOLOGIES, INC.
    Inventors: G. Glenn Henry, Dinesh K. Jain
  • Publication number: 20110316614
    Abstract: An apparatus in an integrated circuit for precluding the use of extended JTAG operations. The apparatus has a JTAG control chain, a feature fuse, a level sensor, and an access controller. The JTAG control chain is configured to enable/disable the extended JTAG operations. The feature fuse is configured to indicate whether the extended JTAG features are to be disabled. The level sensor is configured to monitor an external voltage signal, and configured to indicate that the external voltage signal is at an illegal level. The access controller is coupled to the feature fuse, the level sensor, and the JTAG control chain, and is configured to determine if the feature fuse is blown, and is configured to direct the JTAG control chain to disable the extended JTAG operations if the external voltage signal is at an illegal level regardless of whether the feature fuse is blown.
    Type: Application
    Filed: June 25, 2010
    Publication date: December 29, 2011
    Applicant: VIA TECHNOLOGIES, INC.
    Inventors: G. Glenn Henry, Dinesh K. Jain
  • Publication number: 20110291744
    Abstract: Various embodiments of a fuse circuit of a semiconductor apparatus are disclosed. In one exemplary embodiment, the fuse circuit may include a fuse whose electrical connection state can be changed by an electrical stress applied thereto and a plurality of self boosting units configured to perform self boosting operations under the control of a rupture enable signal. The self boosting units may also be configured to generate stress voltages and supply the generated stress voltages to the fuse. The fuse circuit may also include a precharge unit configured to supply a precharge voltage to the fuse in response to a precharge signal and a cross-coupled latching amplification unit configured to sense a change in a voltage level of the precharge voltage supplied to the fuse, with reference to a reference voltage, and output a fuse state signal.
    Type: Application
    Filed: November 18, 2010
    Publication date: December 1, 2011
    Applicant: Hynix Semiconductor Inc.
    Inventor: Hong Gyeom KIM
  • Publication number: 20110279171
    Abstract: An electrically programmable fuse controller, a method of controlling a drive voltage of an integrated circuit (IC) and an IC incorporating the controller or the method. In one embodiment, the controller includes a VID eFuse controller configured to receive and write a voltage identifier to an associated eFuse and thereafter allow the voltage identifier to be read from the eFuse and employed to set a drive voltage of an integrated circuit associated with the VID eFuse controller.
    Type: Application
    Filed: May 12, 2010
    Publication date: November 17, 2011
    Applicant: LSI Corporation
    Inventors: Lihui Cao, Saket K. Goyal, Thai-Minh Nguyen
  • Patent number: 8058921
    Abstract: A fuse circuit includes a fuse having an intact state and a blown state. The fuse can be switched to the blown state by enabling a blowing current to flow through the fuse. The fuse is coupled between a first transistor and a second transistor in series. The first transistor and the second transistor are complementary transistors and operable for reducing an electrostatic discharge current flowing through the fuse. The first transistor and the second transistor are turned on to enable the blowing current to flow through the fuse.
    Type: Grant
    Filed: May 8, 2009
    Date of Patent: November 15, 2011
    Assignee: O2Micro, Inc.
    Inventors: Guo Xing Li, Songtao Chen
  • Patent number: 8054124
    Abstract: An electronic device with polarity reversal protected connections and irreversibly interruptible programming connections, wherein the interruption is performed through safety elements provided in the programming paths, behind which safety elements diodes are disposed which block towards ground in normal operation, so that an overload current can be passed through the safety elements and through the diodes to ground through intentional polarity reversal of the respective connections, whereby the safety elements are destroyed and the programming conductors are irreversibly interrupted.
    Type: Grant
    Filed: January 15, 2009
    Date of Patent: November 8, 2011
    Assignee: ASM Automation Sensorik Messtechnik GmbH
    Inventor: Peter Wirth
  • Publication number: 20110267136
    Abstract: A method of cutting an electrical fuse including a first conductor and a second conductor, the first conductor including a first cutting target region, the second conductor branched from the first conductor and connected to the first conductor and including a second cutting target region, which are formed on a semiconductor substrate, the method includes flowing a current in the first conductor, causing material of the first conductor to flow outward near a coupling portion connecting the first conductor to the second conductor, and cutting the first cutting target region and the second cutting target region.
    Type: Application
    Filed: July 8, 2011
    Publication date: November 3, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Takehiro UEDA
  • Patent number: 8050077
    Abstract: A transistor-based fuse structure is realized in a semiconductor device having a semiconductor substrate, transistor devices formed on the semiconductor substrate, and the transistor-based fuse structure formed on the semiconductor substrate. The transistor-based fuse structure includes a plurality of transistor-based fuses, and the method begins by selecting, from the plurality of transistor-based fuses, a first target fuse to be programmed for operation in a low-resistance/high-current state, the first target fuse having a first source, a first gate, a first drain, and a first gate insulator layer between the first gate and the semiconductor substrate. The method applies a first set of program voltages to the first source, the first gate, and the first drain to cause breakdown of the first gate insulator layer such that current can flow from the first source to the first gate through the first gate insulator layer, and from the first gate to the first drain through the first gate insulator layer.
    Type: Grant
    Filed: February 25, 2009
    Date of Patent: November 1, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ruigang Li, David Donggang Wu, James F. Buller, Jingrong Zhou
  • Publication number: 20110248775
    Abstract: An electronic fuse system includes: a pad, an electronic fuse circuit, a first switch circuit, and a control circuit. The pad is used of receiving a reference voltage. The electronic fuse circuit is used of changing a voltage level when a current signal passes. The first switch circuit coupled between the pad and the electronic fuse circuit, for controlling the first switch circuit disabled or enabled according to a switch control signal. The control circuit, coupled to the first switch circuit, for transferring the switch control signal according a control signal and a lock signal. Wherein, when the lock signal is enabled, the control signal is unable to control the control circuit to turn on the first switch circuit.
    Type: Application
    Filed: April 7, 2011
    Publication date: October 13, 2011
    Inventor: Kai-Yin Liu
  • Patent number: 8037444
    Abstract: An integrated circuit device such as a structured ASIC includes a mask-programmable portion and a post-fabrication-programmable portion. The mask-programmable portion includes circuitry that is able to read information from the post-fabrication-programmable portion and use that information to affect operation of other componentry of the mask-programmable portion. Signal timing is an example of the kind of operation that may be affected by the above-mentioned information, which may allow post-fabrication timing tuning of the device.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: October 11, 2011
    Assignee: Altera Corporation
    Inventors: Boon Jin Ang, Bee Yee Ng, Thow Pang Chong, Yu Fong Tan
  • Publication number: 20110241764
    Abstract: In one embodiment, a redundancy circuit may include a comparison unit configured to record a first repair address through fuse cutting, compare a comparison address with the first repair address, and output a comparison result signal; a first fuse enable unit configured to output a first fuse enable signal for repairing the first repair address; a second fuse enable unit configured to output a second fuse enable signal for repairing a second repair address; a first determination unit configured to output a first repair determination signal in response to receipt of the first fuse enable signal and the comparison result signal; and a second determination unit configured to output a second repair determination signal in response to receipt of an inverted signal of a value of the comparison result signal corresponding to the certain bit, remaining bits, and the second fuse enable signal.
    Type: Application
    Filed: July 27, 2010
    Publication date: October 6, 2011
    Applicant: Hynix Semiconductor Inc.
    Inventor: Ki Hoon Lee
  • Publication number: 20110241761
    Abstract: A fuse circuit includes a fuse information signal generation unit and an output driving unit. The fuse information signal generation unit is configured to precharge a fuse information signal in response to a precharge signal and drive the fuse information signal in response to a selection signal capable of cutting a fuse. The output driving unit configured to equally maintain potentials at both terminals of the fuse in response to a control signal.
    Type: Application
    Filed: December 21, 2010
    Publication date: October 6, 2011
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Keun Kook KIM
  • Publication number: 20110241762
    Abstract: A fuse circuit includes a fuse, a control pulse generation unit, and an equipotential element. The fuse is coupled between a power supply voltage terminal and a first node. The control pulse generation unit is configured to generate a control pulse including a pulse generated in a period in which a power-up period is ended. The equipotential element is configured to make the first node have the same potential as a power supply voltage in response to the control pulse.
    Type: Application
    Filed: January 26, 2011
    Publication date: October 6, 2011
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Keun Kook KIM
  • Publication number: 20110234303
    Abstract: A fuse circuit includes an electric fuse coupled to a first voltage source; a low resistance unit coupled to the electric fuse and having a junction which is capable of breaking down; and a switching unit coupled between the low resistance unit and a second voltage source.
    Type: Application
    Filed: July 21, 2010
    Publication date: September 29, 2011
    Applicant: Hynix Semiconductor Inc.
    Inventor: Jun Gi CHOI
  • Publication number: 20110235453
    Abstract: A fuse circuit includes a fuse driving unit, a separation/connection unit, a voltage equalization unit, and a latching unit. The fuse driving unit is configured to drive an output terminal in response to a fuse reset signal, depending on data programmed in a fuse. The separation/connection unit is disposed between the fuse and the output terminal and configured to separate or connect the fuse from or to the output terminal in response to a control signal. The voltage equalization unit is configured to equalize both ends of the fuse to the same voltage in response to the control signal. The latching unit is configured to latch and output the output terminal driven by the fuse driving unit.
    Type: Application
    Filed: June 15, 2010
    Publication date: September 29, 2011
    Inventors: Sung-Soo CHI, Ki-Chang Kwean
  • Patent number: 8026737
    Abstract: An fusing apparatus for correcting process variation is provided. The fusing apparatus for correcting the process variation of the semiconductor device includes a fusing part including a fusing resistor fused by a current penetrating; a current driving transistor for fusing the fusing resistor by driving a fusing current according to a fusing enable signal applied; a current path part for building a current path by connecting to the fusing part, and controlling a first node voltage according to a fusing state of the fusing resistor; and a latch part for latching a second node signal inversely amplified from the first node voltage, and outputting the latch value when a power-on reset part operates in a normal mode. Using the fusing cell, the test time can be reduced and the current consumption can be greatly decreased in the fusing process.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: September 27, 2011
    Assignee: Korea Electronics Technology Institute
    Inventors: Yeon-Kug Moon, Jae-Ho Kim, Il-Yeup Ahn, Sang-Shin Lee, Min-Hwan Song, Kwang-Ho Won
  • Publication number: 20110199150
    Abstract: A fuse set includes a first row constituted by a plurality of fuses which are arranged with a first spacing; a second row including a plurality of fuses which are disposed to correspond to the fuses of the first row on the same plane, and separated from the fuses of the first row with a second spacing; and a connection part disposed between the first row and the second row and electrically connected with the plurality of fuses of the first row and the plurality of fuses of the second row, wherein the connection part and the pluralities of fuses of the first and second rows are disposed on different planes.
    Type: Application
    Filed: April 22, 2011
    Publication date: August 18, 2011
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Jong Jin LEE
  • Patent number: 7999597
    Abstract: A circuit adjustable after packaging includes a functional circuit supplied with a power potential and a reference potential and has at least one parameter adjustable by programming at least one programmable element and a circuit to program the programmable element of the functional circuit. The adjustable circuit also includes a limiter circuit to limit the voltage between the power supply potential and the reference potential to an adjustable limiting voltage, and a circuit to adjust the limiting voltage. After adjusting a parameter of the functional circuit, the limiting voltage of the limiter circuit is adjusted.
    Type: Grant
    Filed: May 21, 2009
    Date of Patent: August 16, 2011
    Assignee: STMicroelectronics S.A.
    Inventors: Sébastien Laville, Frédéric Goutti