Fusible Link Or Intentional Destruct Circuit Patents (Class 327/525)
  • Publication number: 20130162329
    Abstract: An anti-fuse circuit includes a control block configured to generate a first control signal and a second control signal in response to a first test signal and a second test signal, and a fuse set block configured to perform a primary fuse rupture operation in response to the first control signal and to perform a secondary fuse rupture operation in response to the second control signal, the fuse set block activating a fuse signal if any one of the primary fuse rupture operation and the secondary fuse rupture operation succeeds.
    Type: Application
    Filed: September 3, 2012
    Publication date: June 27, 2013
    Applicant: SK HYNIX INC.
    Inventor: Hoe Kwon JUNG
  • Publication number: 20130162263
    Abstract: A fuse circuit includes a data line, a plurality of fuse cells selectively programmed and electrically connected with the data line in response to respective selection signals, a dummy fuse cell electrically connected with the data line in response to a test signal, and a sense amplifier configured to sense a data of the data line. The fuse circuit includes a plurality of fuses, reduces the area thereof, and easily detects whether a sense amplifier operates properly or not in the fuse circuit.
    Type: Application
    Filed: August 27, 2012
    Publication date: June 27, 2013
    Inventor: Kwi-Dong KIM
  • Patent number: 8471623
    Abstract: An integrated circuit, wherein a voltage-adjustable power supply circuit (42) receives a first power supply control signal (6) output by a programming power supply control circuit (41), outputs a first voltage signal to a efuse circuit (44) by a power source switching circuit (43) and outputs the first voltage signal to other functional circuits (45) of the integrated circuit, and the efuse circuit (44) receives the first voltage signal and a first programming control signal (5) output by the programming power supply control circuit (41) and burns out a corresponding efuse therein; or the voltage adjustable power supply circuit (42) receives a second power supply control signal (6) output by the programming power supply control circuit (41) and outputs a second voltage signal to other functional circuits (45) of the integrated circuit, and the efuse circuit (44) receives a second programming control signal (5) output by the programming power supply control circuit (41) and ensures a corresponding efuse therei
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: June 25, 2013
    Assignee: Actions Semiconductor Co., Ltd.
    Inventors: Jiang Xiong, Hongwei Huang
  • Publication number: 20130147542
    Abstract: A fuse circuit includes a programming fuse signal generation block configured to generate parity signals, logic levels of which are determined according to addresses selected among a plurality of addresses with a programming enable signal enabled, and generate programming fuse signals which are programmed in response to the programming enable signal, the plurality of addresses and the parity signals; a corrected pulse generation block configured to correct an error included in the programming fuse signals and generate corrected pulses; and a fuse unit configured to generate fuse signals which are reprogrammed according to the corrected pulses.
    Type: Application
    Filed: August 9, 2012
    Publication date: June 13, 2013
    Applicant: SK HYNIX INC.
    Inventor: Sang Kwon LEE
  • Patent number: 8461907
    Abstract: A semiconductor device includes a signal output unit, and a decision unit. The signal output unit includes m (?2) pieces of fuses, a NAND gate, resistance elements, and an output terminal. The decision unit decides whether n or more pieces (m?n?2) of fuses are disconnected out of the m pieces of fuses included in the signal output unit, and outputs the result of a decision. When m=n=2, the decision unit is constituted of a NOR gate having two input terminals connected to a respective end of the fuses. Thus, a H-level potential signal is output at an output terminal of the NOR gate when the decision result is affirmative. On the other hand, when the decision result is negative, a L-level potential signal is output at the output terminal.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: June 11, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroaki Ohkubo, Yasutaka Nakashiba
  • Patent number: 8461012
    Abstract: A method for forming a semiconductor structure includes forming an isolation region in a semiconductor substrate; forming a conductive layer over the isolation region; forming a first dielectric layer over the conductive layer; forming a plurality of conductive vias extending through the first dielectric layer to the conductive layer and electrically contacting the conductive layer; forming a second dielectric layer over the first dielectric layer; and forming a conductive ground plane in the second dielectric layer. Each of the plurality of conductive vias is in electrical contact with the conductive ground plane, and the conductive ground plane includes an opening, wherein the opening is located directly over the conductive layer. At least one interconnect layer may be formed over the second dielectric layer and may include a transmission line which transmits a signal having a frequency of at least 30 gigahertz.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: June 11, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Vishal P. Trivedi
  • Patent number: 8456221
    Abstract: A voltage operation system includes: a power on reset circuit, a voltage detecting circuit, an operating signal generating circuit, and an electronic fuse circuit. The power on reset circuit is used for generating a power on reset signal. The voltage detecting circuit detects an operating voltage to output a voltage detecting signal. The operating signal generating circuit, coupled to the power on reset circuit and the voltage detecting circuit-outputs an operating signal. The electronic fuse circuit can be fused according to a lock signal, a fuse signal, and the operating signal.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: June 4, 2013
    Assignee: Realtek Semiconductor Corp.
    Inventor: Kai-Yin Liu
  • Publication number: 20130135034
    Abstract: A semiconductor integrated circuit includes a fuse connected between a first node and a second node, a first driver configured to pull down a voltage of the first node in an initialization period in response to a fuse sensing signal, a second driver configured to pull up a voltage of the second node in an initial period of a fuse sensing period in response to the fuse sensing signal, a sensor configured to determine whether the fuse is blown or not in response to a voltage of the first node, and a third driver configured to drive the second node to a voltage level lower than a pull-up voltage level of the second driver after the initial period of the fuse sensing period in response to an output signal of the sensor and the fuse sensing signal.
    Type: Application
    Filed: December 27, 2011
    Publication date: May 30, 2013
    Inventor: Young-Han JEONG
  • Publication number: 20130135035
    Abstract: An anti-fuse control circuit includes a first power supply voltage application unit, a second power supply voltage application unit and a control unit. The first power supply voltage application unit configured to selectively apply first power supply voltage to an output node in response to a power up signal. The second power supply voltage application unit configured to selectively apply second power supply voltage to the output node in response to a program signal. The control unit configured to control a connection between the output node and an anti-fuse in response to the power up signal when the program signal is inactivated.
    Type: Application
    Filed: January 17, 2012
    Publication date: May 30, 2013
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Jung taek YOU
  • Publication number: 20130134297
    Abstract: A resistor array is provided in an element array. A mean value of a characteristic-value distribution is associated with a median of combined resistance values obtained by the element array. An array of trimming information pieces corresponding to combined resistance values larger than the median is set in a descending order of ‘15’ to ‘8’ in decimal number, and an array of trimming information pieces corresponding to combined resistance values less than the median is set in an ascending order of ‘0’ to ‘7’ in decimal number. A circuit converts trimming information derived from the trimming information generation circuit to generate element selection information for selecting turn-off resistors to obtain combined resistance values from the resistor array. Thus, the number of melted-and-cut fuses involved in generation of trimming information associated within the range of “mean value±2?” in the distribution is reduced.
    Type: Application
    Filed: November 21, 2012
    Publication date: May 30, 2013
    Inventors: Kazuo NODA, Takahiro INOUE
  • Patent number: 8446210
    Abstract: An electronic fuse system includes: a pad, an electronic fuse circuit, a first switch circuit, and a control circuit. The pad is used for receiving a reference voltage. The electronic fuse circuit is used for changing a voltage level when a current signal passes. The first switch circuit is coupled between the pad and the electronic fuse circuit, for controlling the first switch circuit to be disabled or enabled according to a switch control signal. The control circuit, coupled to the first switch circuit is for transferring the switch control signal according a control signal and a lock signal.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: May 21, 2013
    Assignee: Realtek Semiconductor Corp.
    Inventor: Kai-Yin Liu
  • Patent number: 8441306
    Abstract: This invention provides a poly fuse burning system comprising a poly fuse, a controllable power source supplying power for burning the poly fuse, and a monitor circuit monitoring the burning state of the poly fuse, wherein when a targeted burning state is reached, a control signal is output to shut down the controllable power source to stop the burning.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: May 14, 2013
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Jui-Lung Chen, Tien-Hui Huang, Chieh-Yao Chuang
  • Publication number: 20130106496
    Abstract: Electrically programmable fuses and methods for forming the same are shown that include forming a wire between a first pad and a second pad on a substrate, forming a blocking structure around a portion of the wire, and depositing a metal layer on the wire and first and second pads to form a metal compound, wherein the metal compound fully penetrates the portion of the wire within the blocking structure.
    Type: Application
    Filed: September 12, 2012
    Publication date: May 2, 2013
    Applicant: International Business Machines Corporation
    Inventors: Josephine B. Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight
  • Publication number: 20130106497
    Abstract: Many inventions are disclosed. Some aspects are directed to MEMS, and/or methods for use with and/or for fabricating MEMS, that supply, store, and/or trap charge on a mechanical structure disposed in a chamber. Various structures may be disposed in the chamber and employed in supplying, storing and/or trapping charge on the mechanical structure. In some aspects, a breakable link, a thermionic electron source and/or a movable mechanical structure are employed. The breakable link may comprise a fuse. In one embodiment, the movable mechanical structure is driven to resonate. In some aspects, the electrical charge enables a transducer to convert vibrational energy to electrical energy, which may be used to power circuit(s), device(s) and/or other purpose(s). In some aspects, the electrical charge is employed in changing the resonant frequency of a mechanical structure and/or generating an electrostatic force, which may be repulsive.
    Type: Application
    Filed: December 17, 2012
    Publication date: May 2, 2013
    Inventors: Markus Lutz, Aaron Partridge, Brian H. Stark
  • Patent number: 8432717
    Abstract: Provided is a semiconductor integrated circuit including: an anti-fuse element that electrically connects a first node and a first power supply terminal when data is written and electrically disconnect the first node and the first power supply terminal when data is not written; a first switch circuit that is connected between the first node and a first data line applied with a predetermine first voltage, and enters an off state from an on state according to a first control signal; and a detection part that detects write data of the anti-fuse element according to whether a voltage of the first node is substantially the same as the first voltage or substantially the same as a supply voltage of the first power supply terminal when the first switch circuit enters the off state.
    Type: Grant
    Filed: October 5, 2010
    Date of Patent: April 30, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroyuki Furukawa, Isao Naritake
  • Patent number: 8429471
    Abstract: An apparatus for precluding the use of extended JTAG operations, including a JTAG control chain, a feature fuse, a level sensor, an access controller, and a blow controller. The JTAG control chain enables/disables the extended JTAG operations. The feature fuse indicates whether the extended JTAG features are to be disabled. The level sensor monitors an external voltage signal, and indicates that the external voltage signal is at a legal level. The access controller determines if the feature fuse is blown, and directs the JTAG control chain to disable the extended JTAG operations if the feature fuse is blown, and directs the JTAG control chain to disable the extended JTAG operations if the external voltage signal is at an illegal level regardless of whether the feature fuse is blown. The blow controller receives a voltage, and blows a selected fuse within a fuse array responsive to a valve of the voltage.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: April 23, 2013
    Assignee: VIA Technologies, Inc.
    Inventors: G. Glenn Henry, Dinesh K. Jain
  • Publication number: 20130093502
    Abstract: Provided is an apparatus for generating a digital value that may generate a random digital value, and guarantee time invariance of the generated digital value. The apparatus may include a digital value generator to generate a random digital value using semiconductor process variation, and a digital value freezing unit that may be connected to the digital value generator and fixed to one of a first state and a second state based on the generated digital value, to freeze the digital value.
    Type: Application
    Filed: March 30, 2012
    Publication date: April 18, 2013
    Inventors: Tae Wook Kim, Dong Kyue Kim, Byong Deck Choi
  • Patent number: 8421520
    Abstract: A fuse circuit includes an electric fuse coupled to a first voltage source; a low resistance unit coupled to the electric fuse and having a junction which is capable of breaking down; and a switching unit coupled between the low resistance unit and a second voltage source.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: April 16, 2013
    Assignee: SK Hynix Inc.
    Inventor: Jun Gi Choi
  • Patent number: 8416012
    Abstract: A reference voltage generating circuit includes a first power supply, a second power supply, a first variable resistance circuit having one end connected to the first power supply and configured to be capable of adjusting a resistance value of the first variable resistance circuit, a series resistance circuit having at least one resistance and one end connected to the first variable resistance circuit, a second variable resistance circuit having one end connected to the series resistance circuit and the other end connected to the second power supply, and configured to be capable of adjusting a resistance value of the second variable resistance circuit, a first terminal arranged between the first variable resistance circuit and the series resistance circuit, a second terminal arranged between the series resistance circuit and the second variable resistance circuit, and a voltage selecting circuit configured to select one of a voltage of the first terminal and a voltage of the second terminal, and output the se
    Type: Grant
    Filed: January 18, 2011
    Date of Patent: April 9, 2013
    Assignee: Ricoh Company, Ltd.
    Inventor: Keiichi Ashida
  • Patent number: 8405448
    Abstract: An apparatus for programming a fuse includes a programmable branch comprising a fusable element and a reverse-biased diode connected in series. The programmable branch is connected in parallel with a current boost capacitor. An electrical source or input supplies a current that is sufficient to charge the current boost capacitor to a breakdown voltage of the reverse-biased diode and subsequently melt the reverse-biased diode. Melting the reverse-biased diode may induce a reduction in voltage across the current boost capacitor and result in a current surge through the programmable branch that is sufficient to program (i.e. blow) the fusable element. A corresponding method for programming a fuse is also disclosed.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: March 26, 2013
    Inventors: David R. Hall, Marshall Soares, Paul Moody
  • Publication number: 20130063202
    Abstract: An antifuse has first and second semiconductor regions having one conductivity type and a third semiconductor region therebetween having an opposite conductivity type. A conductive region contacting the first region has a long dimension in a second direction transverse to the direction of a long dimension of a gate. An antifuse anode is spaced apart from the first region in the second direction and a contact is connected with the second region. Applying a programming voltage between the anode and the contact with gate bias sufficient to fully turn on field effect transistor operation of the antifuse heats the first region to drive a dopant outwardly, causing an edge of the first region to move closer to an edge of the second region and reduce electrical resistance between the first and second regions by an one or more orders of magnitude.
    Type: Application
    Filed: September 13, 2012
    Publication date: March 14, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yan Zun Li, Chandrasekharan Kothandaraman, Dan Moy, Norman W. Robson, John M. Safran
  • Patent number: 8395439
    Abstract: An internal voltage adjusting circuit of a semiconductor memory device processes a period from activation to deactivation of a reset bar signal by dividing the period into a first period to a third period. In the first period, a peripheral circuit voltage is stabilized to a lowest value to suppress power consumption. In the second period in which a power source voltage is stabilized, the peripheral circuit voltage is set to a highest value to read out optimum internal voltage values from a fuse circuit in a stable manner. In the third period after reading out the optimum internal voltage values, the peripheral circuit voltage is returned to the lowest value to suppress the power consumption. When the reset bar signal is deactivated, the peripheral circuit voltage is set based on the optimum internal voltage values read out from the fuse circuit.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: March 12, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Kenji Yoshida
  • Patent number: 8384466
    Abstract: A semiconductor device includes an electric fuse circuit and a program protective circuit. The electric fuse circuit includes a fuse element and a transistor connected together in series and placed between a program power supply and a grounding, and controlling sections. The program protective circuit is placed in parallel with the electric fuse circuit and between the program power supply and the grounding. When a surge voltage is applied between the program power supply and the grounding, the foregoing structure allows a part of a surge electric current can flow through the program protective circuit.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: February 26, 2013
    Assignee: Panasonic Corporation
    Inventors: Toshiaki Kawasaki, Yasuhiro Agata, Masanori Shirahama, Toshihiro Kougami, Katsuya Arai
  • Patent number: 8368456
    Abstract: A fuse circuit includes a fuse information signal generation unit and an output driving unit. The fuse information signal generation unit is configured to precharge a fuse information signal in response to a precharge signal and drive the fuse information signal in response to a selection signal capable of cutting a fuse. The output driving unit configured to equally maintain potentials at both terminals of the fuse in response to a control signal.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: February 5, 2013
    Assignee: SK Hynix Inc.
    Inventor: Keun Kook Kim
  • Patent number: 8358555
    Abstract: A fuse circuit includes a plurality of fuse sets configured to perform fuse programming and generate fuse signals in response to fuse programming signals and a fuse control unit configured to generate the fuse programming signals depending upon a level of a programming voltage.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: January 22, 2013
    Assignee: SK Hynix Inc.
    Inventors: Jin Youp Cha, Jae Jin Lee
  • Patent number: 8349665
    Abstract: A fuse device includes a fuse unit, which includes a cathode, an anode, and a fuse link coupling the cathode and the anode. A transistor includes at least a portion of the fuse unit to be used as an element of the transistor.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: January 8, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Deok-kee Kim
  • Patent number: 8344456
    Abstract: An ESD protection circuit including a first electrostatic discharge protection circuit provided between first power supply wiring and first ground wiring; a second ESD protection circuit provided between second power supply wiring and second ground wiring; a third ESD protection circuit provided between the first ground wiring and the second ground wiring; a PMOS transistor coupled to the first power supply wiring and provided between a first CMOS circuit coupled to the first ground wiring and the first power supply wiring, the first CMOS circuit receiving a signal from a first internal circuit and outputting a signal to a first node; an NMOS transistor provided between the first node and the first ground wiring; and an ESD detection circuit that renders the PMOS transistor conductive and the NMOS transistor non-conductive during normal operation, and renders the PMOS transistor non-conductive and the NMOS transistor conductive when an ESD is applied.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: January 1, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Masahito Arakawa, Toshihiko Mori
  • Patent number: 8341472
    Abstract: An apparatus in an integrated circuit for precluding the use of extended JTAG operations. The apparatus has a JTAG control chain, a feature fuse, a level sensor, and an access controller. The JTAG control chain is configured to enable/disable the extended JTAG operations. The feature fuse is configured to indicate whether the extended JTAG features are to be disabled. The level sensor is configured to monitor an external voltage signal, and configured to indicate that the external voltage signal is at an illegal level. The access controller is coupled to the feature fuse, the level sensor, and the JTAG control chain, and is configured to determine if the feature fuse is blown, and is configured to direct the JTAG control chain to disable the extended JTAG operations if the external voltage signal is at an illegal level regardless of whether the feature fuse is blown.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: December 25, 2012
    Assignee: VIA Technologies, Inc.
    Inventors: G. Glenn Henry, Dinesh K. Jain
  • Patent number: 8339182
    Abstract: A semiconductor device includes a signal output unit, and a decision unit. The signal output unit includes m (?2) pieces of fuses, a NAND gate, resistance elements, and an output terminal. The decision unit decides whether n or more pieces (m?n?2) of fuses are disconnected out of the m pieces of fuses included in the signal output unit, and outputs the result of a decision. When m=n=2, the decision unit is constituted of a NOR gate having two input terminals connected to a respective end of the fuses. Thus, a H-level potential signal is output at an output terminal of the NOR gate when the decision result is affirmative. On the other hand, when the decision result is negative, a L-level potential signal is output at the output terminal.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: December 25, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroaki Ohkubo, Yasutaka Nakashiba
  • Publication number: 20120313690
    Abstract: An apparatus for programming a fuse includes a programmable branch comprising a fusable element and a reverse-biased diode connected in series. The programmable branch is connected in parallel with a current boost capacitor. An electrical source or input supplies a current that is sufficient to charge the current boost capacitor to a breakdown voltage of the reverse-biased diode and subsequently melt the reverse-biased diode. Melting the reverse-biased diode may induce a reduction in voltage across the current boost capacitor and result in a current surge through the programmable branch that is sufficient to program (i.e. blow) the fusable element. A corresponding method for programming a fuse is also disclosed.
    Type: Application
    Filed: September 13, 2011
    Publication date: December 13, 2012
    Inventors: David R. Hall, Marshall Soares, Paul Moody
  • Patent number: 8330527
    Abstract: Various embodiments of a fuse circuit of a semiconductor apparatus are disclosed. In one exemplary embodiment, the fuse circuit may include a fuse whose electrical connection state can be changed by an electrical stress applied thereto and a plurality of self boosting units configured to perform self boosting operations under the control of a rupture enable signal. The self boosting units may also be configured to generate stress voltages and supply the generated stress voltages to the fuse. The fuse circuit may also include a precharge unit configured to supply a precharge voltage to the fuse in response to a precharge signal and a cross-coupled latching amplification unit configured to sense a change in a voltage level of the precharge voltage supplied to the fuse, with reference to a reference voltage, and output a fuse state signal.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: December 11, 2012
    Assignee: SK Hynix Inc.
    Inventor: Hong Gyeom Kim
  • Patent number: 8324958
    Abstract: In one embodiment, a redundancy circuit may include a comparison unit configured to record a first repair address through fuse cutting, compare a comparison address with the first repair address, and output a comparison result signal; a first fuse enable unit configured to output a first fuse enable signal for repairing the first repair address; a second fuse enable unit configured to output a second fuse enable signal for repairing a second repair address; a first determination unit configured to output a first repair determination signal in response to receipt of the first fuse enable signal and the comparison result signal; and a second determination unit configured to output a second repair determination signal in response to receipt of an inverted signal of a value of the comparison result signal corresponding to the certain bit, remaining bits, and the second fuse enable signal.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: December 4, 2012
    Assignee: SK Hynix Inc.
    Inventor: Ki Hoon Lee
  • Publication number: 20120299630
    Abstract: Provided are a trimming circuit which does not need a dedicated terminal to which a current for cutting a fuse is input, and also a semiconductor device including the trimming circuit. The trimming circuit includes: an input terminal connected to a pad which is an external terminal of an internal circuit; a fuse provided between a power supply terminal and an output terminal; and a diode provided between the input terminal and the output terminal. The trimming circuit performs trimming by applying, to the pad, such a voltage that the diode is biased in the forward direction.
    Type: Application
    Filed: May 18, 2012
    Publication date: November 29, 2012
    Inventors: Atsushi Sakurai, Kazuaki Sano, Fumihiko Maetani, Satoshi Abe
  • Publication number: 20120299640
    Abstract: Integrated circuit die stacks having a first die mounted upon a substrate, the first die manufactured to be initially identical to a second die with a plurality of through silicon vias (‘TSVs’), the first die personalized by blowing fuses on the first die, converting the TSVs previously connected through the blown fuses into pass-through vias (‘PTVs’), each PTV implementing a conductive pathway through the first die with no connection to any circuitry on the first die; and the second die, manufactured to be initially identical to the first die and later personalized by blowing fuses on the second die, the second die mounted upon the first die so that the PTVs in the first die connect signal lines from the substrate through the first die to TSVs in the second die.
    Type: Application
    Filed: August 8, 2012
    Publication date: November 29, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jimmy G. Foster, SR., Kyu-Hyoun Kim
  • Publication number: 20120299639
    Abstract: A highly reliable trimming circuit is provided. A rewritable trimming circuit is provided. A method for driving a highly reliable trimming circuit is provided. A method for driving a rewritable trimming circuit is provided. The trimming circuit includes a storage node connected to a source electrode or a drain electrode of a transistor whose off-state leakage current is extremely low and a transistor whose gate electrode is connected to the storage node. The trimming state of an element or a circuit connected in parallel to a source electrode and a drain electrode of the transistor whose gate electrode is connected to the storage node is controlled using the transistor whose off-state leakage current is extremely low.
    Type: Application
    Filed: May 22, 2012
    Publication date: November 29, 2012
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Makoto Kaneyasu
  • Publication number: 20120293241
    Abstract: An electronic trimming circuit carries out a trimming operation on portions of an integrated device. The circuit includes N trimmable interconnected resistances, each connected in parallel to a respective shunt fuse. N trimming transistors are each connected to a respective one of the shunt fuses to force therethrough substantially the whole current flowing in the respective trimming transistor. N bias networks are each functionally connected to a control terminal of a respective one of the trimming transistors to directly bias an active junction thereof. An externally driven heating device is thermally coupled with the active junctions of the trimming transistors adapted to raise the temperature thereof.
    Type: Application
    Filed: May 14, 2012
    Publication date: November 22, 2012
    Applicant: STMicroelectronics S.r.l.
    Inventors: Giuseppe SCILLA, Francesco Distefano
  • Publication number: 20120286849
    Abstract: A semiconductor apparatus includes: a plurality of electrical fuses; a rupture unit configured to rupture an electrical fuse in response to rupture information applicable to the plurality of electrical fuses, when a rupture enable signal is activated; a scan unit configured to output information on whether an each of the plurality of electrical fuses are ruptured or not, as scan information, when a scan enable signal is activated; and a shift register unit configured to receive an input signal in synchronization with a clock signal and store the input signal as the rupture information, and configured to receive the scan information and output the scan information as an output signal in synchronization with the clock signal.
    Type: Application
    Filed: May 10, 2012
    Publication date: November 15, 2012
    Applicant: SK hynix Inc.
    Inventors: Tae Yong LEE, Sang Hoon SHIN
  • Publication number: 20120286848
    Abstract: The trimming circuit includes a plurality of trimmable resistances that may be coupled among them, each resistance being connected in parallel to a respective fuse. The trimming circuit allows burning any number of fuses according to a fixed trimming sequence using only one or two dedicated pins because it includes an input diode-connected transistor and a plurality of trimming transistors of different sectional area, each connected to force current throughout a respective one of the shunt fuses and coupled to the input diode-connected transistor such to mirror the current flowing therethrough. The fuses of the trimming circuit may be burnt by applying a trimming voltage to the diode-connected input transistor with a voltage generator connected between a dedicated pin of the circuit and a terminal at a reference potential, such to force a current therethrough as long as the mirrored currents flowing throughout the fuses burn them.
    Type: Application
    Filed: May 10, 2012
    Publication date: November 15, 2012
    Applicant: STMicroelectronics S.r.I.
    Inventors: Giuseppe SCILLA, Francesco Distefano
  • Publication number: 20120274391
    Abstract: A fuse circuit of a semiconductor device includes a transfer unit configured to selectively transfer a corresponding address signal in response to a first test mode signal, a fuse control unit configured to drive an output end with a first voltage in response to an output signal of the transfer unit, a fuse unit including a MOS transistor having a gate coupled to the output end, and a fuse enable unit configured to selectively supply a second voltage to a source/drain of the MOS transistor of the fuse unit in response to the first test mode signal, wherein the fuse circuit is programmed by causing a breakdown of the MOS transistor in response to a voltage difference between the first voltage and the second voltage that are applied to the gate and the source/drain of the MOS transistor of the fuse unit.
    Type: Application
    Filed: December 20, 2011
    Publication date: November 1, 2012
    Inventor: Jong-Su Kim
  • Patent number: 8299845
    Abstract: A semiconductor device includes a first circuit, a second circuit, and a first voltage dividing circuit. The first circuit is coupled to a first terminal. The first circuit is operable by a first voltage supplied from the first terminal. The second circuit is coupled through a first resistive element to the first terminal. The second circuit is operable by a second voltage supplied through the first resistive element from the first terminal. The second voltage is smaller in absolute value than the first voltage. The first voltage dividing circuit is coupled to a first node between the first resistive element and the second circuit. The first voltage dividing circuit has a conductive state and a non-conductive state. The first voltage dividing circuit is kept in the conductive state while applying the first voltage to the first terminal to allow the first circuit to operate by the first voltage.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: October 30, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Toru Ishikawa
  • Publication number: 20120268195
    Abstract: A method and an eFuse circuit for implementing with enhanced eFuse blow operation without requiring a separate high current and high voltage supply to blow the eFuse, and a design structure on which the subject circuit resides are provided. The eFuse circuit includes an eFuse connected to a field effect transistor (FET) operatively controlled during a sense mode and a blow mode for sensing and blowing the eFuse. The eFuse circuit is placed over an independently voltage controlled silicon region. During a sense mode, the independently voltage controlled silicon region is grounded providing an increased threshold voltage of the FET. During a blow mode, the independently voltage controlled silicon region is charged to a voltage supply potential. The threshold voltage of the FET is reduced by the charged independently voltage controlled silicon region for providing enhanced FET blow function.
    Type: Application
    Filed: April 21, 2011
    Publication date: October 25, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann, Kelly L. Williams
  • Patent number: 8294475
    Abstract: A circuit arrangement including a fuse comprises a fuse path (SP) which is coupled to a control input (SE) and comprises the fuse (RS) and a first charge reservoir (C1) serially connected thereto for providing a first charge state (L1), a reference path (RP) which is coupled to the control input (SE) and comprises a comparison element (RV) and a second charge reservoir (C2) serially connected thereto for providing a second charge state (L2), and an evaluation unit (AE) comprising a first input (E1) connected to the fuse path (SP) in a switchable manner, a second input (E2) connected to the reference path (RP) in a switchable manner, and a data output (DA) for providing a condition of the fuse (RS) depending on a difference between the first and second charge states (L1, L2). Further, a method for determining the condition of a fuse is provided.
    Type: Grant
    Filed: September 24, 2009
    Date of Patent: October 23, 2012
    Assignee: Austriamicrosystems AG
    Inventor: Johannes Fellner
  • Publication number: 20120262223
    Abstract: A semiconductor device includes a signal output unit, and a decision unit. The signal output unit includes m (?2) pieces of fuses, a NAND gate, resistance elements, and an output terminal. The decision unit decides whether n or more pieces (m?n?2) of fuses are disconnected out of the m pieces of fuses included in the signal output unit, and outputs the result of a decision. When m=n=2, the decision unit is constituted of a NOR gate having two input terminals connected to a respective end of the fuses. Thus, a H-level potential signal is output at an output terminal of the NOR gate when the decision result is affirmative. On the other hand, when the decision result is negative, a L-level potential signal is output at the output terminal.
    Type: Application
    Filed: June 21, 2012
    Publication date: October 18, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroaki OHKUBO, Yasutaka NAKASHIBA
  • Patent number: 8289070
    Abstract: A fuse circuit comprises a fuse set and an enable circuit. The enable circuit is configured to receive a test mode enable signal and a power up signal to generate an enable signal and a voltage level to the fuse set for indicating whether an external supply voltage reaches a predetermined value and whether a test mode is enabled. In particular, an output signal of the fuse set is constant in the test mode, regardless of whether a fuse in the fuse set is blown or not.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: October 16, 2012
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventor: Pei-Jey Huang
  • Publication number: 20120249160
    Abstract: After planarization of a gate level dielectric layer, a dummy structure is removed to form a recess. A first conductive material layer and an amorphous metal oxide are deposited into the recess area. A second conduct material layer fills the recess. After planarization, an electrical antifuse is formed within the filled recess area, which includes a first conductive material portion, an amorphous metal oxide portion, and a second conductive material portion. To program the electrical antifuse, current is passed between the two terminals in the pair of the conductive contacts to transform the amorphous metal oxide portion into a crystallized metal oxide portion, which has a lower resistance. A sensing circuit determines whether the metal oxide portion is in an amorphous state (high resistance state) or in a crystalline state (low resistance state).
    Type: Application
    Filed: June 14, 2012
    Publication date: October 4, 2012
    Applicants: FREESCALE SEMICONDUCTOR, INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Satya N. Chakravarti, Dechao Guo, Chuck T. Le, Byoung W. Min, Rajeevakumar V. Thekkemadathil, Keith Kwong Hon Wong
  • Publication number: 20120249221
    Abstract: A semiconductor integrated circuit includes a fuse set; a terminal assigned to be applied with a first external signal in a normal operation; and a control unit configured to receive a second external signal through the terminal and apply the received second external signal to the fuse set in a fuse control operation.
    Type: Application
    Filed: August 27, 2011
    Publication date: October 4, 2012
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Sang Mook OH, Jae Hyuk IM
  • Publication number: 20120249220
    Abstract: A trim circuit for a power supply controller includes: a control circuit; at least a capacitance type programmable circuit connection; and a switching circuit, under control of the control circuit, the switching circuit selectively coupling the capacitance type programmable circuit connection to anyone of an operation voltage and a programming voltage, for determining a programming state of the capacitance type programmable circuit connection.
    Type: Application
    Filed: March 28, 2011
    Publication date: October 4, 2012
    Applicant: SYSTEM GENERAL CORP.
    Inventors: Rui-Hong Lu, Han-Chung Tai, Hsin-Chih Chiang
  • Patent number: 8278990
    Abstract: An electric fuse cutoff control circuit controlling cutoff of a plurality of electric fuses including: a cutoff information storage circuit adapted to store cutoff information about whether or not each of the plurality of electric fuses is cut off; a cutoff information control circuit controlling the cutoff of the plurality of electric fuses based on an output signal of the cutoff information storage circuit; and a cutoff information renewal circuit receiving an output signal of the cutoff information control circuit and renewing the cutoff information set for the cutoff information storage circuit.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: October 2, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Tatsuru Matsuo
  • Patent number: 8280672
    Abstract: A trimming circuit for a semiconductor memory apparatus includes a trimming code generator configured to provide a trimming code signal group by performing one of addition and subtraction using a test mode signal and a fuse coding signal, and an internal voltage generator configured to provide trimmed voltage in response to the trimming code signal group as output voltage.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: October 2, 2012
    Assignee: SK hynix Inc.
    Inventor: Jee-Yul Kim
  • Patent number: 8274321
    Abstract: A fuse circuit includes a control signal generation unit configured to generate a control signal that is enabled after a moment when a power-up signal is enabled, a potential control unit configured to control potentials of both ends of a fuse in response to the control signal, and a fuse output unit configured to be initialized in response to the power-up signal and output a fuse signal in response to whether the fuse is cut or not.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: September 25, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sung-Soo Chi, Ki-Chang Kwean, Woo-Young Lee