Abstract: An anti-fuse control circuit includes a first power supply voltage application unit, a second power supply voltage application unit and a control unit. The first power supply voltage application unit configured to selectively apply first power supply voltage to an output node in response to a power up signal. The second power supply voltage application unit configured to selectively apply second power supply voltage to the output node in response to a program signal. The control unit configured to control a connection between the output node and an anti-fuse in response to the power up signal when the program signal is inactivated.

Abstract: A semiconductor structure including a device configured to receive an input data-word. The device including a logic structure configured to generate an encrypted data-word by encrypting the input data-word through an encrypting operation. The device further including an eFuse storage device configured to store the encrypted data-word as eFuse data by blowing fuses in accordance with the encrypted data-word.

Abstract: A semiconductor integrated circuit includes a fuse set; a terminal assigned to be applied with a first external signal in a normal operation; and a control unit configured to receive a second external signal through the terminal and apply the received second external signal to the fuse set in a fuse control operation.

Abstract: An anti-fuse circuit includes: a rupture unit including an anti-fuse programmed in response to an input rupture signal during a program mode, and configured to generate an output rupture signal corresponding to a state of the anti-fuse to output the generated output rupture signal to a transmission node, a voltage clamp unit configured to generate a clamp voltage proportional to an external voltage level to generate the clamp voltage having a constant voltage level when the external voltage level rises to a predetermined level or more, and a fuse signal generation unit configured to reset the transmission node to the clamp voltage at the initial stage of the program mode to generate a fuse signal in response to the voltage level of the transmission node during an output mode.

Abstract: An integrated circuit includes active circuitry disposed at a surface of a semiconductor body and an interconnect region disposed above the semiconductor body. A thermoelectric material is disposed in an upper portion of the interconnect region away from the semiconductor body. The thermoelectric material is configured to deliver electrical energy when exposed to a temperature gradient. This material can be used, for example, in a method for detecting the repackaging of the integrated circuit after it has been originally packaged.

Abstract: A voltage divider circuit generating a divided voltage by dividing an input voltage with a predetermined voltage division ratio, and outputting the divided voltage is disclosed. The voltage divider circuit includes a first resistor circuit including multiple resistors connected in series, the resistors being connected in parallel to corresponding fuses; and a second resistor circuit including multiple resistors connected in series, the resistors being connected in parallel to corresponding fuses, the second resistor circuit being connected in series to the first resistor circuit. The divided voltage is output from the connection of the first resistor circuit and the second resistor circuit, and the fuses of the first resistor circuit and the second resistor circuit are subjected to trimming so that the combined resistance of the first resistor circuit and the second resistor circuit is constant.

Abstract: A semiconductor apparatus may include a transmission control signal generation unit, a fuse signal transmission unit, a reception control signal generation unit and a fuse signal reception unit. The transmission control signal generation unit receives a clock signal and generates a plurality of divided clock signals based on the clock signal to output transmission control signals from the plurality of divided clock signals. The fuse signal transmission unit transmits fuse information in synchronization with the transmission control signals. The reception control signal generation unit receives the clock signal and generates the plurality of divided clock signals, and generates reception control signals based on the plurality of divided clock signals. The fuse signal reception unit receives the fuse information in synchronization with the reception control signals.

Abstract: A semiconductor integrated circuit includes a command generating unit configured to generate a plurality of second commands in response to a first command, each second command for indicating an operation sections of a corresponding anti-fuse circuit, and a plurality of anti-fuse circuits, each comprising an anti-fuse and configured to receives a corresponding second command and perform a rupture operation of the anti-fuse in response to the received corresponding second command.

Abstract: An antifuse has first and second semiconductor regions having one conductivity type and a third semiconductor region therebetween having an opposite conductivity type. A conductive region contacting the first region has a long dimension in a second direction transverse to the direction of a long dimension of a gate. An antifuse anode is spaced apart from the first region in the second direction and a contact is connected with the second region. Applying a programming voltage between the anode and the contact with gate bias sufficient to fully turn on field effect transistor operation of the antifuse heats the first region to drive a dopant outwardly, causing an edge of the first region to move closer to an edge of the second region and reduce electrical resistance between the first and second regions by an one or more orders of magnitude.

Abstract: An anti-fuse circuit includes: an anti-fuse unit including an anti-fuse capable of being programmed in response to a rupture signal and configured to generate a fuse signal corresponding to a state of the anti-fuse; a dummy fuse unit including a dummy fuse and configured to generate a dummy fuse signal corresponding to a state of the dummy fuse; and a blocking unit configured to output the fuse signal as a fuse output signal in response to a state of the dummy fuse signal.

Abstract: A semiconductor device includes: a first driving voltage generation unit configured to generate a first driving voltage; a fuse unit coupled between an output node for receiving the first driving voltage and a fuse state sensing node; a driving unit configured to drive the fuse state sensing node with a second driving voltage in response to a control signal; a voltage level control unit configured to generate a voltage level control signal in response to a fuse state sensing signal that corresponds to a voltage level of the fuse state sensing node; and a second driving voltage generation unit configured to control and output a voltage level of the second driving voltage in response to the voltage level control signal. The semiconductor device repeatedly performs a rupture operation by monitoring a fuse state sensing signal.

Abstract: Motor drives, signal conditioning systems and configurable circuit boards are presented in which diode blocking circuits are provided for contemporaneous opening of programming fuses in multiple programmable impedance circuits using a single configuration input signal during manufacturing and for mitigating interference between impedance circuits during system operation.

Abstract: Circuitry includes a pre-amplifier having a differential output, where the differential output corresponds to a common mode voltage; a multiplexer including sets of transistors, each of which has a control input; a comparator including input terminals, a first terminal of the input terminals to receive a signal that is based on an output of the multiplexer, and a second terminal of the input terminals to receive a threshold voltage; a compensation circuit to produce a divided voltage that varies in accordance with variations in the common mode voltage; and an amplifier to receive a predefined voltage and to use the divided voltage to affect the predefined voltage to produce the threshold voltage for the comparator. Signals in the differential output of the pre-amplifier are applicable to corresponding control inputs in the sets of transistors.

Abstract: An electronic trimming circuit carries out a trimming operation on portions of an integrated device. The circuit includes N trimmable interconnected resistances, each connected in parallel to a respective shunt fuse. N trimming transistors are each connected to a respective one of the shunt fuses to force therethrough substantially the whole current flowing in the respective trimming transistor. N bias networks are each functionally connected to a control terminal of a respective one of the trimming transistors to directly bias an active junction thereof. An externally driven heating device is thermally coupled with the active junctions of the trimming transistors adapted to raise the temperature thereof.

Abstract: Such a device is disclosed that includes a first ladder fuse for which blowing points are arranged at a first coordinate and a second ladder fuse for which blowing points are arranged at a second coordinate. When adjustment data for adjusting circuit characteristics is within a first range, a trimming operation is performed on both the first and second ladder fuses, and when the adjustment data for adjusting the circuit characteristics is within a second range, the trimming operation is performed on the second ladder fuse without performing the trimming operation on the first ladder fuse. This configuration eliminates a necessity of irradiation on the first ladder fuse with a laser when the adjustment data is within the second range.

Abstract: A power device possesses a built-in fuse function and can continue to normally operate after a short circuit failure. The power device includes a plurality of output cells, a plurality of bonding wires provided corresponding to the output cells, and a control terminal driving circuit. Each of the output cells includes an output transistor. First side electrodes of the output transistors are commonly coupled to a first power source. Each of second side electrodes of the output transistors is coupled to an output terminal through the corresponding bonding wire. The control terminal driving circuit supplies a drive signal to the control terminals of the individual output transistors to control the output transistors. Each of the bonding wires is designed to be fused and cut if the output transistor included in the corresponding output cell fails and is shorted.

Abstract: A semiconductor integrated circuit includes a fuse connected between a first node and a second node, a first driver configured to pull down a voltage of the first node in an initialization period in response to a fuse sensing signal, a second driver configured to pull up a voltage of the second node in an initial period of a fuse sensing period in response to the fuse sensing signal, a sensor configured to determine whether the fuse is blown or not in response to a voltage of the first node, and a third driver configured to drive the second node to a voltage level lower than a pull-up voltage level of the second driver after the initial period of the fuse sensing period in response to an output signal of the sensor and the fuse sensing signal.

Abstract: A tamper resistant electronic device includes multiple eFuses that are individually blown in each instance the electronic device is tampered with. For example an eFuse is blown when the electronic device is subjected to a temperature that causes solder reflow. Since it is anticipated that the electronic device may be tampered with in an acceptable way and/or an acceptable number of instances, functionality of the electronic device is altered or disabled only after a threshold number of eFuses are blown. In certain implementations, the threshold number is the number of anticipated acceptable tamper events. Upon a tamper event an individual eFuse is blown. If the total number of blown eFuses is less than the threshold, a next eFuse is enabled so that it may be blown upon a next tamper event.

Abstract: A BEOL e-fuse is disclosed which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The BEOL e-fuse can be formed utilizing a line first dual damascene process to create a sub-lithographic via to be the programmable link of the e-fuse. The sub-lithographic via can be patterned using standard lithography and the cross section of the via can be tuned to match the target programming current.

Abstract: An anti-fuse circuit includes: a first fuse unit including a first anti-fuse which is determined to be short-circuited if the first anti-fuse in a programmed state and determined not to be short-circuited if the first anti-fuse in a non-programmed state, and configured to generate an output signal according to a state of the anti-fuse and a restoration signal; and a second fuse unit including a second anti-fuse, and configured to activate the restoration signal when the second anti-fuse is in the programmed state in case where the first anti-fuse is in the programmed state.

Abstract: A fuse circuit includes a data line, a plurality of fuse cells selectively programmed and electrically connected with the data line in response to respective selection signals, a dummy fuse cell electrically connected with the data line in response to a test signal, and a sense amplifier configured to sense a data of the data line. The fuse circuit includes a plurality of fuses, reduces the area thereof, and easily detects whether a sense amplifier operates properly or not in the fuse circuit.

Abstract: An anti-fuse circuit includes a control block configured to generate a first control signal and a second control signal in response to a first test signal and a second test signal, and a fuse set block configured to perform a primary fuse rupture operation in response to the first control signal and to perform a secondary fuse rupture operation in response to the second control signal, the fuse set block activating a fuse signal if any one of the primary fuse rupture operation and the secondary fuse rupture operation succeeds.

Abstract: An integrated circuit, wherein a voltage-adjustable power supply circuit (42) receives a first power supply control signal (6) output by a programming power supply control circuit (41), outputs a first voltage signal to a efuse circuit (44) by a power source switching circuit (43) and outputs the first voltage signal to other functional circuits (45) of the integrated circuit, and the efuse circuit (44) receives the first voltage signal and a first programming control signal (5) output by the programming power supply control circuit (41) and burns out a corresponding efuse therein; or the voltage adjustable power supply circuit (42) receives a second power supply control signal (6) output by the programming power supply control circuit (41) and outputs a second voltage signal to other functional circuits (45) of the integrated circuit, and the efuse circuit (44) receives a second programming control signal (5) output by the programming power supply control circuit (41) and ensures a corresponding efuse therei

Abstract: A fuse circuit includes a programming fuse signal generation block configured to generate parity signals, logic levels of which are determined according to addresses selected among a plurality of addresses with a programming enable signal enabled, and generate programming fuse signals which are programmed in response to the programming enable signal, the plurality of addresses and the parity signals; a corrected pulse generation block configured to correct an error included in the programming fuse signals and generate corrected pulses; and a fuse unit configured to generate fuse signals which are reprogrammed according to the corrected pulses.

Abstract: A method for forming a semiconductor structure includes forming an isolation region in a semiconductor substrate; forming a conductive layer over the isolation region; forming a first dielectric layer over the conductive layer; forming a plurality of conductive vias extending through the first dielectric layer to the conductive layer and electrically contacting the conductive layer; forming a second dielectric layer over the first dielectric layer; and forming a conductive ground plane in the second dielectric layer. Each of the plurality of conductive vias is in electrical contact with the conductive ground plane, and the conductive ground plane includes an opening, wherein the opening is located directly over the conductive layer. At least one interconnect layer may be formed over the second dielectric layer and may include a transmission line which transmits a signal having a frequency of at least 30 gigahertz.

Abstract: A semiconductor device includes a signal output unit, and a decision unit. The signal output unit includes m (?2) pieces of fuses, a NAND gate, resistance elements, and an output terminal. The decision unit decides whether n or more pieces (m?n?2) of fuses are disconnected out of the m pieces of fuses included in the signal output unit, and outputs the result of a decision. When m=n=2, the decision unit is constituted of a NOR gate having two input terminals connected to a respective end of the fuses. Thus, a H-level potential signal is output at an output terminal of the NOR gate when the decision result is affirmative. On the other hand, when the decision result is negative, a L-level potential signal is output at the output terminal.

Abstract: A voltage operation system includes: a power on reset circuit, a voltage detecting circuit, an operating signal generating circuit, and an electronic fuse circuit. The power on reset circuit is used for generating a power on reset signal. The voltage detecting circuit detects an operating voltage to output a voltage detecting signal. The operating signal generating circuit, coupled to the power on reset circuit and the voltage detecting circuit-outputs an operating signal. The electronic fuse circuit can be fused according to a lock signal, a fuse signal, and the operating signal.

Abstract: A resistor array is provided in an element array. A mean value of a characteristic-value distribution is associated with a median of combined resistance values obtained by the element array. An array of trimming information pieces corresponding to combined resistance values larger than the median is set in a descending order of ‘15’ to ‘8’ in decimal number, and an array of trimming information pieces corresponding to combined resistance values less than the median is set in an ascending order of ‘0’ to ‘7’ in decimal number. A circuit converts trimming information derived from the trimming information generation circuit to generate element selection information for selecting turn-off resistors to obtain combined resistance values from the resistor array. Thus, the number of melted-and-cut fuses involved in generation of trimming information associated within the range of “mean value±2?” in the distribution is reduced.

Abstract: A semiconductor integrated circuit includes a fuse connected between a first node and a second node, a first driver configured to pull down a voltage of the first node in an initialization period in response to a fuse sensing signal, a second driver configured to pull up a voltage of the second node in an initial period of a fuse sensing period in response to the fuse sensing signal, a sensor configured to determine whether the fuse is blown or not in response to a voltage of the first node, and a third driver configured to drive the second node to a voltage level lower than a pull-up voltage level of the second driver after the initial period of the fuse sensing period in response to an output signal of the sensor and the fuse sensing signal.

Abstract: An anti-fuse control circuit includes a first power supply voltage application unit, a second power supply voltage application unit and a control unit. The first power supply voltage application unit configured to selectively apply first power supply voltage to an output node in response to a power up signal. The second power supply voltage application unit configured to selectively apply second power supply voltage to the output node in response to a program signal. The control unit configured to control a connection between the output node and an anti-fuse in response to the power up signal when the program signal is inactivated.

Abstract: An electronic fuse system includes: a pad, an electronic fuse circuit, a first switch circuit, and a control circuit. The pad is used for receiving a reference voltage. The electronic fuse circuit is used for changing a voltage level when a current signal passes. The first switch circuit is coupled between the pad and the electronic fuse circuit, for controlling the first switch circuit to be disabled or enabled according to a switch control signal. The control circuit, coupled to the first switch circuit is for transferring the switch control signal according a control signal and a lock signal.

Abstract: This invention provides a poly fuse burning system comprising a poly fuse, a controllable power source supplying power for burning the poly fuse, and a monitor circuit monitoring the burning state of the poly fuse, wherein when a targeted burning state is reached, a control signal is output to shut down the controllable power source to stop the burning.

Abstract: Electrically programmable fuses and methods for forming the same are shown that include forming a wire between a first pad and a second pad on a substrate, forming a blocking structure around a portion of the wire, and depositing a metal layer on the wire and first and second pads to form a metal compound, wherein the metal compound fully penetrates the portion of the wire within the blocking structure.

Abstract: Many inventions are disclosed. Some aspects are directed to MEMS, and/or methods for use with and/or for fabricating MEMS, that supply, store, and/or trap charge on a mechanical structure disposed in a chamber. Various structures may be disposed in the chamber and employed in supplying, storing and/or trapping charge on the mechanical structure. In some aspects, a breakable link, a thermionic electron source and/or a movable mechanical structure are employed. The breakable link may comprise a fuse. In one embodiment, the movable mechanical structure is driven to resonate. In some aspects, the electrical charge enables a transducer to convert vibrational energy to electrical energy, which may be used to power circuit(s), device(s) and/or other purpose(s). In some aspects, the electrical charge is employed in changing the resonant frequency of a mechanical structure and/or generating an electrostatic force, which may be repulsive.

Abstract: Provided is a semiconductor integrated circuit including: an anti-fuse element that electrically connects a first node and a first power supply terminal when data is written and electrically disconnect the first node and the first power supply terminal when data is not written; a first switch circuit that is connected between the first node and a first data line applied with a predetermine first voltage, and enters an off state from an on state according to a first control signal; and a detection part that detects write data of the anti-fuse element according to whether a voltage of the first node is substantially the same as the first voltage or substantially the same as a supply voltage of the first power supply terminal when the first switch circuit enters the off state.

Abstract: An apparatus for precluding the use of extended JTAG operations, including a JTAG control chain, a feature fuse, a level sensor, an access controller, and a blow controller. The JTAG control chain enables/disables the extended JTAG operations. The feature fuse indicates whether the extended JTAG features are to be disabled. The level sensor monitors an external voltage signal, and indicates that the external voltage signal is at a legal level. The access controller determines if the feature fuse is blown, and directs the JTAG control chain to disable the extended JTAG operations if the feature fuse is blown, and directs the JTAG control chain to disable the extended JTAG operations if the external voltage signal is at an illegal level regardless of whether the feature fuse is blown. The blow controller receives a voltage, and blows a selected fuse within a fuse array responsive to a valve of the voltage.

Abstract: Provided is an apparatus for generating a digital value that may generate a random digital value, and guarantee time invariance of the generated digital value. The apparatus may include a digital value generator to generate a random digital value using semiconductor process variation, and a digital value freezing unit that may be connected to the digital value generator and fixed to one of a first state and a second state based on the generated digital value, to freeze the digital value.

Abstract: A fuse circuit includes an electric fuse coupled to a first voltage source; a low resistance unit coupled to the electric fuse and having a junction which is capable of breaking down; and a switching unit coupled between the low resistance unit and a second voltage source.

Abstract: A reference voltage generating circuit includes a first power supply, a second power supply, a first variable resistance circuit having one end connected to the first power supply and configured to be capable of adjusting a resistance value of the first variable resistance circuit, a series resistance circuit having at least one resistance and one end connected to the first variable resistance circuit, a second variable resistance circuit having one end connected to the series resistance circuit and the other end connected to the second power supply, and configured to be capable of adjusting a resistance value of the second variable resistance circuit, a first terminal arranged between the first variable resistance circuit and the series resistance circuit, a second terminal arranged between the series resistance circuit and the second variable resistance circuit, and a voltage selecting circuit configured to select one of a voltage of the first terminal and a voltage of the second terminal, and output the se

Abstract: An apparatus for programming a fuse includes a programmable branch comprising a fusable element and a reverse-biased diode connected in series. The programmable branch is connected in parallel with a current boost capacitor. An electrical source or input supplies a current that is sufficient to charge the current boost capacitor to a breakdown voltage of the reverse-biased diode and subsequently melt the reverse-biased diode. Melting the reverse-biased diode may induce a reduction in voltage across the current boost capacitor and result in a current surge through the programmable branch that is sufficient to program (i.e. blow) the fusable element. A corresponding method for programming a fuse is also disclosed.

Abstract: An antifuse has first and second semiconductor regions having one conductivity type and a third semiconductor region therebetween having an opposite conductivity type. A conductive region contacting the first region has a long dimension in a second direction transverse to the direction of a long dimension of a gate. An antifuse anode is spaced apart from the first region in the second direction and a contact is connected with the second region. Applying a programming voltage between the anode and the contact with gate bias sufficient to fully turn on field effect transistor operation of the antifuse heats the first region to drive a dopant outwardly, causing an edge of the first region to move closer to an edge of the second region and reduce electrical resistance between the first and second regions by an one or more orders of magnitude.

Abstract: An internal voltage adjusting circuit of a semiconductor memory device processes a period from activation to deactivation of a reset bar signal by dividing the period into a first period to a third period. In the first period, a peripheral circuit voltage is stabilized to a lowest value to suppress power consumption. In the second period in which a power source voltage is stabilized, the peripheral circuit voltage is set to a highest value to read out optimum internal voltage values from a fuse circuit in a stable manner. In the third period after reading out the optimum internal voltage values, the peripheral circuit voltage is returned to the lowest value to suppress the power consumption. When the reset bar signal is deactivated, the peripheral circuit voltage is set based on the optimum internal voltage values read out from the fuse circuit.

Abstract: A semiconductor device includes an electric fuse circuit and a program protective circuit. The electric fuse circuit includes a fuse element and a transistor connected together in series and placed between a program power supply and a grounding, and controlling sections. The program protective circuit is placed in parallel with the electric fuse circuit and between the program power supply and the grounding. When a surge voltage is applied between the program power supply and the grounding, the foregoing structure allows a part of a surge electric current can flow through the program protective circuit.

Abstract: A fuse circuit includes a fuse information signal generation unit and an output driving unit. The fuse information signal generation unit is configured to precharge a fuse information signal in response to a precharge signal and drive the fuse information signal in response to a selection signal capable of cutting a fuse. The output driving unit configured to equally maintain potentials at both terminals of the fuse in response to a control signal.

Abstract: A fuse circuit includes a plurality of fuse sets configured to perform fuse programming and generate fuse signals in response to fuse programming signals and a fuse control unit configured to generate the fuse programming signals depending upon a level of a programming voltage.

Abstract: A fuse device includes a fuse unit, which includes a cathode, an anode, and a fuse link coupling the cathode and the anode. A transistor includes at least a portion of the fuse unit to be used as an element of the transistor.

Abstract: An ESD protection circuit including a first electrostatic discharge protection circuit provided between first power supply wiring and first ground wiring; a second ESD protection circuit provided between second power supply wiring and second ground wiring; a third ESD protection circuit provided between the first ground wiring and the second ground wiring; a PMOS transistor coupled to the first power supply wiring and provided between a first CMOS circuit coupled to the first ground wiring and the first power supply wiring, the first CMOS circuit receiving a signal from a first internal circuit and outputting a signal to a first node; an NMOS transistor provided between the first node and the first ground wiring; and an ESD detection circuit that renders the PMOS transistor conductive and the NMOS transistor non-conductive during normal operation, and renders the PMOS transistor non-conductive and the NMOS transistor conductive when an ESD is applied.

Abstract: An apparatus in an integrated circuit for precluding the use of extended JTAG operations. The apparatus has a JTAG control chain, a feature fuse, a level sensor, and an access controller. The JTAG control chain is configured to enable/disable the extended JTAG operations. The feature fuse is configured to indicate whether the extended JTAG features are to be disabled. The level sensor is configured to monitor an external voltage signal, and configured to indicate that the external voltage signal is at an illegal level. The access controller is coupled to the feature fuse, the level sensor, and the JTAG control chain, and is configured to determine if the feature fuse is blown, and is configured to direct the JTAG control chain to disable the extended JTAG operations if the external voltage signal is at an illegal level regardless of whether the feature fuse is blown.

Abstract: A semiconductor device includes a signal output unit, and a decision unit. The signal output unit includes m (?2) pieces of fuses, a NAND gate, resistance elements, and an output terminal. The decision unit decides whether n or more pieces (m?n?2) of fuses are disconnected out of the m pieces of fuses included in the signal output unit, and outputs the result of a decision. When m=n=2, the decision unit is constituted of a NOR gate having two input terminals connected to a respective end of the fuses. Thus, a H-level potential signal is output at an output terminal of the NOR gate when the decision result is affirmative. On the other hand, when the decision result is negative, a L-level potential signal is output at the output terminal.

Abstract: An apparatus for programming a fuse includes a programmable branch comprising a fusable element and a reverse-biased diode connected in series. The programmable branch is connected in parallel with a current boost capacitor. An electrical source or input supplies a current that is sufficient to charge the current boost capacitor to a breakdown voltage of the reverse-biased diode and subsequently melt the reverse-biased diode. Melting the reverse-biased diode may induce a reduction in voltage across the current boost capacitor and result in a current surge through the programmable branch that is sufficient to program (i.e. blow) the fusable element. A corresponding method for programming a fuse is also disclosed.