Abstract: There is provided a non-volatile memory circuit including: plural storage element sections each including a zener zap device and a switch section that connects an anode of the zener zap device to an output terminal during data reading; and wherein cathodes of respective zener zap devices of the plural storage element sections are commonly connected so as to be connected to a power supply employed in the writing or to a power supply employed in the reading, wherein the output terminals of the plural storage element sections are commonly connected to an input terminal of a detector, an anode of each of the storage element sections being connected to a ground voltage during data writing, and wherein the switch section is switched ON during data reading so as to connect the anode of the storage element section through the output terminal to the input terminal of the detector.

Abstract: A repair circuit includes first and second fuse circuits, a determination circuit and an output circuit. The first fuse circuit includes a first fuse and is configured to generate a first master signal indicating whether the first fuse has been programmed. The second fuse circuit includes second fuses and is configured to generate a first address indicating whether each of the second fuses has been programmed. The determination circuit is configured to generate a detection signal based on the first master signal and the first address. The detection signal indicates whether a negative program operation has been performed on the second fuse circuit. The output circuit is configured to generate a second master signal based on the first master signal and the detection signal and generate a repair address corresponding to a defective input address based on the first address and the detection signal.

Abstract: Improvement of key electrical specifications of vertical semiconductor devices, usually found in the class of devices known as discrete semiconductors, has a direct impact on the performance achievement and power efficiency of the systems in which these devices are used. Imprecise vertical device specifications cause system builders to either screen incoming devices for their required specification targets or to design their system with lower performance or lower efficiency than desired. Disclosed is an architecture and method for achieving a desired target specification for a vertical semiconductor device. Precise trimming of threshold voltage improves targeting of both on-resistance and switching time. Precise trimming of gate resistance also improves targeting of switching time. Precise trimming of a device's effective width improves targeting of both on-resistance and current-carrying capability.

Abstract: A product includes: a part including at least one component characterized as an energetic material, where the at least one component is at least partially characterized by physical characteristics of being deposited by an electrophoretic deposition process. A method includes: providing a plurality of particles of an energetic material suspended in a dispersion liquid to an EPD chamber or configuration; applying a voltage difference across a first pair of electrodes to generate a first electric field in the EPD chamber; and depositing at least some of the particles of the energetic material on at least one surface of a substrate, the substrate being one of the electrodes or being coupled to one of the electrodes.

Abstract: A fuse circuit includes a plurality of fuses, a plurality of switches and a plurality of trimming components. The fuses are coupled in parallel to a first node and a second node. The first node is coupled to an operating voltage. The switches are coupled to the second node. The trimming components are respectively disposed between the switches and a ground voltage, and coupled to the second node via the switches, respectively. When one of the trimming components is activated, the activated trimming component allows a plurality of branch currents to be generated between the first node and the second node. The branch currents respectively flow through the fuses so that one of the fuses is blown out by the branch current flowing through the one of the fuses.

Abstract: An integrated circuit system having an integrated circuit (IC) component which is able to have its functionality destroyed upon receiving a command signal. The system may involve a substrate with the IC component being supported on the substrate. A module may be disposed in proximity to the IC component. The module may have a cavity and a dissolving compound in a solid form disposed in the cavity. A heater component may be configured to heat the dissolving compound to a point of sublimation where the dissolving compound changes from a solid to a gaseous dissolving compound. A triggering mechanism may be used for initiating a dissolution process whereby the gaseous dissolving compound is allowed to attack the IC component and destroy a functionality of the IC component.

Abstract: A semiconductor structure including a device configured to receive an input data-word. The device including a logic structure configured to generate an encrypted data-word by encrypting the input data-word through an encrypting operation. The device further including an eFuse storage device configured to store the encrypted data-word as eFuse data by blowing fuses in accordance with the encrypted data-word.

Abstract: Systems and methods of the invention generally relate to altering the functionality of a non-transient electronic device. A container holding an agent is located proximal to a non-transient electronic device capable of performing at least one function. The agent is capable of rendering the device incapable of performing the at least one function. The container is configured to controllably release the agent to the electronic device in a variety of passive and active eventualities.

Abstract: A fuse circuit includes a plurality of fuses, a plurality of switches and a plurality of trimming components. The fuses are coupled in parallel to a first node and a second node. The first node is coupled to an operating voltage. The switches are coupled to the second node. The trimming components are respectively disposed between the switches and a ground voltage, and coupled to the second node via the switches, respectively. When one of the trimming components is activated, the activated trimming component allows a plurality of branch currents to be generated between the first node and the second node. The branch currents respectively flow through the fuses so that one of the fuses is blown out by the branch current flowing through the one of the fuses.

Abstract: A stressed substrate for transient electronic systems (i.e., electronic systems that visually disappear when triggered to do so) that includes one or more stress-engineered layers that store potential energy in the form of a significant internal stress. An associated trigger mechanism is also provided that, when triggered, causes an initial fracture in the stressed substrate, whereby the fracture energy nearly instantaneously travels throughout the stressed substrate, causing the stressed substrate to shatter into multiple small (e.g., micron-sized) pieces that are difficult to detect. The internal stress is incorporated into the stressed substrate through strategies similar to glass tempering (for example through heat or chemical treatment), or by depositing thin-film layers with large amounts of stress. Patterned fracture features are optionally provided to control the final fractured particle size. Electronic systems built on the substrate are entirely destroyed and dispersed during the transience event.

Abstract: A plurality of fuse cells includes a first fuse cell and a second fuse cell. Each of the first and second fuse cells includes a first anti-fuse and a second anti-fuse. A method of programming the fuse cells includes rupturing the first anti-fuse of the first fuse cell based on first data loaded to a program control circuit. The method includes rupturing the second anti-fuse of the first fuse cell before loading second data to the program control circuit. The second data is for rupturing the first anti-fuse of the second fuse cell or the second anti-fuse of the second fuse cell.

Abstract: The invention pertains to a logic circuit device comprising at least one digital input furnished with a fuse (FUS) being, in the closed state, suitable for applying an electrical input voltage of the logic circuit corresponding to a first logic state from among the logic states 0 and 1, and, in the definitive open state, suitable for applying an electrical input voltage of the logic circuit corresponding to the second logic state from among the logic states 0 and 1, said fuse (FUS) being suitable for being placed definitively in the second logic state by injection of a current greater than a threshold current (CS).

Abstract: An anti-fuse includes a single transistor formed over an active region of a semiconductor substrate and entering a fuse cut state by a threshold voltage being varied upon receiving a voltage applied thereto. The single transistor includes a device isolation film formed in the semiconductor substrate to define the active region, and a liner trap film formed between the device isolation film and the active region in such a manner that electrons are trapped in the liner trap film upon receiving the voltage.

Abstract: A memory-like structure composed of variable resistor elements for use in tuning respective branches and leaves of a clock distribution structure, which may be used to compensate for chip-by-chip and/or combinatorial logic path-by-path delay variations, which may be due, for example, to physical variations in deep submicron devices and interconnections, is presented. A single system clocked scan flip-flop with the capability to perform delay test measurements is also presented. Methods for measuring combinatorial logic path delays to determine the maximum clock frequency and delays to program the variable resistors, as well as methods for calibrating and measuring the programmed variable resistors, are also presented.

Abstract: Nanoscale efuses, antifuses, and planar coil inductors are disclosed. A copper damascene process can be used to make all of these circuit elements. A low-temperature copper etch process can be used to make the efuses and efuse-like inductors. The circuit elements can be designed and constructed in a modular fashion by linking a matrix of metal columns in different configurations and sizes. The number of metal columns, or the size of a dielectric mesh included in the circuit element, determines its electrical characteristics. Alternatively, the efuses and inductors can be formed from interstitial metal that is either deposited into a matrix of dielectric columns, or left behind after etching columnar openings in a block of metal. Arrays of metal columns also serve a second function as features that can improve polish uniformity in place of conventional dummy structures. Use of such modular arrays provides flexibility to integrated circuit designers.

Abstract: Semiconductor systems are provided. The semiconductor system includes a controller and a semiconductor device. The controller generates a power voltage signal. The semiconductor device generates a power-up signal in response to the power voltage signal, generates a first selection pulse, a second selection pulse and an initialization pulse signal, generates a first fuse signal for controlling an internal operation according to a cut state of a first fuse, and generates a second fuse signal for controlling the internal operation according to a cut state of a second fuse.

Abstract: Semiconductor systems are provided. The semiconductor system includes a controller and a semiconductor device. The controller generates a power voltage signal. The semiconductor device generates a power-up signal in response to the power voltage signal, generates a first selection pulse, a second selection pulse and an initialization pulse signal, generates a first fuse signal for controlling an internal operation according to a cut state of a first fuse, and generates a second fuse signal for controlling the internal operation according to a cut state of a second fuse.

Abstract: Embodiments related to electrically characterizing a semiconductor device are provided. In one example, a method for characterizing a pin of a semiconductor device is provided, the method comprising providing a test pattern to the semiconductor device. Further, the method includes adjusting a selected electrical state of a pin of the semiconductor device and measuring a value for a dependent electrical state of the pin responsive to the selected electrical state. The example method also includes generating an electrical characterization for the pin by correlating the dependent electrical state with the selected electrical state and outputting the electrical characterization for display.

Abstract: There is described a passive heater-and-diode multiplexing network for selective addressing of thermally-coupled and electrically-disconnected fuses within a passive device network (resistor/capacitor/inductor) or within an application circuit.

Abstract: Systems and methods of the invention generally relate to altering the functionality of a non-transient electronic device. A container holding an agent is located proximal to a non-transient electronic device capable of performing at least one function. The agent is capable of rendering the device incapable of performing the at least one function. The container is configured to controllably release the agent to the electronic device in a variety of passive and active eventualities.

Abstract: A low cost, small scale semiconductor device including a trimming circuit having a fuse resistor is disclosed. By a trimming circuit being configured of a MOSFET, a protection circuit, and a fuse resistor, it is possible to carry out a change from an open circuit state to a short circuit state by fusing the fuse resistor. Also, by the protection circuit and fuse resistor configuring the trimming circuit being formed in a two layer structure, it is possible to reduce the size of the trimming circuit, and thus it is possible to provide a low cost, small scale semiconductor device having a trimming circuit that occupies a small area.

Abstract: An apparatus for monitoring timing of a plurality of critical paths of a functional circuit includes a plurality of canary circuits, each configured to be coupled to a critical path of a functional circuit for detecting and outputting critical timing events. Each canary circuit includes an adjustable delay element and an analyzer circuit for receiving a count of the critical timing event output from at least one of the plurality of canary circuits for a predetermined time interval for a plurality of delay values of the adjustable delay elements and for determining a probability distribution of critical timing events of the at least one of the plurality of critical paths for the predetermined time interval for the plurality of delay values.

Abstract: Systems and methods for authenticating electronic devices may perform one or more operations including, but not limited to: receiving at least one code associated with an authorization to perform one or more manufacturing life-cycle operations for at least one electronic device; and blowing one or more fuses of the at least one electronic device according to the at least one code associated with an authorization to perform one or more manufacturing life-cycle operations for the at least one electronic device.

Abstract: Embodiments may include an eFuse cell. The eFuse cell may include an eFuse having a first end and a second end. A blowFET has a first source/drain area, a second source/drain area, and a first gate. The first source/drain area is coupled to the second end of the eFuse, the second source/drain area is coupled to ground, and the first gate is coupled to a first node. The eFuse cell includes a senseFET having a third source/drain area, a fourth source/drain area, and a second gate. The second gate is coupled to the first node, and the third source/drain area is coupled to a second node. The second node is coupled to an operation signal and the second end of the eFuse. The eFuse cell includes a select eFuse logic element having an input to receive a select eFuse signal and an output coupled to the first node.

Abstract: In one embodiment described herein, on-die programmable fuses may be used. On-die programmable fuses may be programmed by entities other than the chip manufacturer after the fuse array chip has been manufactured and shipped out. However, other non-volatile memories may also be used.

Abstract: Systems and methods for authenticating electronic devices may perform one or more operations including, but not limited to: receiving at least one code associated with an authorization to perform one or more manufacturing life-cycle operations for at least one electronic device; and blowing one or more fuses of the at least one electronic device according to the at least one code associated with an authorization to perform one or more manufacturing life-cycle operations for the at least one electronic device.

Abstract: Provided is a semiconductor integrated circuit including: an anti-fuse element that electrically connects a first node and a first power supply terminal when data is written and electrically disconnect the first node and the first power supply terminal when data is not written; a first switch circuit that is connected between the first node and a first data line applied with a predetermine first voltage, and enters an off state from an on state according to a first control signal; and a detection part that detects write data of the anti-fuse element according to whether a voltage of the first node is substantially the same as the first voltage or substantially the same as a supply voltage of the first power supply terminal when the first switch circuit enters the off state.

Abstract: SoC and SiP designs are configured with an antifuse link within the die to allow on-die programming of bond wires connecting package lead fingers to the bond pads on the die. This permits alteration of the bond pad connections for the die, particularly for the ground voltage ground signal (VSS) connections on the bond pad, at the testing stage after the die package and the power supply have been installed on the PCB. On-die programming of antifuse link allows the VSS bond pad connections to be reconfigured, typically to eliminate long bond wire runs to reduce ground bounce and simultaneous switching output (SSO) noise, after assembly and field testing of the integrated circuit. Antifuse programming is completed by applying the programming voltage to the programming pad of the antifuse.

Abstract: A trim circuit for a power supply controller includes: a control circuit; at least a capacitance type programmable circuit connection; and a switching circuit, under control of the control circuit, the switching circuit selectively coupling the capacitance type programmable circuit connection to anyone of an operation voltage and a programming voltage, for determining a programming state of the capacitance type programmable circuit connection.

Abstract: A microcircuit card (200) includes means for detecting an attack on the card, and command means (130) capable of blowing a fuse (250) of the card when an attack is detected.

Abstract: A fuse circuit having a fuse unit cell containing two fuses. In the program/write mode, only one of the fuses in the fuse unit cell will be blown. In read mode, since only one fuse is blown, the current that goes through the two fuses in the fuse unit cell will be very small. Hence, the read power consumption for the fuse circuit is also very small and its sensing speed is also very high.

Abstract: An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.

Abstract: A semiconductor integrated circuit includes a rupture instructing pulse generation unit configured to generate a rupture instructing pulse signal in response to a fuse rupture command signal and an address; a first anti-fuse rupture unit configured to perform an operation for rupturing a first anti-fuse during an enable period of the rupture instructing pulse signal, and generate rupture information of the first anti-fuse; a pulse shifting unit configured to delay the rupture instructing pulse signal and generate a delayed rupture instructing pulse signal; and a second anti-fuse rupture unit configured to perform an operation for rupturing a second anti-fuse during an enable period of the delayed rupture instructing pulse signal, and generate rupture information of the second anti-fuse.

Abstract: Many inventions are disclosed. Some aspects are directed to MEMS, and/or methods for use with and/or for fabricating MEMS, that supply, store, and/or trap charge on a mechanical structure disposed in a chamber. Various structures may be disposed in the chamber and employed in supplying, storing and/or trapping charge on the mechanical structure. In some aspects, a breakable link, a thermionic electron source and/or a movable mechanical structure are employed. The breakable link may comprise a fuse. In one embodiment, the movable mechanical structure is driven to resonate. In some aspects, the electrical charge enables a transducer to convert vibrational energy to electrical energy, which may be used to power circuit(s), device(s) and/or other purpose(s). In some aspects, the electrical charge is employed in changing the resonant frequency of a mechanical structure and/or generating an electrostatic force, which may be repulsive.

Abstract: An anti-fuse circuit includes: an anti-fuse unit including an anti-fuse capable of being programmed in response to a rupture signal and configured to generate a fuse signal corresponding to a state of the anti-fuse; a dummy fuse unit including a dummy fuse and configured to generate a dummy fuse signal corresponding to a state of the dummy fuse; and a blocking unit configured to output the fuse signal as a fuse output signal in response to a state of the dummy fuse signal.

Abstract: A fuse sensing circuit is disclosed. Embodiments include: providing a sense input terminal; providing a sense output terminal; and providing first and second capacitors that are configured to charge and discharge based on the sense input terminal, wherein the first and second capacitors are further configured to discharge current to a fuse unit cell, and the sense output terminal is configured to indicate a fuse state of the fuse unit cell based on the discharging of the first and second capacitors. Embodiments include the indicated fuse state being based on a discharge rate difference between the discharging of the first capacitor and the discharging of the second capacitor.

Abstract: An anti-fuse circuit includes: a rupture unit including an anti-fuse programmed in response to an input rupture signal during a program mode, and configured to generate an output rupture signal corresponding to a state of the anti-fuse to output the generated output rupture signal to a transmission node, a voltage clamp unit configured to generate a clamp voltage proportional to an external voltage level to generate the clamp voltage having a constant voltage level when the external voltage level rises to a predetermined level or more, and a fuse signal generation unit configured to reset the transmission node to the clamp voltage at the initial stage of the program mode to generate a fuse signal in response to the voltage level of the transmission node during an output mode.

Abstract: Provided are a trimming circuit which does not need a dedicated terminal to which a current for cutting a fuse is input, and also a semiconductor device including the trimming circuit. The trimming circuit includes: an input terminal connected to a pad which is an external terminal of an internal circuit; a fuse provided between a power supply terminal and an output terminal; and a diode provided between the input terminal and the output terminal. The trimming circuit performs trimming by applying, to the pad, such a voltage that the diode is biased in the forward direction.

Abstract: A power device possesses a built-in fuse function and can continue to normally operate after a short circuit failure. The power device includes a plurality of output cells, a plurality of bonding wires provided corresponding to the output cells, and a control terminal driving circuit. Each of the output cells includes an output transistor. First side electrodes of the output transistors are commonly coupled to a first power source. Each of second side electrodes of the output transistors is coupled to an output terminal through the corresponding bonding wire. The control terminal driving circuit supplies a drive signal to the control terminals of the individual output transistors to control the output transistors. Each of the bonding wires is designed to be fused and cut if the output transistor included in the corresponding output cell fails and is shorted.

Abstract: A semiconductor device includes: a first driving voltage generation unit configured to generate a first driving voltage; a fuse unit coupled between an output node for receiving the first driving voltage and a fuse state sensing node; a driving unit configured to drive the fuse state sensing node with a second driving voltage in response to a control signal; a voltage level control unit configured to generate a voltage level control signal in response to a fuse state sensing signal that corresponds to a voltage level of the fuse state sensing node; and a second driving voltage generation unit configured to control and output a voltage level of the second driving voltage in response to the voltage level control signal. The semiconductor device repeatedly performs a rupture operation by monitoring a fuse state sensing signal.

Abstract: A circuit for programming a fuse is disclosed. The circuit includes a voltage supply terminal (Vp) and a latch circuit comprising a p-channel transistor and an n-channel transistor (208-214). A semiconductor controlled rectifier (206) in the circuit includes at least one terminal of the p-channel transistor. A fuse (200) is coupled between the voltage supply terminal and the semiconductor controlled rectifier. The fuse is programmed in response to the semiconductor controlled rectifier.

Abstract: The trimming circuit includes a plurality of trimmable resistances that may be coupled among them, each resistance being connected in parallel to a respective fuse. The trimming circuit allows burning any number of fuses according to a fixed trimming sequence using only one or two dedicated pins because it includes an input diode-connected transistor and a plurality of trimming transistors of different sectional area, each connected to force current throughout a respective one of the shunt fuses and coupled to the input diode-connected transistor such to mirror the current flowing therethrough. The fuses of the trimming circuit may be burnt by applying a trimming voltage to the diode-connected input transistor with a voltage generator connected between a dedicated pin of the circuit and a terminal at a reference potential, such to force a current therethrough as long as the mirrored currents flowing throughout the fuses burn them.

Abstract: An integrated circuit includes a plurality of internal circuits, an e-fuse array circuit configured to store a data used by the internal circuits, and a fuse circuit configured to store a trimming data to set the e-fuse array circuit.

Abstract: A method for controlling performance of an integrated circuit using a zero-pin serial interface is provided. The method comprises identifying a desired performance characteristic of the circuit, and transmitting a first change mode signal to the circuit on a first pin to cause the circuit to enter an instruction reception mode, with the first pin performing differently during a normal operation mode. The method also comprises transmitting a performance adjusting instruction to the circuit on a second pin when the circuit is in the instruction reception mode, with the second pin performing differently during the normal operation mode, and transmitting a second change mode signal to the circuit on the first pin to cause the circuit to enter the normal operation mode. An output performance of the circuit is compared to the desired performance characteristic, with the output performance being the performance of the circuit during the normal operation mode.

Abstract: A fuse circuit having a fuse unit cell containing two fuses. In the program/write mode, only one of the fuses in the fuse unit cell will be blown. In read mode, since only one fuse is blown, the current that goes through the two fuses in the fuse unit cell will be very small. Hence, the read power consumption for the fuse circuit is also very small and its sensing speed is also very high.

Abstract: A fuse sensing circuit is disclosed. Embodiments include: providing a sense input terminal; providing a sense output terminal; and providing first and second capacitors that are configured to charge and discharge based on the sense input terminal, wherein the first and second capacitors are further configured to discharge current to a fuse unit cell, and the sense output terminal is configured to indicate a fuse state of the fuse unit cell based on the discharging of the first and second capacitors. Embodiments include the indicated fuse state being based on a discharge rate difference between the discharging of the first capacitor and the discharging of the second capacitor.

Abstract: A fuse circuit includes a programming fuse signal generation block configured to generate parity signals, logic levels of which are determined according to addresses selected among a plurality of addresses with a programming enable signal enabled, and generate programming fuse signals which are programmed in response to the programming enable signal, the plurality of addresses and the parity signals; a corrected pulse generation block configured to correct an error included in the programming fuse signals and generate corrected pulses; and a fuse unit configured to generate fuse signals which are reprogrammed according to the corrected pulses.

Abstract: A semiconductor package having a mechanical fuse therein and methods to form a semiconductor package having a mechanical fuse therein are described. For example, a semiconductor structure includes a semiconductor package. A semiconductor die is housed in the semiconductor package. A microelectromechanical system (MEMS) device is housed in the semiconductor package. The MEMS device has a suspended portion. A mechanical fuse is housed in the semiconductor package and either coupled to, or decoupled from, the suspended portion of the MEMS device.

Abstract: A method for programming a multi-level electrical fuse system comprises providing a fuse box with an electrical fuse and providing one of at least two fuse writing voltages to the electrical fuse to program the electrical fuse to one of at least two resistance states. The fuse box comprises at least one electrical fuse, a programming device serially coupled to the electrical fuse, and a variable power supply coupled to the fuse box and configured to generate two or more voltage levels.

Abstract: A highly reliable trimming circuit is provided. A rewritable trimming circuit is provided. A method for driving a highly reliable trimming circuit is provided. A method for driving a rewritable trimming circuit is provided. The trimming circuit includes a storage node connected to a source electrode or a drain electrode of a transistor whose off-state leakage current is extremely low and a transistor whose gate electrode is connected to the storage node. The trimming state of an element or a circuit connected in parallel to a source electrode and a drain electrode of the transistor whose gate electrode is connected to the storage node is controlled using the transistor whose off-state leakage current is extremely low.