Abstract: A multi-level signal transmitter includes a voltage selection circuit, which is configured to select one amongst a plurality of driving voltages, which have different voltage levels, in response to input data including at least two bits of data therein. A driver circuit is also provided, which is configured to generate an output data signal as a multi-level signal, in response to the selected one of the plurality of driving voltages. This selected signal is provided as a body bias voltage to at least one transistor within the driver circuit. This driver circuit may include a totem-pole arrangement of first and second MOS transistors having respective first and second body bias regions therein, and at least one of the first and second body bias regions may be responsive to the selected one of the plurality of driving voltages.

Abstract: A bias circuit is provided. The bias circuit may include a first transistor forming an input node, a second transistor forming an output node, and a switch array disposed between the first transistor and the second transistor. The switch array may be configured to charge the first transistor to a supply voltage and the second transistor to a ground during a first mode of operation, and couple the first transistor to the second transistor to approximate a final bias voltage during a second mode of operation.

Abstract: A semiconductor device includes first and second electrodes, a semiconductor part therebetween, and a control electrode between the semiconductor part and the first electrode. The semiconductor part includes first, third and fifth layers of a first conductivity type and second and fourth layers of a second conductivity type. The second layer is provided between the first layer and the first electrode. The third layer is provided between the second layer and the first electrode. The fourth layer and the fifth layer are selectively provided between the first layer and the second electrode. In a method for controlling the semiconductor device, first to third voltages are applied in order to the control electrode while a p-n junction between the first and second layers is biased in a forward direction. The second and third voltages are greater than the first voltage, and the third voltage is less than the second voltage.

Abstract: A memory device can dynamically select a voltage step size for programming (i.e., charging) memory cells. The memory device can increase the voltage step size to reduce programming time or decrease the voltage step size to reduce errors. The memory device can identify device conditions, such as temperature or amount of use (e.g., a count of program/erase cycles). The memory device can increase the voltage step size when the device conditions are less likely to cause errors (e.g., in a middle temperature range or below a threshold number of program/erase cycles) or can decrease the voltage step size when the device conditions are more likely to cause errors (e.g., in a high or low temperature range or above a threshold number of program/erase cycles).

Abstract: A charge pump cell for a charge pump is disclosed that may exhibit improved latch-up immunity. A circuit may be arranged at the charge pump cell to apply a voltage to a bulk contact of a charge transfer transistor of such a charge pump cell at least partially responsive to a relationship between a voltage at a first terminal of the charge transfer transistor and a voltage at a second terminal of the charge transfer transistor. A charge pump including one or more such charge pump cells may include a control loop that is configured to control a pumping signal at least partially responsive to a state of an output voltage of the charge pump.

Abstract: In some examples, an apparatus includes a battery and a dynamic voltage source coupled in series with the battery. The dynamic voltage source is to maintain (or clamp) a system voltage from going below a minimum system voltage.

Abstract: During normal operation of a processor, voltage droop is likely to occur and there is, therefore, a need for techniques for rapidly and accurately detecting this droop so as to reduce the probability of circuit timing failures. The droop detector described herein uses a tap sampled delay line in which a clock signal is split along two separate paths. Each of the taps in the paths are separated by two inverter delays such that the set of samples produced represent sample values of the clock signal that are each separated by a single inverter delay without inversion of the first clock signal between the samples.

Abstract: A switch circuit is provided. The switch circuit includes a P-type transistor switch and a first P-type control transistor. The P-type transistor switch includes a first control end, a first output end, and a first input end. The first input end receives a first input signal whose logic level is one. The first P-type control transistor is coupled to the first input end and the first control end. The first P-type control transistor includes a second control end. The second control end receives a second input signal whose logic level is zero to turn on the first P-type control transistor. When the first P-type control transistor is turned on, the first input signal is transmitted to the first control end of the P-type transistor switch to turn off the P-type transistor switch.

Abstract: A method for an improved characterization of standard cells in a circuit design process is disclosed. Adaptive body biasing is considered during the design process by using simulation results of a cell set, a data-set for performance of the cell set, and a data-set for a hardware performance for a slow, typical and fast circuit property. Static deviations in a supply voltage are considered by determining a reference performance of a cell and a reference hardware performance monitor value at a PVT corner. A virtual regulation and adapting of body bias voltages of the cell set is performed such that the reference performance of the cell or the reference hardware performance monitor value will be reached at each PVT corner and for compensating the static deviation in the supply voltage. The results are provided in a library file.

Abstract: Disclosed are circuits and methods for a comparator with a floating capacitive supply. A capacitor is coupled between a comparator and a power supply. Two sets of electronic switches are configured in opposing operational states to shift the configuration of the circuit between a charging configuration and a decision configuration. In the charging configuration, the capacitor draws current from the power supply. In the decision configuration, the comparator pulls current from the capacitor to perform a decision. The configuration of the two sets of switches is alternated to toggle between the charging configuration and the decision configuration, allowing for the capacitor to be recharged between each decision performed by the comparator.

Abstract: A bus interface bus is described. A first logical state is conveyed over the bus by a higher voltage level and a second logical state is conveyed by a lower voltage level. An output stage of the interface includes a power transistor configured to drive the lower voltage level onto the bus to convey the second logical state, and a protective device between the power transistor and the bus. The protective device couples the power transistor to the bus when turned on and limits negative voltage excursions at the power transistor when turned off. A control circuit of the interface is configured to turn on the protective device when the bus voltage is above the lower voltage level and to turn off the protective device when the bus voltage is at or below the lower voltage level.

Abstract: A sample-and-hold circuit includes a first input resistor, a first transistor, a first capacitor, a second resistor, and a first current source device. A first current terminal of the first transistor is coupled to the first input resistor. A first terminal of the first capacitor is coupled to the second current terminal of the first transistor at a first output node. A first terminal of the second resistor is coupled to the second terminal of the first transistor at the first output node. The first current source device is coupled the first input resistor and to the first current terminal of the first transistor.

Abstract: A semiconductor device capable of performing product-sum operation with low power consumption. The semiconductor device includes first and second logic circuits, first to fourth transistors, and first and second holding units. A low power supply potential input terminal of the first logic circuit is electrically connected to the first and third transistors. A low power supply potential input terminal of the second logic circuit is electrically connected to the second and fourth transistors. The potentials of second gates of the first and fourth transistors are held in the first holding unit as potentials corresponding to first data. The potentials of second gates of the second and third transistors are held in the second holding unit. The on/off states of the first to fourth transistors are determined by second data. A difference in signal input/output time between the first and second logic circuits depends on the first data and the second data.

Abstract: An apparatus includes a plurality of registers and a host interface comprising a plurality of pins. One of the plurality of registers may be a power state entry register configured to control entry to a low power state. One of the plurality of pins may be an enable pin. The apparatus may be configured to enter the low power state in response to setting the power state entry register to a first value and providing the enable pin a signal with a first level. The apparatus may be configured to exit the low power state in response to providing the enable pin the signal with a second level. The apparatus may enter an idle state after exiting the low power state. The low power state may consume less power than the idle state. The enable pin is implemented as an input configured to control a status of a plurality of regulators.

Abstract: A microelectronic circuit structure comprises a stack of bonded layers comprising a bottom layer and at least one upper layer. At least one of the upper layers comprises an oxide layer having a back surface and a front surface closer to the bottom layer than the back surface, and a plurality of FD-SOI transistors built on the front surface. At least a first back gate line and a second back gate line extend separate from each other above the back surface for independently providing a first back gate bias to a first group of transistors and a second back gate bias to a second different group of transistors.

Abstract: A substrate bias generating circuit is provided for generating a substrate bias to a body of a transistor of a functional circuit. The substrate bias generating circuit includes a first transistor and a second transistor which are connected in series between a supply voltage terminal and a ground terminal, and control terminals of the first transistor and the second transistor are coupled to each other. A third transistor includes a terminal electrically coupled to body of one of the first transistor and the second transistor, and another terminal coupled to the body. A resistance element is connected between the terminal of the third transistor and a current input terminal of the first transistor or a current output terminal of the second transistor.

Abstract: A voltage differential sense amplifier circuit for a semiconductor memory circuit is disclosed. The voltage differential sense amplifier circuit includes a first and second pluralities of transistors. A first bias control circuit is included to bias the first plurality of transistors. The first bias control circuit is connected to body terminals of the first plurality of transistors for providing a temperature dependent first bias voltage to control threshold voltages of the first plurality of transistors. The temperature defendant first bias voltage is generated based on junction leakages at the body terminals of the first plurality of transistors. A second bias control circuit is included to bias the second plurality of transistors. The second bias control circuit is connected to body terminals of the second plurality of transistors for providing a temperature dependent second bias voltage to control threshold voltages of the second plurality of transistors.

Abstract: A power supply switching circuit (100) and methodology are disclosed for connecting the greater of first and second power supplies (VSUP1, VSUP2) to an output voltage node (VOUT) with a comparator (102), active power supply switching circuit (103), gate driver circuit (106), and switching array (SW1-SW5) to generate control signals for a pair of PMOS power switches (MP1, MP2) by remapping first and second voltage supplies (VSUP1, VSUP2) to bias the n-wells of the PMOS power switches while simultaneously driving the gate terminals of the PMOS power switches with the gate driver circuit (106) only in response to a comparator activation signal by generating overlapping phase signals (PHI_1, PHI_2) which controls timing of first and second power supply selection signals so that a ground voltage is supplied as the first power supply selection signal only after the maximum bias voltage is supplied as the second power supply selection signal.

Abstract: A system for controlling the impact of process and temperature in passive signal detector includes a voltage level detector, a first transistor with a drain electrically connected to a first input of the voltage level detector, and a second transistor with a drain electrically connected to a second input of the voltage level detector. The first transistor has a threshold voltage of a first voltage value. The threshold voltage corresponds to a minimum gate-to-source voltage to create a conducting path between source and drain terminals of a transistor. The second transistor has a threshold voltage of the first voltage value. An offset voltage is applied across a gate of the first transistor and a source of the second transistor, and applied across a gate of the second transistor and a source of the first transistor. A difference between a threshold voltage and the offset voltage is constant.

Abstract: A switch apparatus is provided. The switch apparatus includes a signal control switch, a switch circuit, a blocking capacitor and a surge current dissipation circuit. The signal control switch and the switch circuit are respectively controlled by a first control signal and a second control signal to be turned on or off. The blocking capacitor is serially coupled between the switch circuit and a reference voltage end. The surge current dissipation circuit includes a Zener diode circuit or at least one diode circuit, and the at least one diode circuit has one or more diodes coupled in series. The one or more diodes coupled in series are coupled between two ends of the surge current dissipation circuit according to a first polarity direction.

Abstract: An output buffer circuit includes an output terminal, a transistor, and a resistor. The transistor includes a first terminal coupled to the output terminal, a second terminal coupled to a ground rail, and a third terminal coupled to an output signal source. The resistor includes a first terminal coupled to a fourth terminal of the transistor, and a second terminal coupled to the ground rail.

Abstract: A compensation device for compensating PVT variations of an analog and/or digital circuit. The compensation device includes a transistor having a first terminal, a second terminal, a third terminal, and a fourth terminal allowing to modify a threshold voltage of the transistor. The transistor is configured to be in saturation region. The voltage at the third terminal has a predetermined value and the difference between the voltage at the second terminal and the voltage at the third terminal has a predetermined value. A current generation module is configured to generate a current of a predetermined value. A compensation module is configured to force this current to flow between the first terminal and the third terminal by adjusting the voltage of the fourth terminal.

Abstract: A tag circuit which allows a load connectable thereto to have a wider power consumption range and which is usable in a wider input power range is provided. The tag circuit includes: a control part which is configured to respond to a command extracted from a radio wave received by an antenna by controlling a load; and a rectifying part which is configured to generate DC power to be supplied to the control part and DC power to be supplied to the load by converting a radio wave received by the antenna into DC power, the rectifying part being capable of changing power conversion characteristics of converting the radio wave received by the antenna into DC power to be supplied to the load.

Abstract: The supply voltage for a module of an integrated circuit managed to support protection against side channel attacks. Upon startup of the integrated circuit, one action from the following actions is selected in response to a command: supplying the module with the supply voltage having a fixed value that is selected from a plurality of predetermined values, or varying the value of the supply voltage in time with a pulsed signal.

Abstract: An exemplary semiconductor device includes a clock generator circuit configured to generate a clock signal, and a duty cycle adjustment circuit configured to receive the clock signal. The duty cycle adjustment circuit includes an adjuster circuit configured to receive a back-bias voltage and to adjust a duty cycle of the clock signal based on the back-bias voltage to provide an output clock signal.

Abstract: Systems and methods for light emitting diodes (LEDs) circuits are provided. Aspects include a set of light emitting diodes (LEDs) arranged in series between a first node and a second node, a power supply coupled to the first node, a first switching element arranged in series between the first node and a third node, wherein the first switching element is in parallel with the set of LEDs, a first charge pump coupled to the third node, a controller configured to operate the first switching element by providing a control voltage for switching the first switching element between an ON and an OFF, wherein the control voltage comprises a switching frequency, and wherein the first charge pump is charged by the power supply responsive to the switching element being in an ON state.

Abstract: A semiconductor device capable of performing product-sum operation with low power consumption. The semiconductor device includes first and second logic circuits, first to fourth transistors, and first and second holding units. A low power supply potential input terminal of the first logic circuit is electrically connected to the first and third transistors. A low power supply potential input terminal of the second logic circuit is electrically connected to the second and fourth transistors. The potentials of second gates of the first and fourth transistors are held in the first holding unit as potentials corresponding to first data. The potentials of second gates of the second and third transistors are held in the second holding unit. The on/off states of the first to fourth transistors are determined by second data. A difference in signal input/output time between the first and second logic circuits depends on the first data and the second data.

Abstract: A stack of series coupled transistors comprising, at least two sub-portions of the stack of series coupled transistors, and at least one logic decoder coupled to the at least two sub-portions to turn ON at least one sub-portion.

Abstract: Low-power, high-performance voltage regulator circuit devices are disclosed and described. In one embodiment, such a device can include a first stage circuitry configured to generate a high voltage reference from a low voltage reference, a second stage circuitry coupled to the first stage circuitry, the second stage circuitry configured to receive the high voltage reference and output a voltage regulated signal, and a switch disposed between and coupled to the first stage circuitry and the second stage circuitry, the switch being configured to couple and uncouple the first stage circuitry from the second stage circuitry.

Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and an I/O interface. A portion of the memory die is used as a pool capacitor for the I/O interface.

Abstract: Devices are described herein for a low static current semiconductor device. A semiconductor device includes a power transistor and a driving circuit coupled to and configured to drive the power transistor. The driving circuit includes a first stage having an enhancement-mode high-electron-mobility transistor (HEMT) and a second stage that is coupled between the first stage and the power transistor and that includes a pair of enhancement-mode HEMTs.

Abstract: An integrated circuit comprises a housing, a plurality of connection pins, a first chip that includes a high-voltage depletion mode transistor, and a second chip that includes a low-voltage enhancement mode transistor. The first chip and second chip each comprise a gate bump contact, a drain bump contact and a source bump contact. The source bump contact of the high-voltage transistor is electrically connected to the drain bump contact of the low-voltage transistor so as to form a central node of the circuit. The circuit includes at least one first Kelvin pin that is electrically connected to the source bump contact of the low-voltage transistor.

Abstract: An apparatus and a method for generation and adaptive regulation of body bias voltages of an integrated circuit efficiently generates control voltages for active body biasing The apparatus includes a digital circuit, a counter, a control unit and at least one charge pump. The control unit and the digital circuit are connected in a closed control loop, and the digital circuit comprises at least one hardware performance monitor to monitor a timing of a body bias voltage. The control loop is formed by a control path comprising the at least one charge pump, the hardware performance monitor and the control unit. The charge pump is controllably connected to the control unit to adjust the charge pump for generation and adaptive regulation of the body bias voltage according to a timing frequency difference between an output signal of the hardware performance monitor and a reference clock signal.

Abstract: An H bridge circuit that is connected to nodes N1 and N2 for a power source and nodes N3 and N4 for a motor includes: a PchMOS transistor that is disposed in an N-type first region and is connected between N1 and N3; an NchMOS transistor that is disposed in an N-type second region and is connected between N2 and N3; a PchMOS transistor that is disposed in an N-type third region and is connected between N1 and N4; and an NchMOS transistor that is disposed in an N-type fourth region and is connected between N2 and N4, in a P-type semiconductor substrate. The distance between the first region and third region is smaller than the distance between the first region and second region, smaller than the distance between the third region and fourth region, and smaller than the distance between the second region and fourth region.

Abstract: The present disclosure discloses a voltage conversion circuit, including: a first power transistor; a second power transistor, where the second power transistor is cut off when the first power transistor is conductive and is conductive when the first power transistor is cut off; a first energy storage element; a second energy storage element, a bleed module, configured to be coupled to the first power transistor, where when the first power transistor is cut off and a voltage of a source of the first power transistor reaches a source threshold, provide a current path for a current flowing from the source of the first power transistor to the ground. By means of the foregoing, a voltage difference between a drain and the source of the first power transistor can be decreased, thereby reducing a risk of burning out the first power transistor, and avoiding an increase in manufacturing costs.

Abstract: A radio frequency switch made up of a plurality of switch cells coupled in series between a first node and a second node is disclosed. Each of the plurality of switch cells has a switch field-effect transistor (FET) having a switch drain terminal, a switch source terminal, a switch gate terminal, and a switch body terminal. A body bias network having a first body bias FET with a first drain terminal coupled to the switch body terminal includes a first cross-FET with a second drain terminal coupled to a first source terminal of the first bias body FET and a second source terminal coupled to the switch gate terminal. A second body bias FET has a third drain terminal coupled to the switch body terminal, and a second cross-FET has a fourth drain terminal coupled to a third source terminal of the second body bias FET.

Abstract: An electronic circuit includes at least one first multi-gate transistor including a first gate and a second gate different from the first gate; and a regulation unit designed to measure a variable representing the drain-source voltage of the first transistor and to apply a polarization potential as a function of the variable to the second gate of the first transistor.

Abstract: Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis.

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include core circuitry connected between a high voltage source and a low voltage source. The core circuitry may include multiple transistors including a first transistor of a first polarity type and a second transistor of a second polarity type that is different than the first polarity type. The integrated circuit may include voltage regulation circuitry connected between an external positive voltage source and ground. The voltage regulation circuitry may operate to provide the low voltage source to the core circuitry. The low voltage source may be equal to or higher than ground. The voltage regulation circuitry may further operate to body bias the multiple transistors with a single voltage that is applied to a body terminal of the first transistor and the second transistor.

Abstract: A method and system of monitoring a reliability of a semiconductor circuit are provided. A current consumption of a first ring oscillator that is in static state is measured at predetermined intervals. Each measured current consumption value is stored. A baseline current consumption value of the first ring oscillator is determined based on the stored current consumption values. A latest measured current consumption value of the first ring oscillator is compared to the baseline current consumption value. Upon determining that the latest measured current consumption value is above a threshold deviation from the baseline current consumption value, the first ring oscillator is identified to have a dielectric breakdown degradation.

Abstract: The inventive concept relates to a semiconductor device including a CMOS circuit and an operation method thereof. A semiconductor device according to an embodiment of the inventive concept includes a semiconductor circuit, a controller, and a voltage generator. The semiconductor circuit operates at a drive voltage to reduce the delay time between input and output as the temperature increases. The controller determines the malfunction of the CMOS circuit based on the difference between the source-drain current of the PMOS transistor and the source-drain current of the NMOS transistor as the temperature changes. The voltage generator generates or adjusts a body-bias voltage applied to the PMOS transistor or the NMOS transistor based on a malfunction determination of the controller. According to the inventive concept, malfunctions and performance deterioration occurring in a CMOS circuit operating at a low voltage may be reduced.

Abstract: An electronic device includes: a clock booster including a doubler capacitor, the clock booster configured to precharge the doubler capacitor to store a boosted intermediate voltage greater than an input voltage; a secondary booster including a booster capacitor, the secondary booster configured to use charges stored on the doubler capacitor to generate a stage output greater than the boosted intermediate voltage; and a connecting switch connected to the clock booster and the secondary booster, the connecting switch configured to electrically connect the doubler capacitor and the booster capacitor during a recycling duration for discharging a recycled charge from the booster capacitor to the doubler capacitor through the connecting switch, wherein the recycling duration is after generating the stage output.

Abstract: A method and system of driving a switched capacitor converter having a plurality of switches. A first driver coupled to a first switch is powered by providing a first reference voltage level VCC to a first supply and a GND reference to a second supply node of the first driver. A second driver coupled to a second switch is powered by providing a unidirectional path between the first supply node of a first driver and the first supply node of the second driver and by keeping OFF the second switch while turning ON the first switch. A third driver coupled to a third switch is powered by providing a unidirectional path between the first supply node of a second driver and the first supply node of the third driver and by keeping OFF the first and third switch while turning ON the second switch.

Abstract: A memory system includes an isolated first well of a first polarity and an array of volatile memory cells. Each of the memory cells includes a first set of transistors in the isolated first well, and a second set of transistors. A source bias circuit is coupled to the array of volatile memory cells. At least a portion of the source bias circuit is in the isolated first well and coupled to source electrodes of the first set of transistors of each of the memory cells. A control circuit is configured to enable the source bias circuit.

Abstract: Related-art back bias generation circuits cause a problem where a long time is required for transition between an operating state and a standby state because driving power is lowered to reduce the power consumption in the standby state. A back bias generation circuit outputs a predetermined voltage. The predetermined voltage is the back bias voltage of a substrate in a standby mode. A bias control circuit stores an electrical charge while a circuit block is in an operating mode, supplies the stored electrical charge to the substrate of a MOSFET included in the circuit block when the circuit block transitions from the operating mode to the standby mode, and subsequently supplies the output of the back bias generation circuit to the substrate of the MOSFET.

Abstract: A transistor biasing circuit including a first controller configured to receive a sensor signal generated based on the performance of one or more transistors of a digital circuit and to compare the sensor signal with a reference signal and to generate a first biasing voltage control signal; a first actuator configured to generate a first biasing voltage based on the first biasing voltage control signal; a second actuator configured to generate a second biasing voltage based on a second biasing voltage control signal; and a second controller configured to generate the second biasing voltage control signal based on an intermediate voltage level generated based on the first and second biasing voltages.

Abstract: Roughness is eliminated and planarization is achieved by a metal oxide film on a surface of a lower electrode. Consequently, damage on a capacitive film caused by the roughness of the lower electrode is reduced. Furthermore, physical damage on the capacitive film is reduced by forming a first layer of an upper electrode by, for example, CVD. Consequently, the damage on the capacitive film is suppressed, and the reliability of the capacitive film is improved. Furthermore, not by forming the whole upper electrode by the CVD or the like, but by forming a second layer by PCD or the like on the first layer, an increase in resistance of the upper electrode is suppressed as well.

Abstract: An HVJT is includes a parasitic diode formed by pn junction between an n?-type diffusion region and a second p?-type separation region surrounding a periphery thereof. The n?-type diffusion region is arranged between an n-type diffusion region that is a high potential side region and an n-type diffusion region that is a low potential side region, and electrically separates these regions. In the n?-type diffusion region, an nchMOSFET of a level-up level shift circuit is arranged. The n?-type diffusion region has a planar layout in which the n?-type diffusion region surrounds a periphery of the n-type diffusion region and a region where the nchMOSFET is arranged protrudes inwardly. A high-concentration inter-region distance L1 of the nchMOS region where the nchMOSFET is arranged is longer than a high-concentration inter-region distance L2 of the parasitic diode. Thus, the reliability of the semiconductor device may be improved.

Abstract: A method for controlling voltage of a doped well in a substrate is provided. The substrate and the doped well are in different conductive type. The method includes applying a substrate voltage to the substrate while a well power for applying a well voltage to the doped well is turned off. The method also includes detecting a voltage level of one of the doped well and the substrate to judge whether or not a voltage target is reached. The well power is turned on to apply the well voltage to the doped well when the voltage level as detected reaches to the voltage target.

Abstract: A body-control-device for a bi-directional transistor, said bi-directional transistor having a first-transistor-channel-terminal, a second-transistor-channel-terminal, a transistor-control-terminal and a transistor-body-terminal. The body-control-device comprises a body-control-terminal connectable to the transistor-body-terminal of the bi-directional transistor, a first-body-channel-terminal connectable to the first-transistor-channel-terminal of the bi-directional transistor, a second-body-channel-terminal connectable to the second-transistor-channel-terminal of the bi-directional transistor, a negative-voltage-source and a switching-circuit configured to selectively provide an offset-first-circuit-path between the first-body-channel-terminal and the body-control-terminal, wherein the offset-first-circuit-path includes the negative-voltage-source such that it provides a negative voltage bias between the body-control-terminal and the first-body-channel-terminal.