Having Particular Substrate Biasing Patents (Class 327/534)
  • Patent number: 10367056
    Abstract: An HVJT is includes a parasitic diode formed by pn junction between an n?-type diffusion region and a second p?-type separation region surrounding a periphery thereof. The n?-type diffusion region is arranged between an n-type diffusion region that is a high potential side region and an n-type diffusion region that is a low potential side region, and electrically separates these regions. In the n?-type diffusion region, an nchMOSFET of a level-up level shift circuit is arranged. The n?-type diffusion region has a planar layout in which the n?-type diffusion region surrounds a periphery of the n-type diffusion region and a region where the nchMOSFET is arranged protrudes inwardly. A high-concentration inter-region distance L1 of the nchMOS region where the nchMOSFET is arranged is longer than a high-concentration inter-region distance L2 of the parasitic diode. Thus, the reliability of the semiconductor device may be improved.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: July 30, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takahide Tanaka, Masaharu Yamaji
  • Patent number: 10352986
    Abstract: A method for controlling voltage of a doped well in a substrate is provided. The substrate and the doped well are in different conductive type. The method includes applying a substrate voltage to the substrate while a well power for applying a well voltage to the doped well is turned off. The method also includes detecting a voltage level of one of the doped well and the substrate to judge whether or not a voltage target is reached. The well power is turned on to apply the well voltage to the doped well when the voltage level as detected reaches to the voltage target.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: July 16, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Hsin-Pang Lu, Hsin-Wen Chen
  • Patent number: 10348296
    Abstract: A body-control-device for a bi-directional transistor, said bi-directional transistor having a first-transistor-channel-terminal, a second-transistor-channel-terminal, a transistor-control-terminal and a transistor-body-terminal. The body-control-device comprises a body-control-terminal connectable to the transistor-body-terminal of the bi-directional transistor, a first-body-channel-terminal connectable to the first-transistor-channel-terminal of the bi-directional transistor, a second-body-channel-terminal connectable to the second-transistor-channel-terminal of the bi-directional transistor, a negative-voltage-source and a switching-circuit configured to selectively provide an offset-first-circuit-path between the first-body-channel-terminal and the body-control-terminal, wherein the offset-first-circuit-path includes the negative-voltage-source such that it provides a negative voltage bias between the body-control-terminal and the first-body-channel-terminal.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: July 9, 2019
    Assignee: NXP USA, Inc.
    Inventors: Evgueniy Nikolov Stefanov, Philippe Dupuy
  • Patent number: 10312906
    Abstract: A switch apparatus is provided, including: a main switch connected between first and second terminals, and electrically connecting or disconnecting the first and second terminals according to gate voltage applied to a gate terminal; a voltage output unit having a voltage divider including a first voltage-division resistance on the first terminal side and a second voltage-division resistance on the second terminal side, and outputting voltage corresponding to voltage of the first terminal and voltage of the second terminal if the main switch is caused to enter a connected state; a buffer outputting voltage following output voltage of the voltage output unit in a connected state of the main switch; and a switch control circuit supplying first voltage corresponding to output voltage of the buffer to the gate terminal, and supplying a second voltage corresponding to output voltage of the buffer to a bulk terminal of the main switch.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: June 4, 2019
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: Kenichi Sato, Atsuo Ito
  • Patent number: 10298227
    Abstract: An apparatus includes a circuitry to perform a high current and/or a high voltage switching. The circuitry includes a first Gallium Nitride (GaN) on a silicon (Si) substrate lateral field effect transistor. A source terminal of the first GaN lateral field effect transistor on the Si substrate includes an electrical connection to backside of P-type Si substrate through a high voltage isolated resistor that is coupled to a source terminal or a second resistor that is operably coupled to a drain terminal and a substrate terminal. The high voltage isolated resistor and the second resistor cause to a leakage current from the drain terminal to the source terminal via a buffer layer. The leakage current equalizes the voltage drop on the first GaN lateral field effect transistor on the Si substrate to a voltage drop on a serially connected second GaN lateral field effect transistor on the Si substrate.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: May 21, 2019
    Assignee: VISIC TECHNOLOGIES LTD.
    Inventors: Gregory Bunin, David Shapiro, Lev Stessin
  • Patent number: 10260962
    Abstract: A device that operates over a plurality of predetermined temperature ranges that can include a subthreshold operating circuit including a first insulated gate field effect device (IGFET) having a first conductivity type. The first IGFET can be coupled to receive a first back body bias potential that changes according to the temperature range in which the device is operating. The subthreshold operating circuit can operate at a power supply potential below a threshold voltage of the first IGFET.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: April 16, 2019
    Inventor: Darryl G. Walker
  • Patent number: 10263622
    Abstract: [Object] To provide a semiconductor apparatus and a method of controlling a MOS transistor, with which a leak current of the MOS transistor can be suppressed. [Solving Means] A semiconductor apparatus includes a MOS transistor and a voltage application unit that applies, when the MOS transistor is off, a voltage for controlling a threshold value of the MOS transistor in a shallower direction onto a substrate of the MOS transistor.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: April 16, 2019
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Tsuyoshi Suzuki
  • Patent number: 10205461
    Abstract: Methods and apparatuses featuring an injection-locked oscillator (ILO) are described. In some embodiments, an ILO can have multiple injection points and a free-running frequency that is capable of being adjusted based on a control signal. In some embodiments, each injection point of an ILO can correspond to a phase tuning range. In some embodiments, a circuit can include circuitry to detect a phase boundary between two adjacent phase tuning ranges. In some embodiments, a circuit can use the detected phase boundary to switch between the two adjacent phase tuning ranges.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: February 12, 2019
    Assignee: Rambus Inc.
    Inventors: Marko Aleksić, Brian S. Leibowitz
  • Patent number: 10181463
    Abstract: An integrated circuit having a CML driver including a driver biasing network. A first output pad and a second output pad are connected to a voltage pad. A first driver is connected to the first output pad and the voltage pad. A second driver is connected to the second output pad and the voltage pad. A first ESD circuit is connected to the voltage pad, the first output pad, and the first driver. A second ESD circuit is connected to the voltage pad, the second output pad, and the second driver. The first ESD circuit biases the first driver toward a voltage of the voltage pad when an ESD event occurs at the first output pad, and the second ESD circuit biases the second driver toward the voltage of the voltage pad when an ESD event occurs at the second output pad.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: January 15, 2019
    Assignee: International Business Machines Corporation
    Inventors: James P. Di Sarro, Robert J. Gauthier, Nathan D. Jack, JunJun Li, Souvick Mitra
  • Patent number: 10181855
    Abstract: An integrated circuit includes a first logic circuit region comprising a first regional clock network for supplying a first regional clock signal to digital logic circuit(s); and a clock gating circuit to derive the first regional clock signal from a clock signal and selectively apply and interrupt the first regional clock signal in accordance with a state select signal. The first logic circuit region comprises a first back bias voltage grid connected to respective bodies of PMOS transistors of the digital logic circuit(s) and a second back bias voltage grid connected to respective bodies of NMOS transistors of the digital logic circuit(s). The integrated circuit further comprises a controllable back bias voltage generator configured to adjust a first back bias voltage of the first back bias voltage grid, and to adjust a back bias voltage of the second back bias voltage grid, in accordance with the state select signal.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: January 15, 2019
    Assignee: GN Hearing A/S
    Inventors: Dan Raun Jensen, Per Asbeck, Frederic Hasbani
  • Patent number: 10164573
    Abstract: A differential-logic logic circuit chained with another differential-logic circuit comprises a first logic cell composed of back-gate transistors, the first cell having a first input for receiving a first input signal and having an output for delivering a first output signal, and a second logic cell complementary to the first cell, composed of back-gate transistors, the second cell having as many inputs as the first cell, each input able to receive an input signal complementary to the respective input signal of the first cell, the second cell having an output for delivering a second output signal complementary to the first output signal of the first cell. The first output signal of the first cell is applied to the back gate of each transistor of the second cell, and the second output signal of the second cell is applied to the back gate of each transistor of the first cell.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: December 25, 2018
    Assignees: UNIVERSITE DE NICE, COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Gilles Fernand Jacquemod, Emeric De Foucauld, Alexandre Benjamin Fonseca, Yves Leduc, Philippe Bernard Pierre Lorenzini
  • Patent number: 10163811
    Abstract: A semiconductor package structure comprises: a high-voltage depletion type semiconductor transistor comprising a source electrode, a gate electrode and a drain electrode; a low-voltage enhancement type semiconductor transistor comprising a source electrode, a gate electrode and a drain electrode; a shell comprising a cavity for receiving the high-voltage depletion type semiconductor transistor and the low-voltage enhancement type semiconductor transistor, and a high-voltage terminal, a first low-voltage terminal and a second low-voltage terminal; and cascade circuits comprising a supporting sheet having a conductive surface. The source electrode of the high-voltage depletion type transistor and the drain electrode of the low-voltage enhancement type semiconductor transistor are fixed to the conductive surface of the supporting sheet and electrically connected to each other through the conductive surface of the supporting sheet.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: December 25, 2018
    Assignee: GPOWER SEMICONDUCTOR, INC.
    Inventor: Shufeng Zhao
  • Patent number: 10122266
    Abstract: In an embodiment, set forth by way of example and not limitation, an integrated circuit includes charge pump circuitry formed on an integrated circuit (IC) chip, a first protective circuit formed on the integrated circuit chip and coupling the first output node to a first IC port, a second protective circuit formed on the integrated circuit chip and coupling the second output node to a second IC port, and a third protective circuit formed on the integrated circuit chip and coupling the power input node to a power input IC port.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: November 6, 2018
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Marco Farina, Mauro Ranzato, Gianluca Mariano
  • Patent number: 10095302
    Abstract: A processing device includes a power management unit to receive a base clock (BCLK) frequency rate to be applied to the processing device; and to determine, using a reference voltage/frequency curve, a voltage corresponding to the BCLK frequency rate, wherein the reference V/F curve is generated based on a reference BCLK frequency rate of the processing device.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: October 9, 2018
    Assignee: Intel Corporation
    Inventors: Ariel Gur, Daniel J Ragland, Ofer Nathan, Nadav Shulman, Esfir Natanzon
  • Patent number: 10068721
    Abstract: In one embodiment, a hot swap circuit is disclosed. The hot swap circuit includes a first switch connected to a power input line. The hot swap circuit also includes a first capacitor connected to the first switch that is charged when the first switch is closed. The hot swap circuit further includes a second switch connected to the first switch and the first capacitor. The hot swap circuit additionally includes an input capacitor connected to the second switch and located in parallel with an input line to a power system. When the second switch is closed, the input capacitor is charged.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: September 4, 2018
    Assignee: Cisco Technology, Inc.
    Inventors: Michael Robert Grant, Yang Li, Jessica Leigh Kiefer, Kan Chiu Seto, Shobhana Punjabi
  • Patent number: 10044260
    Abstract: A charge pump circuit may include: input units suitable for receiving a first input pulse signals and outputting second input pulse signals that are out of phase; an internal voltage generation unit suitable for generating an internal voltage by performing a voltage pumping operation in response to an external voltage and the second input pulse signals, and adjusting a well bias voltage at a power-up period and a normal operation period after the power-up period, in response to a switching control signal; and a switching control signal generation unit suitable for generating the switching control signal which is activated differently on the power-up period and the normal operation period.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: August 7, 2018
    Assignee: SK Hynix Inc.
    Inventor: Chung-Hun Jeon
  • Patent number: 10031538
    Abstract: Low-power, high-performance voltage regulator circuit devices are disclosed and described. In one embodiment, such a device can include a first stage circuitry configured to generate a high voltage reference from a low voltage reference, a second stage circuitry coupled to the first stage circuitry, the second stage circuitry configured to receive the high voltage reference and output a voltage regulated signal, and a switch disposed between and coupled to the first stage circuitry and the second stage circuitry, the switch being configured to couple and uncouple the first stage circuitry from the second stage circuitry.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: July 24, 2018
    Assignee: Intel Corporation
    Inventors: Matthew Dayley, Liyao Miao
  • Patent number: 10008926
    Abstract: A switched capacitor DC-DC converter circuit and a method for outputting voltage using the same are disclosed. The circuit includes a switched capacitor circuit and a body bias control circuit. The on-resistance of the transistor in the switched capacitor circuit is increased by the body bias control circuit, so as to lower the voltage ripple generated from the output voltage.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: June 26, 2018
    Assignee: Nuvoton Technology Corporation
    Inventor: Po-Hsuan Huang
  • Patent number: 9991902
    Abstract: An ADC and an analog-to-digital conversion method are provided. The ADC includes: a clock generator, including M transmission gates, where the M transmission gates are configured to receive a first clock signal that is periodically sent and separately perform gating control on the first clock signal, so as to generate M second clock signals, M is an integer that is greater than or equal to 2; M ADC channels that are configured in a time interleaving manner, configured to receive one analog signal and separately perform, under the control of the M second clock signals, sampling and analog-to-digital conversion on the analog signal, so as to obtain M digital signals, where each ADC channel is corresponding to one clock signal of the M second clock signals; and an adder, configured to add the M digital signals together in a digital field, so as to obtain a digital output signal.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: June 5, 2018
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Jinda Yang, Liren Zhou
  • Patent number: 9979362
    Abstract: A power amplifier include an amplifier including at least one field effect transistor (FET) that operates in an amplifying stage configured to amplify an input signal, and a body controller configured to control a bias voltage of a body terminal of the FET based on a power of the input signal. The body controller performs controlling so that the bias voltage of the body terminal is reduced in response to the power of the input signal being increased. Accordingly, such a power amplifier exhibits improved linearity.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: May 22, 2018
    Assignees: Samsung Electro-Mechanics Co., Ltd., Korea Advanced Institute of Science and Technology
    Inventors: Seung Hoon Kang, Gyu Suck Kim, Song Cheol Hong
  • Patent number: 9973080
    Abstract: According to one embodiment, a switched capacitor power supply circuit includes a switched capacitor power supply circuit unit that supplies a voltage obtained by converting an input voltage with a predetermined conversion ratio as an output voltage by switching a connection configuration between a plurality of capacitors that perform charge and discharge, and a control circuit that switches the connection configuration between the plurality of capacitors according to the output voltage to change the conversion ratio.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: May 15, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Chen Kong Teh
  • Patent number: 9953714
    Abstract: A semiconductor device includes a first circuit configured to generate a first voltage based on a first current, a second circuit that includes a first transistor of a first conductivity type having a first terminal, a second terminal, and a first gate, the second circuit configured to generate a second voltage based on a voltage difference between the first terminal and the second terminal, and a third circuit configured to compare the first voltage and the second voltage, and generate a third voltage for adjusting a substrate bias of the first transistor, based on the comparison result.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: April 24, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Kosuke Yanagidaira
  • Patent number: 9939330
    Abstract: A semiconductor device that may include at least one temperature sensing circuit is disclosed. The temperature sensing circuits may be used to control various operating parameters to improve the operation of the semiconductor device over a wide temperature range. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without compromising performance at other operating temperatures. The temperature sensing circuit may provide a plurality of temperature ranges for setting the operational parameters. Each temperature range can include a temperature range upper limit value and a temperature range lower limit value and adjacent temperature ranges may overlap. The temperature ranges may be set in accordance with a count value that can incrementally change in response to the at least one temperature sensing circuit.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: April 10, 2018
    Inventor: Darryl G. Walker
  • Patent number: 9929643
    Abstract: Embodiments of a charge pump circuit and a method for operating a charge pump circuit are disclosed. In an embodiment, a charge pump circuit includes a charge pump configured to generate a charge pump output voltage, a transistor array including multiple transistor devices that includes at least one transistor device having a back gate terminal coupled to the charge pump output voltage, and a control circuit configured to control the charge pump output voltage so as to regulate the back bias voltage of the transistor devices within the transistor array. Other embodiments are also described.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: March 27, 2018
    Assignee: NXP B.V.
    Inventor: Ivan Carlos Ribeiro do Nascimento
  • Patent number: 9917579
    Abstract: A switching circuit includes a first diode coupled between a first terminal and a second terminal, a second diode coupled between the first terminal and a third terminal, and a bias circuit coupled to the first terminal and configured to bias the first diode on and the second diode off in a first switch state and to bias the first diode off and the second diode on in a second switch state, the bias circuit including a voltage converter configured to convert a fixed voltage to an intermediate voltage and a current source coupled in series with the voltage converter.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: March 13, 2018
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventors: Brendan Foley, David Ryan, James Brogle
  • Patent number: 9911737
    Abstract: An integrated circuit includes a substrate with first and second cells having first and second FDSOI field-effect transistors. There are first and second ground planes, a buried oxide layer and first and second wells, under the ground planes. The first well and the first ground plane have the same doping and the second well and the second ground plane have the same doping. The first and second cells are adjoined and their transistors are aligned in a first direction. The wells of the first cell and the first well of the second cell are doped opposite of the second well. A control device applies a first electrical bias to the wells with the first doping and a second electrical bias to the well with the second doping. The transistors of the first cell and second cell have different threshold voltage levels.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: March 6, 2018
    Assignee: STMicroelectronics SA
    Inventors: Bastien Giraud, Philippe Flatresse, Jean-Philippe Noel, Bertrand Pelloux-Prayer
  • Patent number: 9905194
    Abstract: A display driving integrated circuit is provided which drives a plurality of gate lines included in a display panel. The display driving integrated circuit includes: a charge pump configured to change a voltage from an external power source to generate an output voltage; and a gate line driver configured to drive the plurality of gate lines based on the output voltage. The charge pump may operate in one of a low-current mode and a high-current mode based on a size of the display panel.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: February 27, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chiahsin Lin, Chih-Yang Liao, Jaeyeon Kim
  • Patent number: 9882428
    Abstract: An integrated circuit, such as included as a portion of a sensor node, can include a regulator circuit having an input coupleable to an energy harvesting transducer. The integrated circuit can include a wireless receiver circuit coupled to the regulator circuit and configured to wirelessly receive at least enough operating energy to establish operation of the sensor node without requiring the energy harvesting transducer. The integrated circuit can include a digital processor circuit coupled to the regulator circuit and a power management processor circuit. The digital processor circuit or one or more other circuits can include a subthreshold operational mode established by the power management processor circuit based on the selected energy consumption level. For example, establishing the subthreshold operational mode can include adjusting or selecting a supply voltage so as to establish subthreshold operation of a field effect transistor (FET) in the digital processor circuit or other circuits.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: January 30, 2018
    Assignees: UNIVERSITY OF VIRGINIA PATENT FOUNDATION, UNIVERSITY OF WASHINGTON THROUGH ITS CENTER FOR COMMERCIALIZATION
    Inventors: Benton H. Calhoun, Brian Otis
  • Patent number: 9863808
    Abstract: The present invention relates to an output-current detection IC chip for diode sensors and a diode sensor device, which reduce the influence by a leak current of a protection circuit. The present invention is equipped with a sensor unit in which anodes of N (N being an integer of 2 or more) diode sensors are connected to each other, a common terminal connected to a connection portion where the anodes are connected to each other, N input terminals connected to cathodes of the diode sensors, N+1 protection circuits connected to the input terminals and the common terminal, an I-V conversion circuit which converts an output current of each diode sensor into a voltage, a chopper circuit which switches the polarity of the output current and inputs the same to the I-V conversion circuit, and a dummy protection circuit connected to the input of the I-V conversion circuit.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: January 9, 2018
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: Tetsuya Saito, Kensaku Wada
  • Patent number: 9860468
    Abstract: A solid-state image pickup device includes: a pixel portion in which a plurality of pixels are arrayed in matrix; and an Analog-Digital converter. The Analog-Digital converter converts pixel signals, which are generated in the pixel portion, from analog signals into digital signals. The Analog-Digital converter includes: a comparator; and a counter. The comparator compares the analog signals, each of which corresponds to each of the plurality of pixels, with a reference signal. The comparator includes: a first differential transistor to which the reference signal is input; a second differential transistor to which the analog signals are input; a first load transistor; a second load transistor; and a current source transistor. A fluctuation of a voltage between a gate and a source of the first differential transistor is suppressed. This fluctuation follows a voltage fluctuation of a node connected commonly to the second differential transistor and the second load transistor.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: January 2, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kazuko Nishimura, Yutaka Abe
  • Patent number: 9860639
    Abstract: A power control circuit for a hearing device is devised. The power control circuit has a switched-capacitor power supply, a substrate bias control circuit, a reference circuit, a performance monitor circuit, a first plurality of N-type semiconductors and a second plurality of P-type semiconductors. The performance monitor circuit is adapted to monitor the supply voltage, the first substrate bias control voltage and the second substrate bias control voltage, respectively, and is adapted to provide a measure of performance to the substrate bias control circuit. The substrate bias control circuit is adapted to optimize the current consumption of the circuit by continuously altering the levels of the first substrate bias control voltage and the second substrate bias control voltage based on the performance measurement.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: January 2, 2018
    Assignee: GN HEARING A/S
    Inventor: Martin Vinter
  • Patent number: 9852674
    Abstract: A demultiplexer includes: a first transistor connected between a data input terminal and a first output terminal; a second transistor connected between the data input terminal and a second output terminal; and a first pre-charge circuit connected to a gate electrode of the first transistor, the first pre-charge circuit including: a third transistor and a first diode connected between a first clock input terminal and the gate electrode of the first transistor in parallel; and a first capacitor connected between a second clock input terminal and the gate electrode of the first transistor.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: December 26, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Young Wan Seo, Jong Hee Kim, Ji Sun Kim, Jae Keun Lim, Chong Chul Chai
  • Patent number: 9754932
    Abstract: A semiconductor device includes a substrate, an active layer, a transistor, and a capacitor. The active layer is disposed on the substrate, and the active layer is divided into a first portion and a second portion. The transistor and the capacitor are disposed on the substrate. The transistor includes the second portion, a source electrode, a drain electrode, and a gate electrode. The source electrode and the drain electrode are respectively and electrically connected to the second portion. The gate electrode is disposed on the second portion. The capacitor includes the first portion, a first electrode, a first insulating layer, and a second electrode. The first electrode is electrically connected to the first portion and the source electrode. The first insulating layer is disposed on the first portion. The second electrode is disposed on the first insulating layer and is electrically connected to the gate electrode.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: September 5, 2017
    Assignee: DELTA ELECTRONICS, INC.
    Inventor: Wen-Chia Liao
  • Patent number: 9748378
    Abstract: A semiconductor device includes a transistor in a semiconductor substrate having a first main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, and a gate electrode adjacent to at least two sides of the channel region. The gate electrode is disposed in trenches extending in a first direction parallel to the first main surface. The gate electrode is electrically coupled to a gate terminal. The channel region and the drift zone are disposed along the first direction between the source region and the drain region. The semiconductor device further includes a conductive layer beneath the gate electrode and insulated from the gate electrode. The conductive layer is electrically connected to the gate terminal.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: August 29, 2017
    Assignee: Infineon Technologies AG
    Inventors: Karoline Koepp, Andreas Meiser, Till Schloesser
  • Patent number: 9741859
    Abstract: A field effect transistor (FET) with a graphene layer as a channel layer is disclosed. The FET provides two gate electrodes, one of which receives the gate bias, while, the other receives a reference bias. An intermediate electrode made of ohmic metal to the graphene layer is provided between the two gate electrodes. The second gate electrode receiving the reference bias suppresses the hole injection into the channel beneath the first gate electrode.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: August 22, 2017
    Assignees: Sumitomo Electric Industries, Ltd., Tohoku University
    Inventors: Yasunori Tateno, Maki Suemitsu, Hirokazu Fukidome
  • Patent number: 9722085
    Abstract: A transistor includes a channel layer in which a plurality of graphene whose edge portions are terminated with modifying groups different from each other are bonded to each other; a gate electrode formed on the channel layer via a gate insulating film; and a source electrode and a drain electrode formed on the channel layer.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: August 1, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Shintaro Sato, Hideyuki Jippo, Mari Ohfuchi
  • Patent number: 9712152
    Abstract: A circuit for controlling power supply includes a first switch situated between a first power supply and a first node coupled to a circuit block, a second switch situated between a second power supply having a voltage value different than the first power supply and a second node coupled to a back gate of a transistor of the circuit block, a third switch situated between the first node and the second node, and a control unit configured to place the second switch in an “on” state and the third switch in an “off” state during an “on” state of the first switch, and to place the second switch in an “off” state and the third switch in an “on” state during an “off” state of the first switch.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: July 18, 2017
    Assignee: SOCIONEXT INC.
    Inventor: Atsushi Okamoto
  • Patent number: 9667138
    Abstract: An electronic device includes a transistor having a body and a body biasing circuit. The body biasing circuit includes a threshold estimator circuit to estimate a threshold voltage of the transistor and a comparison circuit to compare the threshold voltage of the transistor to a reference threshold voltage and to generate a comparison signal based thereupon. A bias adjust circuit generates a body biasing voltage that biases the body of the transistor as a function of the comparison signal, the body biasing voltage being a voltage that, when applied to the body of the transistor, adjusts the threshold voltage thereof to be equal to the reference threshold voltage.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: May 30, 2017
    Assignee: STMICROELECTRONICS (SHENZHEN) R&D CO. LTD
    Inventors: Min Chen, Wen Liu
  • Patent number: 9632126
    Abstract: An integrated circuit includes an operational circuit and a test circuit for measuring a leakage current associated with all or part of the operational circuit. The leakage current measurement circuit may include a mirror circuit configured to mirror leakage current to a current-to-voltage converter and an analog-to-digital converter configured to convert the analog voltage representative of the leakage current developed by the current-to-voltage converter to a digital value.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: April 25, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kun-Yong Yoon, Jae-Jin Park, Ji-Hwan Hyun
  • Patent number: 9577636
    Abstract: A semiconductor device may be provided. The semiconductor device may include a first switching control signal generation circuit configured to generate a first switching control signal which is enabled in synchronization with a time when a first delay period has passed from a time when a power-down mode is entered. The semiconductor device may include a second switching control signal generation circuit configured to generate a second switching control signal which is enabled during a period from a time when a read operation mode or a write operation mode is entered to a time when a second delay period has passed.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: February 21, 2017
    Assignee: SK hynix Inc.
    Inventor: Yun Seok Hong
  • Patent number: 9543941
    Abstract: Radio-frequency (RF) switch circuits are disclosed providing improved switching performance. An RF switch system includes at least one field-effect transistor (FET) disposed between a first node and a second node, each FET having a respective gate and body. A resonance circuit connects the body of each of the at least one FET to a reference node. The resonance circuit may be configured to behave as an approximately closed circuit at low frequencies below a selected value and an approximately open circuit at an operating frequency, wherein the approximately closed circuit allows removal of surface charge from the body to the reference node.
    Type: Grant
    Filed: July 6, 2013
    Date of Patent: January 10, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventors: Haki Cebi, Fikret Altunkilic
  • Patent number: 9503074
    Abstract: In some method and apparatus embodiments, an RF circuit comprises a switch transistor having a source, a drain, a gate, and a body. A gate control voltage is applied to the gate of the switch transistor. A body control voltage is applied to the body of the switch transistor. The body control voltage is a positive bias voltage when the switch transistor is in an on state. In some embodiments, an RF circuit comprises a control voltage applied to the gate of the switch transistor through a first resistance and applied to the body of the switch transistor through a second resistance. The first resistance is different from the second resistance.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: November 22, 2016
    Assignee: Qualcomm Incorporated
    Inventors: Max Samuel Aubain, Clint Kemerling
  • Patent number: 9494987
    Abstract: An integrated circuit includes an input/output pad, an input circuit, and an output circuit. The input circuit is coupled to the input/output pad that receives input signals including a wake-up signal that indicates when the integrated circuit is to switch from a power-down mode to an active mode. The output circuit is coupled to the input/output pad that provides output signals to the input/output pad. The output circuit includes a first P channel transistor in a well having a drain coupled to the input/output pad, and a source coupled to a power supply terminal. The power supply terminal receives a first power supply voltage during the active mode and is decoupled from any power supply during the power-down mode. The well is coupled to the wake-up signal in response to the wake-up signal indicating a change from the power-down mode to the active mode.
    Type: Grant
    Filed: November 30, 2013
    Date of Patent: November 15, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Dzung T. Tran, Rishi Bhooshan, Rakesh Pandey, Fujio Takeda
  • Patent number: 9455728
    Abstract: A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: September 27, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jingdong Deng, Chung S. Ho, David Flye, Zhenrong Jin, Ramana M. Malladi
  • Patent number: 9443845
    Abstract: An integrated circuit comprises a transistor body control circuit for controlling a body of a bidirectional power transistor. The transistor body control circuit comprises switches connected between a body terminal and a first current terminal, with a control terminal for controlling the current flowing through the switch. The control terminal of the switch is connected to alternating current, AC capacitive voltage divider. The AC capacitive voltage dividers are connected to the control terminals and arranged to control the switches to switch the voltage of the body terminal as a function of the voltage between the first current terminal and the second current terminal. The integrated circuit further comprises a bi-directional power transistor connected to the transistor body control circuit.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: September 13, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Evgueniy Stafanov, Edouard Denis De Fresart, Hubert Michel Grandry
  • Patent number: 9425795
    Abstract: The present disclosure relates to a detection circuit formed as part of an integrated circuit. In one example, the detection circuit includes a signal generator configured to generate a reference signal, and an amplification circuit comprising a p-channel transistor and an n-channel transistor, wherein the amplification circuit is affected by a variability that also affects a functional circuit formed as part of the integrated circuit. The variability causes the p-channel transistor and the n-channel transistor to have different respective drive strengths. The amplification circuit is configured to receive the reference signal and to provide an amplified signal representative of a difference in the respective drive strengths, wherein the reference signal is more insensitive to the variability than the amplified signal. The present disclosure also relates to an integrated circuit and a method for detecting and compensating a transistor mismatch.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: August 23, 2016
    Assignee: Stichting IMEC Nederland
    Inventors: Maryam Ashouei, Tobias Gemmeke
  • Patent number: 9356506
    Abstract: A charge pump regulator at least includes a first charge pump circuit and a second charge pump circuit. In an enabled period, a first clock signal is provided to the first charge pump circuit. Consequently, the first charge pump circuit generates an output voltage to an output terminal of the charge pump regulator. In the enabled period, a second clock signal is provided to the second charge pump circuit. Consequently, the second charge pump circuit generates the output voltage to the output terminal of the charge pump regulator. In a first time interval of the enabled period, the first clock signal has a first frequency and the second clock signal is maintained at a fixed level. In a second time interval of the enabled period, both of the first clock signal and the second clock signal have a second frequency.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: May 31, 2016
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventor: Hsin-Liang Ho
  • Patent number: 9337174
    Abstract: According to one embodiment, a semiconductor device includes first to fourth circuit substrates. Each of the first to fourth circuit substrates includes a switching device. The first circuit substrate includes a first terminal unit and a second terminal unit set to a potential lower than a potential of the first terminal unit. The third circuit substrate includes a fifth terminal unit and a sixth terminal unit set to a potential lower than a potential of the fifth terminal unit. The first circuit substrate overlaps the third circuit substrate. The second circuit substrate overlaps the fourth circuit substrate. A direction from the first terminal unit toward the second terminal unit is reversely oriented with respect to a direction from the fifth terminal unit toward the sixth terminal unit.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: May 10, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kohei Hasegawa, Takashi Yamamoto
  • Patent number: 9323260
    Abstract: An internal voltage generation circuit including a voltage generator and a detection voltage generator. The voltage generator generates a temperature reference voltage signal whose level depends on an internal temperature, a division reference voltage signal whose level is constant regardless of the internal temperature, and a selection reference voltage signal obtained by detecting a level of an internal voltage signal. The detection voltage generator compares the division reference voltage signal and the selection reference voltage signal in response to the temperature reference voltage signal to generate a detection voltage signal controlling a pumping operation of the internal voltage signal.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: April 26, 2016
    Assignee: SK hynix Inc.
    Inventor: Jae Hoon Kim
  • Patent number: 9324876
    Abstract: A semiconductor device includes a first oxide semiconductor film over an insulating surface; a second oxide semiconductor film over the first oxide semiconductor film; a source electrode and a drain electrode in contact with side surfaces of the first oxide semiconductor film, side surfaces of the second oxide semiconductor film, and the top surface of the second oxide semiconductor film; a third oxide semiconductor film over the second oxide semiconductor film, the source electrode, and the drain electrode; a gate insulating film over the third oxide semiconductor film; and a gate electrode in contact with the top surface of the gate insulating film. A length obtained by subtracting a channel length between the source electrode and the drain electrode from a length of the second oxide semiconductor film in the channel length direction is 0.2 times to 2.0 times as long as the channel length.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: April 26, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki Kobayashi, Daisuke Matsubayashi