Abstract: A transistor has a gate electrode, a gate insulation layer structure, a channel layer and source/drain layers. The gate insulation layer structure includes a lower gate insulation layer, a control layer for controlling a threshold voltage of the transistor, and an upper gate insulation layer. The channel layer contacts a surface of the gate insulation layer structure and vertically overlaps the gate electrode. The source/drain layers are adjacent to but not contacting the gate electrode.

Abstract: Circuits and methods for protecting polarity-sensitive components, such as light emitting diodes, electrolytic capacitors or integrated circuits, operating from a DC current source including a DC motor, an inductor or relay having a positive terminal and a negative terminal for receiving current from the current source, a protection diode connected parallel with the positive and negative terminals of the motor in a reverse bias configuration, at least one polarity-sensitive component connected in parallel with the protection diode and the DC motor, and a polarity protection transistor connected either between the nominally positive current source terminal and the positive motor terminal, or between the nominally negative current source terminal and the negative motor terminal.

Abstract: An improved charge pump design useful in low power applications derives an alternative voltage from a supply voltage. The design can be constructed using PMOS manufactured according to standard processes such that triple well manufacturing processes are not required. The design can incorporate control gate circuitry to increase efficiency and decrease degradation due to the threshold voltage of the transistors used.

Abstract: Disclosed is a device having a transistor that includes a source, a drain, a channel region extending between the source and the drain, a gate disposed near the channel region, and a conductive member disposed opposite of the channel region from the gate. The conductive member may not overlap the source, the drain, or both the source and the drain.

Abstract: Circuits and methods are provided for facilitating transitioning of a digital circuit from backgate biased standby mode to active mode. The digital circuit includes a semiconductor substrate, multiple n-channel transistors disposed at least partially in one or more p-type wells in the semiconductor substrate, multiple p-channel transistors disposed at least partially in one or more n-type wells in the semiconductor substrate, and a backgate control circuit. The backgate control circuit is electrically coupled to the p-type well(s) and to the n-type well(s) to facilitate transitioning of the multiple n-channel transistors and the multiple p-channel transistors from backgate biased standby mode to active mode by automatically shunting charge from the n-type well(s) to the p-type well(s) until a well voltage threshold is reached indicative of a completed transition of the transistors from backgate biased standby mode to active mode.

Abstract: An integrated circuit is provided with adjustable transistor body bias circuitry and adjustable power supply circuitry. The adjustable circuitry may be used to selectively apply body bias voltages and power supply voltages to blocks of programmable logic, memory blocks, and other circuit blocks on the integrated circuit. The body bias voltages and power supply voltages may be identified by computer aided design tools. The body bias voltages may be used to reduce leakage currents and power consumption when high speed circuit block operation is not required. Reduced power supply voltages may also be used to reduce power consumption when high speed circuit block operation is not required. To ensure optimum switching speeds, circuit blocks for which high-speed performance is critical can be provided with minimal body bias voltage or no body bias and can be provided with maximum power supply levels.

Abstract: An unnecessary through current is suppressed and insufficiency of an output electric potential and increase in power consumption are suppressed in a power supply circuit using a charge pump method. In order to suppress a reduction in an output electric potential VPP as well as suppressing transient through currents I1 and I2 when a clock DCCLK is inverted, resistances R1 of a wiring 11, R2 of a wiring 12 and R4 of a wiring 14 are set so as to satisfy relations R4>R1 and R4>R2. That is, the through currents I1 and I2 can be suppressed by reducing the resistances R1 and R2 so that electric potentials V1 and V2 are quickly inverted when the clock DCCLK is inverted. Also, the through current I1 can be suppressed to suppress the reduction in the positive output electric potential VPP by setting the resistance R4 to be larger than either of the resistances R1 and R2.

Abstract: A circuit and a method for adjusting the performance of an integrated circuit, the method includes: comprising: (a) measuring the performance of a first monitor circuit having at least one field effect transistor (FET) of a first set of FETs, each FET of the first set of FETs having a designed first threshold voltage; (b) measuring the performance of a second monitor circuit having at least one field effect transistor (FET) of a second set of FETs, each FET of the second set of FETs having a designed second threshold voltage, the second threshold voltage different from the first threshold voltage; and (c) applying a bias voltage to wells of the FETs of the second set of FETs based on comparing a measured performance of the first and second monitor circuits to specified performances of the first and second monitor circuits.

Abstract: A network having a current mirror comprising: a output transistor having a gate electrode for controlling a first current between a first electrode and a second electrode, the first electrode being coupled to a positive reference potential and the second electrode being connected to ground. A second transistor has a gate electrode for controlling a second current between a first electrode and a second electrode of the second transistor. The gate electrodes are connected together to produce the first current and the second current with equal current densities. A first portion of current from a current source is fed to the first electrode of the second transistor and a second portion of current from the current source is fed to a bias voltage producing circuit producing a bias voltage at the gate electrode of the output transistor for tracking variations in the first current passing through the output transistor.

Abstract: A charge pump type booster circuit generates a positive or negative boosted output voltage by switching booster paths one by one. This charge pump type booster circuit includes a plurality of booster paths, each of the plurality of booster paths including at least one booster capacitor, wherein a number of the booster capacitor at each of the plurality of booster paths is different between one booster path and the other booster path. This makes it possible to suppress an increase in a number of an external capacitor for setting an output voltage of the booster circuit constant.

Abstract: In order to resolve a problem of the conventional technique in which there is a charge pump capacitance which is not used when a boosting method of the charge pump is changed, in a charge pump circuit unit, a connection switching terminal selects a power source voltage, a logically-inverting buffer gate and a capacitor to conduct an operation of boosting the power source voltage so as to be twice the power source voltage, and a connection switching terminal outputs the boosted voltage as a boost control voltage. In a charge pump circuit unit, a connection switching terminal selects the boost control voltage outputted from the charge pump circuit unit, and a logically-inverting buffer gate and a capacitor conduct an operation of boosting the inputted voltage so as to be 3×VDD. An internal voltage is generated by outputting the boosted voltage to an internal power line via a NMOS transistor.

Abstract: A control circuit controls a power-source-voltage feed circuit, and controls a power source voltage fed to a target circuit. A reference-speed monitor monitors whether or not a delay time of a critical path in the target circuit is satisfies a required operational speed. A voltage-difference monitor monitors a difference between the power source voltage of the target circuit and a threshold voltage of the target circuit, to output the voltage difference information. The control circuit determines whether to increase or decrease the power source voltage based on a result of monitoring by the reference-speed monitor. The control circuit determines the change rate of the power source voltage so that the control rate of the power source voltage is proportional to the voltage difference information output from the voltage-difference monitor.

Abstract: A differential charge pump includes a differential charge pump unit, current adjusting device, and common mode voltage control circuit. The differential charge pump unit is used for generating a output voltage signal according to a pump-up signal and a pump-down signal. The current adjusting device is coupled to the differential charge pump unit for providing an adjusting current signal to the differential charge pump unit as the pump-up signal and pump-down signal are both enabled or disabled. The control circuit is coupled to the differential charge pump unit for outputting a feedback signal to the differential charge pump unit according to the output voltage signal.

Abstract: A method and circuit for providing a bias voltage to a MOS device is disclosed. The method and circuit comprise utilizing at least one diode connected circuit to provide a voltage that tracks process, voltage and temperature variations of a semiconductor device. The method and circuit includes utilizing a current mirror circuit coupled to the at least one diode connected circuit to generate a bias voltage for the body of the semiconductor device from the voltage. The bias voltage allows for compensation for the process, voltage and temperature variations.

Abstract: Provided is a semiconductor device for performing charge pumping. The semiconductor device may include a first pumping unit, a second pumping unit, and a controller. The first pumping unit may be configured to output a boosted voltage via an output node by using a first input signal and the initial voltage, where the boosted voltage is greater than an initial voltage. The second pumping unit may be configured to output the boosted voltage via the output node by using a second input signal and the initial voltage. The controller may be configured to control the first and second pumping units. Each of the first and second pumping units may include an initialization unit, a boosting unit, and a transmission unit. The initialization unit may be configured to control a voltage of a boosting node to be equal to the initial voltage during an initialization operation. The boosting unit may be configured to boost the voltage of the boosting node based on the first and second input signals.

Abstract: A method, system, and apparatus circuit to generate CMOS level signal to track core supply voltage (VDD) level are disclosed. In one embodiment, a system of an integrated circuit includes an HHV generation circuit located in the integrated circuit to provide an HHV voltage signal to a subsystem circuit of the integrated circuit to replace a core voltage signal used by the subsystem circuit when the core voltage signal is below a specified value, an core voltage source located within the integrated circuit to provide the core voltage signal to the HHV generation circuit, and an external voltage source to provide an external voltage signal of an other entity located outside the integrated circuit to the HHV generation circuit. The system may include a pad driver circuit configured to associate the integrated circuit with the other entity.

Abstract: A current mirror circuit includes a reference current source that generates a reference current, a reference transistor, a mirror transistor and a ratioed body bias feedback unit. The reference transistor has a first node that is coupled to the output of the reference current source, a gate that is coupled to the first node and a second node coupled to a common voltage. The mirror transistor has a gate coupled to the first node. The ratioed body bias feedback unit generates a body bias voltage coupled to the body of the reference transistor and the body of the mirror transistor. The ratioed body bias feedback unit is configured to adjust the body bias voltage in relationship to the common voltage so that the reference transistor and the mirror transistor each have a threshold voltage within a predefined range.

Abstract: A body-bias voltage source having an output monitor, charge pump, and shunt. A shunt circuit having on/off control is coupled to the output monitor and to the output of the charge pump. Upon sensing that the output voltage of the charge pump is above a desired value, the output monitor may disable the charge pump circuit and may enable the shunt circuit to reduce the voltage at the output of the charge pump. When the voltage output of the charge pump is below the desired value, the output monitor may disable the shunt circuit and may enable the charge pump circuit. A shunt circuit having proportional control may be substituted for the shunt circuit with on/off control.

Abstract: An internal voltage detection circuit and an internal voltage generation device using the same are disclosed. The internal voltage detection circuit includes a first detect signal generator for generating a first detect signal to detect a level of an internal voltage corresponding to an operating temperature of a memory cell, a second detect signal generator for generating a second detect signal to detect a specific level of the internal voltage corresponding to a preset temperature, and a detect signal clamp unit for comparing a level of the first detect signal and a level of the second detect signal with each other and clamping the first detect signal according to a result of the comparison.

Abstract: A solar cell device includes a solar cell section configured to output a first voltage upon receiving light. A charge pump circuit includes a first charge pump. The first charge pump includes a first terminal and a second terminal. The first terminal is configured to receive the first voltage from the solar cell section, and the second terminal is configured to output a second voltage that is higher than the first voltage. An output section is configured to receive an output voltage output by the charge pump circuit. The charge pump circuit is formed on a single semiconductor substrate.

Abstract: A system to evaluate charge pump output may include a comparator to compare a charge pump output voltage to a reference voltage to generate a comparison result. The system may also include a divider to divide down a clock signal. The system may further include a logical conjunction unit to operate on the comparison result and the divided down clock signal.

Abstract: A voltage redoubling circuit, wherein said circuit relies on a voltage-detecting unit, an oscillating unit, an inversing unit, a first switching device, a second switching device, a third switching device, a fourth switching device, and a fifth switching device to pump a reference voltage to an output voltage. In such a way, a conducted memory cell can be quickly and accurately accessed via a circuit operated in a low voltage region by a single on-and-off signal rather than a number of pulse control signals.

Abstract: A reference voltage generating circuit comprises: a monitor circuit, including a low threshold voltage PMOS transistor, a low threshold voltage NMOS transistor, and a resistor having a predetermined resistance which are connected in series, for generating a reference voltage at one end; and an additional circuit for supplying a monitor current to the monitor circuit and for controlling the other end of the monitor circuit to be at a constant voltage, wherein a voltage value of the reference voltage is corrected within a range corresponding to a process fluctuation from a predetermined center value, based on the monitor current changing in response to the process fluctuation.

Abstract: Switched capacitor networks for power delivery to packaged integrated circuits. In certain embodiments, the switched capacitor network is employed in place of at least one stage of a cascaded buck converter for power delivery. In accordance with particular embodiments of the present invention, a two-stage power delivery network comprising both switched capacitor stage and a buck regulator stage deliver power to a microprocessor or other packaged integrated circuit (IC). In further embodiments, a switched capacitor stage is implemented with a series switch module comprising low voltage MOS transistors that is then integrated onto a package of at least one IC to be powered. In certain embodiments, a switched capacitor stage is implemented with capacitors formed on a motherboard, embedded into an IC package or integrated into a series switch module.

Abstract: Voltage regulator circuitry is provided that exhibits a high power supply rejection ratio and a wide output voltage range. The voltage regulator circuitry can regulate power supply voltages for circuitry on a programmable logic device such as transistor body bias circuitry and configuration random-access-memory array circuitry. The voltage regulator circuitry includes an n-channel metal-oxide-semiconductor drive transistor that is coupled between a power supply voltage terminal and an output terminal. The n-channel metal-oxide-semiconductor drive transistor has a gate that receives a control signal from an operational amplifier. A boost circuit generates an elevated power supply voltage for the operational amplifier. A programmable voltage divider is coupled to the voltage regulator's output. The operational amplifier produces the control signal by comparing a feedback signal from the voltage divider to a reference voltage.

Abstract: An integrated circuit is provided that has circuitry containing metal-oxide-semiconductor transistors with body terminals. The body terminals may be biased with an externally supplied body bias voltage that reduces power consumption. During power-up operations, the external body bias voltage may temporarily not be available. In this situation, boost circuitry may produce an internal power supply signal that may be used in place of the unavailable external body bias voltage, thereby reducing leakage currents and power consumption during power up. A multiplexer may be used in routing an appropriate body bias signal to the transistors. The boost circuitry and multiplexer may be controlled by control signals that are generated by control logic. The control logic may produce the control signals by monitoring external and internally generated power supply voltage levels during power up operations.

Abstract: A circuit for body biasing is provided. The circuit includes: (1) a p-type transistor having a first current terminal, which is coupled to a first voltage supply, a second current terminal, a control terminal, and a bulk terminal; and (2) an n-type transistor having a first current terminal, which is coupled to a second voltage supply different from the first voltage supply, a second current terminal, a control terminal, and a bulk terminal, wherein the bulk terminal of the p-type transistor, the second current terminal of the p-type transistor, and the control terminal of the n-type transistor is coupled to a first node, wherein the control terminal of the p-type transistor, the bulk terminal of the n-type transistor, and the second current terminal of the second transistor is coupled to a second node different from the first node.

Abstract: A dual mode charge-pump circuit and associated method and apparatuses for providing a plurality of output voltages, using a single flying capacitor, the circuit including a network of switches that is operable in a number of different states and a controller for operating said switches in a sequence of the states so as to generate positive and negative output voltages together spanning a voltage approximately equal to the input voltage and centered on the voltage at the common terminal, in a first mode and positive and negative output voltages each up to substantially the input voltage in a second mode.

Abstract: A circuit for biasing the bulk of a MOS transistor, including a capacitive element connecting the bulk of the MOS transistor to a source of an voltage.

Abstract: A charge pump circuit and associated method and apparatuses for providing a plurality of output voltages using a single flying capacitor. The circuit includes a network of switches that are operable in a number of different states and a controller for operating the switches in a sequence of states so as to generate positive and negative output voltages together spanning a voltage approximately equal to the input voltage and centered on the voltage at the common terminal.

Abstract: A method includes receiving a set of voltages comprising at least a first voltage, a second voltage, and a third voltage and biasing a well of a transistor based on the extreme voltage of the set of voltages. Biasing the well of the transistor can include concurrently providing a first signal and a second signal based on a comparison of the first voltage and the second voltage and selectively coupling the well of the transistor to a source of the extreme voltage of the set of voltages based on the first signal, the second signal, and the third voltage. An electronic device comprises a transistor and a power switching module. The power switching module includes a set of inputs, each input configured to receive a corresponding one of a set of voltages comprising at least a first voltage, a second voltage, and a third voltage, and includes an output coupled to a well of the transistor, the output configured to provide the extreme voltage of the set of voltages.

Abstract: Provided are an internal voltage initializing circuit for use in a semiconductor memory and a driving method thereof, which are capable of preventing a back bias voltage from abnormally increasing due to a pumping operation of a VPP pump according to a change in a level of a power-up signal. The internal voltage initializing circuit includes: a high voltage initializing unit for selectively connecting a power supply voltage terminal an a high voltage terminal in response to a power-up signal; and a back bias voltage initializing unit for selectively connecting a ground terminal and a back bias voltage terminal in response to a signal produced by delaying the power-up signal by a predetermined time.

Abstract: A body biasing control circuit capable of being shared by a plurality of macro blocks and can independently control body voltages of a plurality of macro blocks. The body biasing control circuit includes a lookup table for storing a plurality of indexes where each index is associated with a body voltage appropriate for an operating state of a corresponding macro block. A control unit receives a corresponding index from the lookup table and generates a plurality of body voltages appropriate for an operating state of a macro block corresponding to the index and supplies the body voltages to the macro block.

Abstract: An active charge pump circuit may include a charge pump circuit, a control circuit, and a charge transfer circuit. The charge pump circuit may generate a charge pumping voltage in response to an active enable signal. The control circuit may generate a charge transfer control signal varying between a ground voltage and a boosted power supply voltage that is twice as much as a power supply voltage in response to the active enable signal. The charge transfer circuit may output the charge pumping voltage as an active voltage in response to the charge transfer control signal.

Abstract: An LCD driving circuit comprising an over-voltage protection circuit includes an input terminal to receive an input voltage, a voltage-dividing circuit, a voltage-stabilizing circuit including a voltage-stabilizing element, a control circuit, a switching element, and an output terminal. The voltage-dividing circuit provides a reference voltage according to the input voltage to the voltage-stabilizing circuit, the voltage-stabilizing circuit determines whether the voltage-stabilizing element conducts according to the reference voltage, and the control circuit controls the switching element to switch on or off according to a working stage of the voltage-stabilizing element to determine whether the output terminal outputs an output voltage.

Abstract: A semiconductor integrated circuit that suppresses steep changes of an output voltage when starting of a charge pump circuit to suppress transient displacement of output of a circuit block operating independently of the charge pump circuit is provided. A semiconductor integrated circuit has: a charge pump circuit which charges a first capacitor with an input voltage, transfers a charge accumulated in the first capacitor to a second capacitor, outputs, as an output voltage, a voltage of the second capacitor, and is capable of changing over a capability of charging the second capacitor; a first circuit block that receives a positive voltage and a grounding potential; and a second circuit block that receives the positive voltage and the output voltage of the charge pump. The semiconductor integrated circuit suppresses the charging capability by the charge pump circuit when starting of the charge pump circuit.

Abstract: A voltage multiplier includes a control circuit that generates first and second signals in phase opposition and a charging section. The latter comprises a first capacitor having a first terminal coupled to the first signal and a second capacitor having a first terminal coupled with the second signal. The multiplier includes respective parasitic capacitances placed respectively between the capacitors and a reference voltage. The charging section is coupled with an input voltage and is suitable for producing an output voltage that is a multiple of the constant voltage. The multiplier comprises a switch that selectively connects the parasitic capacitances to carry out a charge transfer from one parasitic capacitance to the other.

Abstract: A memory device of the irreversibly electrically programmable type is provided with a memory cell having a dielectric zone disposed between a first electrode and second electrode. An access transistor is connected in series with the second electrode, and an auxiliary transistor is connected in series with the first electrode. The auxiliary transistor is biased to have a saturation current which is lower than a saturation current of the access transistor when both the auxiliary and access transistors are actuated. A number of the memory cells are arranged in a memory plane to form the memory device.

Abstract: A method and circuit for changing a threshold voltage of a transistor. The circuit includes a sense circuit coupled to a switching transistor, a circuit transistor and to one terminal of a resistor. The other terminal of the resistor is connected to a body contact. The switching transistor directs current along one of two different paths in response to an input voltage sensed by the sense circuit. When the switching transistor directs a first current along one path, the first current is steered towards the resistor and flows through the resistor in one direction and when the switching transistor directs a second current along the other path, the second current is directed towards the resistor and flows through the resistor in the opposite direction from the first current. Steering the currents varies the potential of a body with respect to the potential at the source of the circuit transistor.

Abstract: A charge pump circuit that supplies current to an offset current of an output signal for an oscillating circuit is disclosed. The charge pump circuit includes a first switch and a second switch. The first switch is coupled to a gate of an output diode that provides a charge up current from the charge pump circuit. A second switch is coupled to an anode of the output diode and supplies the charge up current to the output diode. The first switch comprises a first state and the second switch comprises a second state that is opposite the first state. Thus, when the second switch is on, the first switch is off. The charge pump circuit also includes a capacitance to hold a bias voltage when the first switch is off.

Abstract: Semiconductor integrated circuit apparatus and electronic apparatus having a leakage current detection circuit where arbitrarily set leakage current detection ratio does not depend on power supply voltage, temperature, or manufacturing variations, and where leakage current detection is straightforward. Semiconductor integrated circuit apparatus extracts a stable potential from the center of two NchMIS transistors, amplifies drain current of an NchMOS transistor taking this potential as a gate potential to a current value of an arbitrary ratio using current mirror circuit, makes this current value flow through NchMOS transistor with the gate and drain connected, and applies drain potential of this NchMOS transistor to the gate of leakage current detection NchMOS transistor.

Abstract: An integrated circuit includes a substrate, a storage device formed in the substrate to hold bias settings, and operational blocks formed in the substrate, each operational block including an operational circuit and a charge pump to provide well bias voltages to the operational circuit in response to one or more of the bias settings. A method for testing an integrated circuit having two or more operational blocks includes: (a) determining a maximum operating speed of each of the blocks at a minimum supply voltage; (b) selecting a block that has a slow operating speed; (c) selecting a well bias to speed up the selected block; (d) selecting a supply voltage to meet a target operating frequency at the selected well bias and measuring power; (e) repeating acts (b)-(d) while the measured power is less than a baseline power; and (f) saving the selected well bias and supply voltage settings for operation of the integrated circuit.

Abstract: A circuit including a charge pump and regulation circuitry is described. The output of the charge pump is connected to provide a first output signal that is connectable to drive a load. A diode is connected to provide a second output signal of lower voltage from the first output signal. The regulation circuitry is connected to the second output level and is connectable to the charge pump to regulate its output. The circuit also includes a current source connectable from the second line to ground, where control circuitry connects the current source to the second line when the first line is connected to the load.

Abstract: Techniques of providing a low output voltage, high current capability charge pump are given. The charge pump has multiple capacitors along with switching circuitry. In an initialization phase, the first plate of each of the capacitors is connected to receive a regulator voltage and the second plate of each capacitor is connected to ground. In a transfer phase, the capacitors are connected in series, where, for each capacitor after the first, the second plate is connected to the first plate of the preceding capacitor in the series. The output voltage of the pump is from the first plate of the last capacitor in the series. Regulation circuitry generates the regulator voltage from a reference voltage to have a value responsive to the output voltage level of the pump.

Abstract: A multi-stage voltage multiplication circuit and methodology are provided which use a multi-stage charge pump boosting circuit (210) and two-stage pass gate circuit (220) having complementary power switches (M6, M9, M7, M10) to efficiently develop an output voltage (VOUT) that is higher than the input supply voltage (VDD). By using a two-stage complementary switch to connect boosted clock signals (P1, P2) from a charge pump (210) to the multiplier output (VOUT), return current from the storage capacitor (COUT) to the pumping capacitor (C1, C2) is blocked, thereby increasing power transfer efficiency, even at high clock frequencies. In addition, a boosted auxiliary voltage is generated by an additional boosting stage (230) and applied to the PMOS wells of the pass gate circuit (220), thereby preventing latch-up and backflow.

Abstract: Devices and systems for generating a bias current with a low minimum voltage, for example, are disclosed. One such device includes a first transistor having a source coupled to a voltage supply, a drain coupled to a first node, and a gate coupled to a second node, a second transistor having a source coupled to a reference, and a drain and a gate coupled to the first node, a third transistor having a source coupled to the reference, a drain coupled to a third node, and a gate coupled to the first node, a first resistive element coupled between the voltage supply and the third node, a second resistive element coupled between the voltage supply and the second node, and a fourth transistor having a source coupled to the reference, a drain coupled to the second node, and a gate coupled to the third node.

Abstract: An NchMOS transistor (1) is provided for muting of an output terminal (10) to which positive and negative output signals are outputted, and a mute switch circuit (3) is provided for controlling on/off of the transistor (1) by switching a voltage applied to the gate of the transistor (1). When muting is turned off, the back gate of the transistor (1) is biased by resistance division between resistors (R1 and R2) connected in series between the output terminal (10) and a predetermined negative potential (VSS).

Abstract: A voltage generator includes a bias signal generator generating first to fourth bias signals using a reference voltage, the first to fourth bias signals having different voltage levels. A driving signal generator receives the first and third bias signals to generate a pull-up signal in response to a voltage level of an output terminal and receiving the second and fourth bias signals to generate a pull-down signal in response to a voltage level of the output terminal. A voltage driver pulls up and pulls down a voltage level of the output terminal in response to the respective pull-up and pull-down signals. An auxiliary driving controller disables the pull-up signal when the voltage level of the output terminal is greater than that of the reference voltage and the pull-down signal when the voltage level of the output terminal is less than that of the reference voltage.

Abstract: It is an object of the present invention to reliably avoid problems with a load connected when stopping the operation of a charge pump circuit. The charge pump circuit is provided with a first switching element (S1) connected to a power supply, a second switching element (S2) connected to a load (102)and a capacitor element (Cp) connected between the first switching element (S1) and the second switching element (S2), and moves charge in a direction opposite to the direction in which charge moves during normal operation by inverting the phase of any one of clock signals applied to the first switching element (S1), second switching element (S2) and capacitor element (Cp) during normal operation.

Abstract: A boost voltage generating circuit of a semiconductor device includes a main pump circuit having a transfer transistor, the main pump circuit to boost a voltage of a boost node and to transfer charge from the boost node to an output node through the transfer transistor in response to at least one control signal, and an additional pump circuit configured to boost a voltage of a terminal of the transfer transistor.