Abstract: An internal voltage generating circuit may include a first pull up resistor activated by a first range signal and connected between a pull up voltage terminal and a pull up common node; a second pull up resistor activated by a second range signal and connected between the pull up voltage terminal and the pull up common node; a first pull down resistor activated by the first range signal and connected between a pull down voltage terminal and a pull down common node; a second pull down resistor activated by the second range signal and connected between the pull down voltage terminal and the pull down common node; a resistor string including a plurality of series resistors connected between the pull up common node and the pull down common node; and a voltage selection circuit select voltage in response to voltage selection information.

Abstract: An electronic device comprises a first component susceptible to a wearout effect, operation of which first component depends on an operating parameter, and a second component having an on-state and an off-state. The electronic device further comprises a time estimator for updating an estimate of an accumulated time the second component was in the on-state; and a controller for controlling the operating parameter on the basis of the accumulated time estimate so as to respond to the expected wearout effect. The first component and the second component may be the same, or the first component may have an on-state correlated to the on-state of the second component. The operating parameter may, for example, be a level or amplitude or correction value of one of the following: a voltage applied at the first component, an electric current fed to the first component, and a power provided to the first component. A method of operating such an electronic device is also disclosed.

Abstract: Example reference current distribution circuitry described herein include current mirrors having resistive elements of varying sizes between gate nodes of sense amplifier transistors along a voltage distribution line. Examples of counter coupling capacitances which may be coupled to the gate nodes of sense amplifier transistors are also described.

Abstract: Systems and methods for current sensing are described. The described systems and methods utilize a comparator for generating a current sense signal based on comparing an output current of a circuit against a reference current. The reference current is generated by using a current sourcing circuit that is connected to a controllable current source.

Abstract: An apparatus comprising a first line driver, a second line driver, a charge pump, and a control logic circuit coupled to the first line driver and the second line driver and configured to disable the charge pump when both a first control signal associated with the first line driver and a second control signal associated with the second line driver indicate a charge pump disable state. A network component comprising at least one processor configured to implement a method comprising receiving a first control signal and a second control signal, disabling a charge pump when both the first control signal and the second control signal indicate a charge pump disable state, and operating the charge pump to boost a voltage when the first control signal, the second control signal, or both indicate a charge pump active state.

Abstract: A reference voltage generator includes a first transistor and a second transistor coupled in series between a current supply and ground. Gate insulating films of the first transistor and the second transistor are made of the same type of film with the same thickness. Impurities contained in gate electrodes of the first transistor and the second transistor have different conductivity types, or have the same conductivity type and different concentrations. The first transistor has a greater gate width than the second transistor. The first transistor and the second transistor operate in a subthreshold region when a reference voltage is output outside.

Abstract: An input/output (I/O) driver is disclosed that employs a compensation circuit to limit the voltages across devices of the driver from exceeding a defined threshold to allow lower voltage devices to implement the operation of the driver. In particular, the driver employs a pull-up circuit including first and second switching devices coupled between a first voltage rail and an output of the driver. The driver employs a pull-down circuit including third and fourth switching devices coupled between the output and a second voltage rail. The I/O driver employs a compensation circuit configured to apply a compensation voltage to the node between the first and second switching devices and to the node between the third and fourth switching devices at the appropriate times to maintain the respective voltages across the second and third switching devices at or below a defined threshold, such as a reliability limit, during the operation of the driver.

Abstract: A digitally controlled non-inverting buck-boost DC-DC converter system including a non-inverting buck-boost DC-to-DC converter control module and a negative feedback module and applicable for a radio frequency circuit module is revealed. By locking a duty cycle to two specific levels, the non-inverting buck-boost DC-to-DC converter control module only needs a single operation mode to achieve the required effects. Simultaneously, pulse-skipping phenomenon is also avoided. Furthermore, a reference voltage is modified through a reference voltage correction circuit of the negative feedback module to eliminate errors between previous DC output voltage and the reference voltage. Thereby the DC output voltage can remain in a stable state so as to reduce operational defects during the mode transition.

Abstract: A semiconductor device includes an internal voltage generation unit configured to generate an internal voltage in response to an enable signal, an enable setting logic unit configured to define a starting time point for generating the internal voltage in response to the enable signal, a monitoring unit configured to monitor whether or not the internal voltage reaches a target level, and define an ending time point for generating the internal voltage in response to the monitoring result, and a measurement result signal generation unit configured to generate a measurement result signal corresponding to a developing time of the internal voltage in response to an output signal of the enable setting logic unit and an output signal of the monitoring unit.

Abstract: A limiting circuit for at least one semiconductor transistor. The circuit includes a limiting path which is coupled between a first power terminal and a second power terminal of the semiconductor transistor. The limiting path includes a limiting transistor. A node of the limiting path located between the limiting transistor and the second power terminal of the semiconductor transistor is coupled to a control terminal of the semiconductor transistor. A voltage source is coupled to the control terminal of the limiting transistor and is designed to apply a control voltage to said control terminal of the limiting transistor. The control voltage corresponds to a critical voltage for the voltage between the first power terminal and the second power terminal of the semiconductor transistor. The limiting transistor is switched to a conductive state when said critical voltage is exceeded at a power terminal of said limiting transistor.

Abstract: A bias circuit for generating an output bias current includes a first transistor, a passive component, a second transistor, and a bias current generator. The first transistor has a first node coupled to a first reference voltage, a second node, and a control node. The passive component is coupled between the first reference voltage and the control node of the first transistor. The second transistor has a first node coupled to the control node of the first transistor, a control node coupled to the second node of the first transistor, and a second node for providing the output bias current according to a current passing through the passive component. The bias current generator is coupled to the second node of the first transistor, and implemented for providing the first transistor with a bias current.

Abstract: A delay circuit for an RFID tag includes a power supply input and a power supply output and one or more delay circuits in cascade connection between the power supply input and the power supply output. A first delay circuit includes a passive circuit, a second delay circuit includes a ramp circuit, and a third delay circuit includes a current mirror circuit.

Abstract: The present invention provides a three-dimensional integrated circuit wherein generation of hot spot which makes a high temperature part as a result of intensively generated heat can be suppressed in. The integrated circuit apparatus comprises: a first circuit made of a memory circuit, a second circuit made of an arithmetic circuit, and a control circuit. The first circuit is partitioned into a plurality of circuit blocks according to the distance from the arranged position of the second circuit, and the control circuit controls the partitioned respective circuit blocks separately.

Abstract: A microcomputer includes a first switch coupled between a main power supply terminal and a power supply node, and a second switch coupled between an auxiliary power supply terminal and the power supply node. The microcomputer compares a voltage V1 of the main power supply terminal with a reference voltage VR1. When V1>VR1, the microcomputer turns on the first switch and turns off the second switch, and when V1<VR1, the microcomputer turns off the first switch, and turns on/off the second switch to gradually increase a voltage V3 of the power supply node. Thus, the operation of a clock generation circuit driven by V3 can be stable even when V3 is changed from V1 to V2.

Abstract: A voltage down converter includes a first driver having a first input terminal configured to generate a first voltage by using an external voltage in response to a first driving signal being inputted to the first input terminal, a control circuit configured to output the first driving signal to the first input terminal in response to a level of the first voltage, a second driver having a second input terminal configured to generate a second voltage by using the external voltage in response to the first driving signal or a second driving signal being inputted to the second input terminal, wherein the first driving signal is transferred from the first input terminal to the second input terminal through a conductive line, and a driving control circuit configured to generate the second driving signal and transferred to the second input terminal in response to a level of the second voltage.

Abstract: A microcontroller system includes a higher power reference voltage circuit and a lower power reference voltage circuit configured to draw less power than the higher power reference voltage circuit when enabled. The system includes a power state logic controller configured to enable the lower power reference voltage circuit to provide a first regulated voltage during a power saving mode, and, on exiting the power saving mode, enable the higher power reference voltage circuit to provide a second regulated voltage.

Abstract: A semiconductor device includes an internal voltage generation unit configured to generate an internal voltage in response to an enable signal, an enable setting logic unit configured to define a starting time point for generating the internal voltage in response to the enable signal, a monitoring unit configured to monitor whether or not the internal voltage reaches a target level, and define an ending time point for generating the internal voltage in response to the monitoring result, and a measurement result signal generation unit configured to generate a measurement result signal corresponding to a developing time of the internal voltage in response to an output signal of the enable setting logic unit and an output signal of the monitoring unit.

Abstract: A reference current generating circuit with high current mirror accuracy is provided by low power supply voltage operation. The reference current generating circuit includes a cascode current mirror circuit 1 outputting mirror currents I1 and I2, and a reference current Iref, a current-voltage converter circuit 2 converting the mirror current I1 into a voltage V1, a current-voltage converter circuit 3 converting the mirror current I2 into a voltage V2, a differential amplifier 4 in which the voltage V1 is input to a first input terminal and the voltage V2 is input to a second input terminal, a voltage-current converter circuit 5 converting a voltage V3 output from the differential amplifier 4 into currents I3 and I4, and a current-voltage converter circuit 6 converting the current I3 into a voltage V4 which is output to a gate of a transistor in the cascode current mirror circuit.

Abstract: Power control is facilitated. In accordance with one or more embodiments, power is supplied to power rails of an integrated circuit using a power control circuit including a power regulator and a reset circuit that is responsive to a supply voltage. The power regulator provides power to the power rails, based upon a control signal. The reset circuit controls the power regulator to provide power to the power rails independently of the control signal when the supply voltage is below an operational voltage level, and controls the power regulator to provide power to the power rails in response to the control signal when the supply voltage reaches the operational voltage level.

Abstract: An age compensation method and apparatus for an integrated circuit (IC). An IC may be configured to operate at an initial operating voltage at the beginning of its operational life. Various circuits may be used to detect aging of the IC, and indications of aging may be stored to determine the aging of the IC. The information indicative of the determined aging of the IC may be compared to an aging threshold. If the information indicates that the aging is greater than or equal to the determined aging threshold, the operating voltage of the IC may be increased. This process may be repeated over the life of the IC, increasing the operating voltage as the IC ages. Raising the operating voltage in response to aging may compensate for various age related degradation mechanisms that can occur over the operational life of the IC.

Abstract: A semiconductor apparatus according to aspects of the invention includes a power MOSFET including a main MOSFET and sensing MOSFET's. The main MOSFET and the sensing MOSFET's are formed on a semiconductor substrate, and a sensing MOSFET is selected for changing the sensing ratio and further for confining the sensing ratio variations within a certain narrow range stably from a low main current range to a high main current range. A semiconductor apparatus according to aspects of the invention facilitates reducing the manufacturing costs thereof, obviating the cumbersomeness caused in the use thereof, and confining the sensing ratio variations within a certain narrow range stably.

Abstract: A voltage regulator bypass circuit to control bypass of a voltage regulator of an integrated circuit device, the voltage regulator bypass circuit including a first voltage detector, a second voltage detector, and circuit. The first voltage detector to detect that a core circuitry voltage level is above a first threshold and to assert a first detect signal at an output in response to the detection. The second voltage detector to detect that an unregulated supply voltage is above a second threshold and to assert a second detect signal at an output in response to the detection. The circuit having a first input coupled to the output of the first voltage detector and a second input coupled to the output of the second voltage detector, the circuit to bypass the voltage regulator in response the output of the latch being cleared.

Abstract: TASK: to provide an internal voltage trimming circuit having a simple configuration and operated by a consumption current smaller than that using a comparator. MEANS FOR SOLVING THE PROBLEM: An internal voltage trimming circuit comprises a trimming controller using a change in a counting value of a clock according to a current flowing through a transistor of a power supply current source for a clock generator to trim an internal voltage generated by an internal voltage generator. The trimming controller counts a first counting value of the clock when a predetermined reference voltage is applied to a control terminal of the transistor and a second counting value of the clock when the internal voltage is applied to the control terminal of the transistor and controls the internal voltage generated by the internal voltage generator to substantially coincide the second counting value with the first counting value.

Abstract: An integrated circuit may include a signal generator configured to generate a switching signal and a switching unit coupled to the signal generator. The switching unit may be configured to generate a pulsed current based on the switching signal using a first voltage. The integrated circuit may also include an inductive unit coupled to the switching unit. The inductive unit may be configured to receive the pulsed current and to generate a second voltage different from the first voltage.

Abstract: Described herein is an integrated circuit which comprises: a switching voltage regulator (SVR), having one or more bridge drivers, to provide regulated power supply to a plurality of power domains; and a power control unit (PCU) operable to adjust switching frequencies of the SVR according to states of the plurality of power domains, wherein drive strength or active phase count of the one or more bridge drivers is also adjusted by a logic unit of the SVR when the switching frequencies of the SVR are adjusted.

Abstract: Systems, apparatus, and methods are provided for initializing a voltage bus. An exemplary system includes an input interface, a voltage bus, discharge circuitry coupled to the voltage bus, connection circuitry coupled between the voltage bus and the input interface, and a control module coupled to the connection circuitry and the discharge circuitry. The control module activates the discharge circuitry prior to activating the connection circuitry.

Abstract: Systems and methods for bi-modal and fine grained power delivery to an integrated circuit comprising functional blocks. A first power source is coupled to a functional block of the integrated circuit for supporting a first operating mode of the functional block. A second power source is coupled to the functional block for supporting a second operating mode of the functional block. The first and second operating modes can be high and low frequency modes respectively. The second power source can be derived from the first power source using on-die regulators or provided independently. A desired average throughput of the functional block can be achieved by controlling duty cycles of the first and second power sources.

Abstract: A reference-voltage generating circuit of an embodiment includes a first FET; a second FET; a first resistor in which one end is connected to a power supply while the other end is connected to a drain of the first FET; and a second resistor that is connected between the drain and a gate of the first FET, wherein a gate and a source of the second FET are connected, a drain of the second FET is connected to the gate of the first FET, the drain of the first FET outputs a reference voltage, and the source of the first FET and the source of the second FET are connected to a ground or another circuit.

Abstract: Various embodiments of the present invention relate to a voltage generator, and more particularly, to systems, devices and methods of configuring a charge pump system by incorporating an auxiliary charge pump to generate an intermediate voltage that is used to boost up a primary charge pump according to a level of an input supply voltage. The intermediate voltage has a higher level than that of the input supply voltage, and is provided to boost up the primary charge pump when the input supply voltage is determined to be lower than a threshold voltage. Such a charge pump based voltage generator is compatible to a wide input supply range, capable of sustaining a large output load and effectively reduces the chip estate.

Abstract: A voltage regulator bypass circuit to control bypass of a voltage regulator of an integrated circuit device, the voltage regulator bypass circuit including a first voltage detector, a second voltage detector, and circuit. The first voltage detector to detect that a core circuitry voltage level is above a first threshold and to assert a first detect signal at an output in response to the detection. The second voltage detector to detect that an unregulated supply voltage is above a second threshold and to assert a second detect signal at an output in response to the detection. The circuit having a first input coupled to the output of the first voltage detector and a second input coupled to the output of the second voltage detector, the circuit to bypass the voltage regulator in response the output of the latch being cleared.

Abstract: There are provided a bias circuit supplying different levels of bias power according to respective power modes through a simple circuit configuration, and a power amplifier having the same. The bias circuit includes: a bias setting unit setting a bias power voltage level by switching reference power having a pre-set voltage level determined according to a pre-set power mode; and a bias supply unit including a switching element performing switching according to the setting of the bias setting unit and supplying bias power having a voltage level determined according to a switching operation of the switching element.

Abstract: The present invention discloses a method, an apparatus, and a system for adaptively adjusting a voltage. The method includes: acquiring an internal temperature code of a system chip and a time sequence code of a system logic circuit, where the internal temperature code is detected by a temperature sensor and the time sequence code is output by a time sequence monitoring unit; selecting a time sequence reference calibration code from multiple configured time sequence reference calibration codes according to the acquired temperature code; and comparing the acquired time sequence code with the selected time sequence reference calibration code and determining, according to a comparison result, an adjustment voltage to be output for a system load. By using the foregoing method, the present invention can better reduce a power loss and achieve a better power reduction effect.

Abstract: An electric device and a control method of the same, the electric device including a load terminal, a constant voltage output unit to generate an output voltage to the load terminal, a feedback circuit having a plurality of feedback circuit elements to generate a feedback signal to the constant voltage output unit to adjust the output voltage, and a controller to set a power mode of the electric device and to generate a control signal according to an enable signal and the set power mode such that the control signal corresponds to one or more of the feedback circuit elements to adjust the feedback signal, wherein the enable signal corresponds to a level of the output voltage.

Abstract: An integrated circuit including a state retention node, a conductive clock network shielding and multiple state retention devices for maintaining a state of the integrated circuit during the low power state. The state retention node receives a state retention supply voltage which remains at an operative voltage level during a low power state. The conductive clock network shielding is distributed with clock signal conductors and is coupled to the state retention node. Each state retention device has a supply voltage input coupled to the clock network shielding so that it remains powered during the low power state. The state retention node may be implemented as a minimal set of conductive traces. A state retention buffer may be provided for buffering a power gating signal indicative of the low power state, in which the buffer has a supply voltage input coupled to the clock network shielding.

Abstract: Provided are a variable field effect transistor (FET) designed to suppress a reduction of current between a source and a drain due to heat while decreasing a temperature of the FET, and an electrical and electronic apparatus including the variable gate FET. The variable gate FET includes a FET and a gate control device that is attached to a surface or a heat-generating portion of the FET and is connected to a gate terminal of the FET so as to vary a voltage of the gate terminal. A channel current between the source and drain is controlled by the gate control device that varies the voltage of the gate terminal when the temperature of the FET increases above a predetermined temperature.

Abstract: An internal voltage generating circuit may include a first pull up resistor activated by a first range signal and connected between a pull up voltage terminal and a pull up common node; a second pull up resistor activated by a second range signal and connected between the pull up voltage terminal and the pull up common node; a first pull down resistor activated by the first range signal and connected between a pull down voltage terminal and a pull down common node; a second pull down resistor activated by the second range signal and connected between the pull down voltage terminal and the pull down common node; a resistor string including a plurality of series resistors connected between the pull up common node and the pull down common node; and a voltage selection circuit select voltage in response to voltage selection information.

Abstract: A voltage regulator circuit comprises active and standby amplifiers, first and second transistors, and a capacitor. The active amplifier has a negative input connected to a first reference voltage, and the standby amplifier has a negative input connected to a second reference voltage. The first reference voltage is greater than the second reference voltage. The first transistor has a gate connected to an output of the active amplifier and a drain connected to a voltage regulated output, and the second transistor has a gate connected to an output of the standby amplifier and a drain connected to the voltage regulated output. The capacitor is connected between a chip enable signal and the voltage regulated output.

Abstract: Current sources, systems including the current source, and methods for regulating and/or controlling a circuit using the current source. The current source is generally configured to (i) receive a reference current, a bias voltage and a feedback/input current and (ii) provide an output current. The systems generally include the current source, a circuit directly or indirectly receiving the output current, a bias source/generator configured to provide the bias voltage, and a current reference configured to sink or source a predetermined amount of current from or to the output current. The method generally includes (a) applying a bias voltage to the current source, the current source receiving an input current and providing an output current; (b) sinking or sourcing a reference current from or to the output current; (c) applying the output of the current source directly or indirectly to a regulated circuit; and (d) providing the input current from the regulated circuit.

Abstract: Disclosed is a switching voltage regulator circuitry controlled to supply a voltage to at least a portion of an integrated circuit (IC). Information corresponding to a current load for a different power state of at least a portion of the IC is received. The switching voltage regulator circuitry is controlled to adjust the voltage to a different value based at least in part on the received information. Disclosed is a voltage received for a power state of at least a portion of an IC having first logic to perform one or more functions and second logic integrated with the first logic. Information corresponding to a current load for a different power state of at least a portion of the IC is sent from the second logic to voltage regulator control logic to adjust the voltage to a different value.

Abstract: A circuit for downscaling voltage comprising: a voltage regulator; a voltage reference register configured to provide a voltage reference value; a voltage comparator configured to output a logical one if a supply voltage of the voltage regulator is greater than the voltage reference value, wherein a first input of the voltage comparator is coupled to output of the voltage regulator and a second input of the voltage comparator is coupled to output of the voltage reference register; an AND gate, where a first input of the AND gate is coupled to output of the voltage comparator and a second input of the AND gate is coupled to a voltage reference ready signal; a switch configured to close based on output of logical one from the AND gate; and a pull-down resistor configured to couple to the output of the voltage regulator only if the switch is closed.

Abstract: A voltage reducing circuit includes an internal power supply section configured to reduce an external power supply voltage supplied from an external power supply to an internal power supply voltage which is lower than the external power supply voltage based on a reference voltage. A first current control section is configured to control a current flowing through the internal power supply section when the internal power supply voltage is lower than a setting voltage. A second current control section is configured to control the current flowing through the internal power supply section when the internal power supply voltage exceeds the setting voltage.

Abstract: Disclosed herein is a pad controlling apparatus controlling current and voltage applied to a pad, the pad controlling apparatus including: a voltage drop unit dropping the voltage applied to the pad; a switching unit connected in parallel with the voltage drop unit; and a control unit comparing a level of the dropped voltage and first reference voltage with each other and turning on the switching unit on when the level of the dropped voltage is larger than the first reference voltage. According to the present invention, even though interrupt occurs from the outside, a chip may be normally operated.

Abstract: A semiconductor device includes a regulator including an operational amplifier configured of a current mirror and generating the second voltage V2 from a first voltage V1; and a control circuit that generates the current control signal OVDR, makes a current that is flowed by the current mirror increase by a first transition of the current control signal OVDR, and makes the current that is flowed by the current mirror decrease by a second transition of the current control signal OVDR. The control circuit includes a slew-rate processing unit that makes a second slew rate of the current control signal OVDR related to the second transition be smaller than a first slew rate of the current control signal OVDR related to the first transition.

Abstract: A first pump circuit generates a first voltage for decreasing the distance between primary electrodes. The first voltage is limited to a predetermined limit by a first limiter circuit. A second pump circuit generates a second voltage for keeping the distance between the primary electrodes constant. A third pump circuit generates the second voltage and has a supplying capacity smaller than the first one. The second voltage is limited by second and third limiter circuits. A ripple capacitor is charged up to the second voltage by the second pump circuit and the second limiter circuit within a period of time the first voltage is being generated. When a supplying voltage of the first pump circuit reaches to the first voltage, and a deformation stops, the second voltage is supplied by the third pump circuit and the third limiter circuit instead of the second pump circuit and the second limiter circuit.

Abstract: To provide an internal power supply circuit that supplies a power supply voltage to an internal circuit of a semiconductor device via an internal power supply wiring, the internal power supply circuit includes a plurality of power supply units connected in common to the internal power supply wiring and an internal-power-supply control circuit that selects either activation or deactivation with regard to at least a part of the power supply units.

Abstract: Various circuit board voltage regulators and methods of making and using the same are disclosed. In one aspect, a method of manufacturing is provided that includes fabricating at least one inductor in a circuit board and coupling a semiconductor chip to the circuit board. The at least one inductor is electrically coupled to the semiconductor chip. Regulator logic is electrically coupled to the at least one inductor, the regulator logic and the at least one inductor are operable to deliver a regulated voltage to the semiconductor chip.

Abstract: A linear voltage regulator includes a pair of amplifiers. A first amplifier of the pair is used in conventional fashion to generate a regulated output voltage by controlling an impedance of a pass transistor in the linear voltage regulator, the controlling being based on a difference between a reference voltage and a voltage at a first node in a voltage divider network connected between the output terminal of the voltage regulator and a ground terminal. The second amplifier of the pair compares the regulated output voltage and a voltage at a second node in the voltage divider network, and injects a proportional current into the first node. Generation of a regulated output voltage lesser than the reference voltage is thereby enabled.

Abstract: An integrated circuit device has a primary voltage regulator and an ultra-low power secondary voltage regulator. The ultra-low power secondary voltage regulator supplies voltage to certain circuits used for providing data retention and dynamic operation, e.g., a real time clock and calendar (RTCC) when the integrated circuit device is in a low power sleep mode. The primary voltage regulator provides power to these same certain circuits when the integrated circuit is in an operational mode.

Abstract: The present invention relates to circuits and methods for limiting the operating area of a transistor in a constant current source. The circuits and methods use a detector and a driver to limit the operating area of a transistor. The detector and driver have parameters selected so that, when the voltage at the drain of the transistor satisfies a reference condition, the driver causes drain current of the transistor to decrease. The reference condition is determined relative to the maximum safe drain-to-source voltage at the design drain current of the constant current source.

Abstract: The operating voltage of an integrated circuit (e.g., a processor) is changed in response to one or more conditions (e.g., a laptop computer is connected to an AC power source). Both the operating frequency and the operating voltage of the integrated circuit are changed. The voltage regulator providing the operating voltage to the integrated circuit is caused to transition between voltage levels using one or more intermediate steps. The integrated circuit continues to operate in the normal manner both at the new voltage and throughout the voltage transition.