Abstract: A semiconductor integrated circuit having an internal circuit group, which includes at least one internal circuit, includes a plurality of process monitoring circuits, each of which is disposed at a different location in the internal circuit group, each of the process monitoring circuits, which is operated in response to a power supply voltage, detecting monitoring data in the area where one of the process monitoring circuits is disposed, and a power supply voltage generating circuit generating the power supply voltage corresponding to the monitoring data, and supplying the power supply voltage to the internal circuit group.

Abstract: Methods of generating a program voltage for programming a non-volatile memory device include generating an initial voltage and generating a first ramping voltage in response to the initial voltage. The first ramping voltage has a ramping speed slower than the ramping speed of the initial voltage. A second ramping voltage is generated in response to the first ramping voltage. The second ramping voltage has a lower ripple than the first ramping voltage. The second ramping voltage is output as a program voltage for programming a non-volatile memory device. A program voltage generating circuit includes a program voltage generating unit configured to generate an initial voltage, a ramping circuit configured to generate a first ramping voltage responsive to the initial voltage, and a voltage controlling unit configured to generate a second ramping voltage having relatively low ripple and to output the first ramping voltage or the second ramping voltage responsive to a voltage level of the first ramping voltage.

Abstract: A battery-powered power supply system is disclosed that is fully compatible with PMU ASIC and USB power architectures as well as being backwards compatible with the non-PMU power architectures. A battery-powered power supply utilizes a battery source (e.g., two AA battery cells in series), in a circuit including a switching power supply IC with a programmable variable output voltage and current limiter, along with a microcontroller. The invention also can include a flashlight or similar light source, which has utility beyond the obvious uses of a flashlight. The voltage and current supplied by the system of the present invention is controlled by the microcontroller to provide a variable voltage, variable as a function of time, if desired, during the charging operation. The flexibility afforded by a micro-controller controlled system allows the present invention to operate in different power or operational states and to adapt itself to the load demands.

Abstract: A semiconductor integrated circuit device with reduced consumption current is provided. A first step-down circuit stationarily forms internal voltage lower than supply voltage supplied through an external terminal. A second step-down circuit is switched between first mode and second mode according to control signals. In first mode, the internal voltage is formed from the supply voltage supplied through the external terminal and is outputted through a second output terminal. In second mode, operating current for a control system that forms the internal voltage is interrupted and an output high impedance state is established. The first output terminal of the first step-down circuit and the second output terminal of the second step-down circuit are connected in common, and the internal voltage is supplied to internal circuits.

Abstract: A delay circuit has a circuit structure dominated by an NMOS or a PMOS transistor. The delay circuit is supplied with, as a power supply voltage, an output voltage of a power supply voltage step-down circuit having a level generating circuit for generating a reference voltage obtained by an offset voltage and a manufacturing variation dependent voltage, and an m-time voltage generating circuit. A semiconductor device includes the delay circuit.

Abstract: An apparatus and method for providing a temperature compensated reference current in an electronic device is disclosed. The temperature compensated reference current is compensated for temperature and other circuit variations. The reference current is provided by an improved reference current generator and may be used in a memory device or any other desired circuit.

Abstract: A semiconductor device card, such as a memory card for example, includes a semiconductor device, a working voltage indicator, and a working voltage generator. A working voltage indicator is set to indicate a desired level of a working voltage corresponding to the semiconductor device. A working voltage generator generates the working voltage having the desired level and being coupled to the semiconductor device. Thus, the semiconductor device card is easily adaptable to accommodate various working voltages of the semiconductor device.

Abstract: An apparatus and method for supplying power to circuits of an integrated circuit (IC) from the wasted power in low-swing high-speed differential line drivers used in the IC, is disclosed. In a high speed line driver the load resistors of the driver are connected to a power supply, either the local power supply or the receiver power supply. DC power for the driver is supplied through these resistors. A large portion of this power, supplied from the power supply is wasted in the DC set-up circuit of the differential line driver. It is proposed to use this wasted power to power selected circuits of an IC. The use of this wasted power from the drivers for powering the circuits reduces the overall power dissipation of the system.

Abstract: As part of anti-fuse circuitry for a memory device, a preferred exemplary embodiment of the current invention provides a direct connection between an anti-fuse and a contact pad used to provide voltage to that anti-fuse. The contact pad also serves as a voltage source for at least one other part of the memory device. At least one circuit coupled to the anti-fuse is temporarily isolated from it in the event that a voltage present at the pad would damage the circuit or cause the circuit to improperly read the status of the anti-fuse. The contact pad is available during a probe stage of the in-process memory device, but once the device is packaged, access to that contact pad is prevented. At the backend of the production process, the anti-fuse may be accessed through a second pad, whose electrical communication with the anti-fuse is regulated.

Abstract: A bias generator for initializing a voltage controlled delay line by providing the voltage controlled delay line with a control signal having an initial voltage and monitoring the variable delay line for an output clock signal. The voltage of the control signal is varied from the initial voltage until an output clock signal from the voltage controlled delay line is detected by the bias generator.

Abstract: Consistent with an example embodiment, there is a method is for powering an integrated circuit. An integrated circuit comprises a chip within a package assembly, the chip includes a plurality of logic circuits each having at least one power input which should not receive a power voltage exceeding a predetermined maximum operating voltage. The method comprises measuring a power voltage supplied to the integrated circuit directly within the chip at the power input of at least one logic circuit. The power voltage is regulated such that the voltage supplied to the power input of at least one logic circuit of the chip is equal to the predetermined maximum operating voltage of this logic circuit.

Abstract: A reference voltage generator is provided. The reference voltage generator includes a bandgap reference circuit, a level shifter and a voltage divider. The bandgap reference circuit includes a current generator and a first BJT. The current generator outputs a reference current. The first BJT flows in the reference current from its emitter via a first resistor and has its collector and base grounded, such that a bandgap reference voltage and a first bias voltage can be output at the connection between the current generator and the first resistor and at the emitter of the first BJT. The level shifter is coupled to the bandgap reference circuit and outputs a second bias voltage higher than the first bias voltage and unequal to the bandgap reference voltage. The voltage divider is connected between the second bias voltage and the bandgap reference voltage and outputs a reference voltage therebetween.

Abstract: A power supply device is described comprising a DC voltage supply, a power section connected to the DC supply for supplying DC power from the DC voltage supply to first and second outlet ports for connection to a remote device via a cable connection, a voltage boosting circuit for generating a voltage above that of the DC supply, an energy absorbing circuit connected between an output of the voltage boosting circuit and a ground potential, and a diode connection means between the first outlet port and the energy absorbing circuit. The major components of the power supply device may be implemented as an integrated circuit.

Abstract: A charge pump circuit including a plurality of controlled charge pumps (CPs), a plurality of uncontrolled CPs, a plurality of control units, and an output unit is provided. Each controlled CP determines whether to provide charges to a node by a control signal, and each uncontrolled CP constantly provides charges to the node. The higher the node voltage at the node is, the more the controlled CPs not providing charge to the node are, so as to suppress the voltage of the node. In addition, the output unit regulates and outputs an output voltage according to the node voltage by the negative feedback.

Abstract: The composing circuit outputs a lower voltage out of voltages output from the constant voltage generation circuit and the dummy pump circuit as a voltage to the sensing circuit. The sensing circuit compares voltages to generate a pump activation signal for activating the pump circuit. Since when an external power supply voltage is a low voltage, the voltage applied to the sensing circuit will be an output voltage of the dummy pump circuit having the same output characteristics as those of the pump circuit in place of the reference voltage, no pump activation signal is generated. As a result, when the external power supply voltage is a low voltage, power consumption can be suppressed without uselessly outputting a pump activation signal.

Abstract: A semiconductor memory device includes a first pump clock generator configured to generate a first pump clock signal based on a power supply voltage. The device also includes a first charge pump configured to generate a first pump output voltage in response to the first pump clock signal. The device also includes a second pump clock generator configured to generate a second pump clock signal based on the first pump output voltage. The device also includes a second charge pump configured to generate a second pump output voltage in response to the second pump clock signal. The device also includes a switching unit configured to selectively connect the first charge pump to the second charge pump.

Abstract: A microcontroller unit includes a processor for generating a first control signal to start a comatose mode of operation for the microcontroller unit. Control logic responsive to the first control signal generates an enable signal at a first level and the control logic is further responsive to a second control signal for generating the enable signal at a second level. A voltage regulator generates regulated voltage from an input voltage. The voltage regulator shuts down to provide a zero volt regulated voltage responsive to the enable signal at the first level and powers up to provide a regulated voltage at an operating level responsive to the enable signal at the second level.

Abstract: A sub-bandgap reference voltage generator, generates a pair of variable voltages one having a positive temperature coefficient and one having a negative voltage coefficient. The pair of voltages are added to generate an output voltage whose value and temperature may be varied. To achieve this, a first voltage having a positive temperature coefficient is multiplied by a first ratio defined by first and second resistive values to generate a second voltage. A third voltage having a negative temperature coefficient is multiplied by a second ratio defined by third and fourth resistive values to generate a fourth voltage. The second and fourth voltages are added together to generate the output voltage of the sub-bandgap voltage generator.

Abstract: A circuit for reference current and voltage generation is provided. The circuit comprises a current bias circuit and a voltage reference circuit. Wherein, the current bias circuit receives an enable signal, provides a reference current, a bias signal and a startup signal when the enable signal is in an enabling state, and provides a first predetermined voltage and a second predetermined voltage when the enable signal is in a disabling state. The voltage reference circuit is electrically coupled to the current bias circuit. In addition, the voltage reference circuit enters into a turned-on state and provides a reference voltage after receiving the bias signal and the enable signal, and enters into a turned-off state after receiving the first and the second predetermined voltages.

Abstract: The pin number reduction circuit circuits and methodology of the present invention provide a higher pseudo power supply and a lower pseudo power supply for a digital functional section in mixed-signal IC, memory IC, and SOC including analog functional section and digital (or memory) functional section in order to reduce digital noise coupling. The circuit and methodology of the present invention basically includes resistors, capacitors, transistors, and amplifiers. It is noted that analog functional section is coupled between a positive power supply and a negative power supply, which are connected to two pins. One amplifier with a PMOS transistor and one resistor string provides a higher pseudo power supply, and the other amplifier with an NMOS transistor and the other resistor string provides a lower pseudo power supply so that a digital functional section is coupled between these pseudo power supplies.

Abstract: A reference ladder having a plurality of embedded, programmable discontinuity resistors for adjusting the output voltages at a plurality of output taps of the ladder. In an embodiment, each discontinuity resistor has a programmable resistance. The reference ladder is factory tested to determine the voltage outputs at a plurality of output taps. A difference between the measured output voltages and the nominal output voltages is calculated. A determination is made of optimized resistances of the discontinuity resistors in order to minimize the differences between measured and nominal output voltages. The discontinuity resistors are then programmed, with the desired resistances stored in a non-volatile memory of the reference ladder. The output of the reference ladder may be further adjusted by using a trimming network at the bottom of the ladder to add a uniform offset to all the output voltages of all the output taps.

Abstract: A voltage regulator as a stable power supply to internal circuits in a semiconductor memory device is provided. This regulator includes a comparing unit, a first driver transistor, a feedback unit, an auxiliary control unit, a first switch, a second switch, and a second driver transistor. The comparing unit compares a reference voltage with a feedback signal to control the first driver transistor and maintain the internal power supply at a stable level. The second driver transistor, controlled by the first and second switches responsive to a trigger signal corresponding abrupt current consumptions and the auxiliary control unit responsive to the comparing result, supplies sufficient and appropriate current to the internal circuits and prevents the internal power supply from excessive overshoot and drop-out.

Abstract: An internal voltage generating circuit for use in a semiconductor memory device includes a reference voltage input terminal to receive a reference voltage, a comparison unit to output a first internal voltage, the first internal voltage having a voltage level based at least in part on the reference voltage, a first feedback unit to receive the first internal voltage and an external voltage and to provide a first feedback internal voltage to the comparison unit, a loading circuit to output a second internal voltage, and a second feedback unit to receive the second internal voltage from the loading circuit and to provide a second feedback internal voltage to the comparison unit.

Abstract: A current source circuit includes a voltage output section which outputs a voltage signal; a current source section and a conversion section. The current source section has at least one current source block comprising a plurality of current sources, each of which outputs an output current. The conversion section is provided between the voltage output section and the current source section and outputs a reference current to the plurality of current sources of the at least one current source block based on the voltage signal such that the output current from each of the plurality of current sources is set based on the reference current.

Abstract: An internal voltage generating apparatus adaptive to a temperature change includes a reference voltage circuit including a complementary to absolute temperature (CTAT) type transistor and a proportional to absolute temperature (PTAT) type transistor for generating a first to a third initial reference voltage signals. A buffer circuit for buffering a first, a second and a third initial reference voltage signal is included to generate a first, a second, and a third reference voltage signal in response to enable signals. An internal voltage generating circuit is included to generate an internal voltage signal based on the first, the second and the third reference voltage signal by using an inputted power voltage.

Abstract: A method and apparatus for an integrated circuit having a offset reference circuit block to receive an external voltage reference and output an offset reference voltage are described herein.

Abstract: In a bias voltage generating circuit for outputting through switching over a plurality of bias voltages and standby voltages provided for the respective bias voltages, a voltage return unit is provided for each bias voltage, and charges stored in the voltage return unit are supplied before power ON starts so that the bias voltage is approximated to a predetermined voltage. A drive controller drives the voltage return unit and a standby voltage generator, and a period of driving control is arbitrarily set by a register.

Abstract: A power gating circuit of a signal processing system includes a low dropout linear regulator, a control circuit, and an output circuit. The low dropout linear regulator includes a first transistor, an operational amplifier, a first resistor, a second resistor, and an output end. The output circuit includes a fourth transistor and a step-down circuit. The control circuit controls output voltage of the output circuit according to a control signal.

Abstract: One aspect of the invention relates to a voltage regulation process as well as to a voltage regulation system. A first voltage, present at an input of the voltage regulating system, is changed into a second voltage, which can be tapped at an output of the voltage regulation systems, with a first device for generating an essentially constant voltage from the first voltage, or a voltage derived from it. A further device is provided for generating a further voltage from the first voltage or a voltage derived from it, in particular a voltage which can be higher than the voltage generated by the first devices.

Abstract: A semiconductor integrated circuit device includes: a switching current observer for observing a switching current; a leakage current observer for observing a leakage current; a comparator which compares the switching current and the leakage current with each other; a threshold voltage controller for controlling a substrate bias voltage in order to make a ratio of the switching current and the leakage current constant; a delay observer for observing a delay amount; and a power supply voltage controller for controlling a power supply voltage in order to keep the delay amount in a predetermined range. In the semiconductor integrated circuit device, a process which enables the minimization of an operation power is carried out by controlling the threshold voltage to make the ratio of the switching current and the leakage current constant at a given clock frequency and controlling the power supply voltage to guarantee the operating speed.

Abstract: A method and an apparatus for controlling voltage level and clock signal frequency supplied to a system.

Abstract: A device for providing a supply voltage and a load modulation in a transponder with a unit having a resistance controllable by a control signal at a control input thereof, a unit for applying a load modulation signal to the control input, and a unit for applying a voltage limitation control signal to the control input.

Abstract: A design structure that includes at least one tunneling device voltage reference circuit for use in low voltage applications is disclosed. The tunneling device voltage reference circuit includes a pair of voltage dividing device stacks, one having a linear voltage output and the other having a non-linear voltage output. A feedback circuit supplies a regulated voltage to each of the voltage dividing stacks so that the output voltages of the two device stacks equalize. Once the feedback circuit has locked, any one of the device stack output voltages and the regulated voltage may be used as a voltage reference.

Abstract: Systems and methods of managing power provide for applying a voltage from a voltage regulator to a component of a computing system and reducing the voltage based on a power saving parameter that is dedicated to the component. The reduction can be in conjunction with the entry of the component into a low power state such as a standby state or an off state, where the power saving parameter defines a voltage such as a minimum operating voltage or minimum sustainable voltage for the component, respectively. In one embodiment, the component is a central processing unit.

Abstract: A regulator circuit having a voltage output terminal is provided. The regulator circuit includes a current mirror module, a plurality of source followers, and a switch. The current module receives a driving voltage, and has a first current terminal coupled to a driving current and a plurality of second current terminals, so that the driving current is copied to each second current terminal. Furthermore, each of second current terminals is coupled to one of source followers respectively. An output terminal of each source follower is coupled to an input terminal of next source, and the input terminal of the first source follower receives a control voltage. So that the source followers can determine whether the switch conducts the driving voltage to the voltage output terminal or not according to the copied driving current and the control voltage.

Abstract: A power supply circuit includes a first voltage regulator to generate a first supply voltage for a first circuit of a phase-locked loop and a second voltage regulator to generate a second supply voltage for a second circuit of the phase-locked loop. The first and second supply voltages are independently generated by the first and second voltage regulators based on the same reference signal. The first circuit may be a charge pump and the second circuit may be a voltage-controlled oscillator. Different circuits may be supplied with the independently generated supply voltages in alternative embodiments.

Abstract: A stabilized DC power supply circuit comprises an error amplifier circuit U1, an output amplifier circuit U2, an output voltage division circuit U3, and a reference voltage circuit U4. A bias current boost circuit U6 capable of stabilized operation is added to the DC power supply circuit. Since the feedback loop of the bias current boost circuit U6 is provided with a hysteresis function or an artificial hysteresis function by a large delay element, it is possible to adaptively control bias current without sacrifice of stability and realize a stabilized DC power supply circuit exhibiting high response and high stability with low current consumption.

Abstract: A flash memory device applies a low read voltage at increased flash memory device temperatures. A high read voltage is applied when a supply voltage is high, thereby maintaining a stable threshold voltage margin of a programmed cell or an erased cell. As a result, the reliability of the flash memory cell is enhanced.

Abstract: This invention provides a signal transmission circuit, a signal output circuit, and a termination method of a signal transmission circuit capable of preventing the re-reflection of the signal at a transmitting node of a transmission path even when an impedance of a signal output circuit does not match a characteristic impedance of a transmission path. On a signal transmission circuit composed of a transmission path, a signal output circuit connected to a transmitting node of the transmission path, and a signal receiver circuit connected to a receiving node of the signal transmission path, in order to prevent the re-reflection of an output signal of a signal output unit at the transmitting node via the receiving node, a correction current generator unit is provided for outputting correction current with a predetermined current amount and at a predetermined timing set in a current amount/timing control section, to the transmitting node.

Abstract: System and method for controlling voltage in a non-volatile memory system is provided. The system includes a voltage regulator that monitors an output voltage (VDD) and a mirror voltage (Vmirror). When the voltage VDD is greater than the voltage Vmirror beyond a threshold value, a control signal turns off a control transistor, which prevents the voltage VDD to increase beyond a certain value. The method includes comparing an output voltage (VDD) with a mirror voltage (Vmirror); and generating a control signal to turn off a control transistor if the voltage VDD is greater than the voltage Vmirror.

Abstract: The present invention relates to a method and circuit arrangement for controlling performance of an integrated circuit in response to a monitored performance indicator, wherein power supply of the integrated circuit is controlled based on said performance indicator. At least one of a noise level of the controlled power supply and a clock frequency generated in said integrated circuit is monitored and a respective control signal is fed back to the controlling function if the checking result is not within a predetermined range. Thereby, an simple and easily extendable automatic adaptation to process variations can be achieved.

Abstract: An IC incorporating a multiphase voltage converter with synchronized phase shift including a phase shift pin, a frequency select pin, a master clock pin, and a voltage regulator. The phase shift pin is coupled to a first voltage for a master mode or a first resistor for a slave mode. The frequency select pin is coupled to one of a second voltage and a second resistor. The master clock pin provides a master clock signal or receives an external clock signal. The IC provides the master clock signal at a frequency determined by the second resistor or otherwise at a default frequency. The voltage regulator operates in the slave mode at a phase shift relative to the external clock signal based on the first resistor and the second resistor or based on the first resistor and a default resistance if the second voltage is coupled.

Abstract: A circuit is described that generates multiple voltages each having a common reference point. The circuit uses a feedback control loop to generate a center voltage, a first voltage generator, and a second voltage generator. The first voltage generator generates a first high voltage related to the center voltage plus a first offset voltage and a first low voltage related to the center voltage minus the first offset voltage, where the first offset voltage is determined by a first control input to the first voltage generator. The second voltage generator generates a second high voltage related to the center voltage plus a second offset voltage and a second low voltage related to the center voltage minus the second offset voltage, where the second offset voltage is determined by a second control input to the second voltage reference generator. An example is also presented where the multiple voltage generator circuit is advantageously employed in a deserializer data acquisition system.

Abstract: A current driver includes a gate line having a first and second nodes, K driving transistors, a terminal and a voltage generation section. The terminal receives a first current. The voltage generation section generates a bias voltage according to a current value of the first current. The gate line receives, at one of the first and second nodes, the bias voltage generated by the voltage generation section. Gates of the K transistors are connected between the first and second nodes of the gate line. In the voltage generation section, the relationship between the first current and the bias voltage is adjusted in the first mode, according to a current value of an output current flowing in a first driving transistor of the K driving transistors, and in the second mode, according to a current value of an output current flowing in a second driving transistor of the K driving transistors.

Abstract: An apparatus and method for improving memory cell reliability is disclosed. The slew rate is reduced in an applied voltage signal used to program a memory cell when Fowler-Nordheim (FN) tunneling injection is detected. The applied programming signal is provided by a charge pump that is preferably a regulated charge pump. The charge pump is selectively controlled by a slew rate control circuit when FN tunneling injection is detected by a voltage level detection circuit at a predetermined threshold voltage level.

Abstract: A bandgap reference circuit, taking two or more power supplies as the input power supply for outputting a reference voltage, includes a first reference circuit, a second reference circuit, a power selection circuit and a switch circuit. The first and second reference circuits receive two respective power supplies for producing first and second voltages, respectively. As the power selection circuit takes the first power voltage level as the input voltage, the power selection circuit outputs a first control signal; while the power selection circuit takes the second power voltage level as the input voltage, the power selection circuit outputs a second control signal. The switch circuit is coupled to the power selection circuit, the first reference circuit and the second reference circuit. As the switch circuit receives the first control signal, it outputs the first voltage; while the switch circuit receives the second control signal, it outputs the second voltage.

Abstract: System and method for controlling voltage in a non-volatile memory system is provided. The system includes a voltage regulator that monitors an output voltage (VDD) and a mirror voltage (Vmirror). When the voltage VDD is greater than the voltage Vmirror beyond a threshold value, a control signal turns off a control transistor, which prevents the voltage VDD to increase beyond a certain value. The method includes comparing an output voltage (VDD) with a mirror voltage (Vmirror); and generating a control signal to turn off a control transistor if the voltage VDD is greater than the voltage Vmirror.

Abstract: A power supply apparatus of a semiconductor integrated circuit includes a power control device that detects a level of power supplied from the outside and outputs a control signal as information on the detected level, and a power supply device that controls an internal resistance component in response to an input of the control signal, controls the level of the power supplied from the outside, and supplies the power having the controlled level to circuit blocks.

Abstract: A load driving device according to the present invention includes: a first current generation section generating a first current in accordance with a driving current of a load; a second current generation section generating a predetermined second current; an integration section charging and discharging a capacitor in accordance with magnitude relation between the first current and the second current; a comparison section comparing a terminal voltage of the capacitor and a predetermined threshold voltage; and an output section generating a protection signal based on output logic of the comparison section. Such configuration permits appropriately preventing load burnout.

Abstract: A system and system for automatic voltage calibration is presented. A voltage calibration system includes three main units, which are a voltage level trimming unit, a trim detection unit, and a trim control unit. The three units work in conjunction with each other during a trimming operation in order to identify a tap voltage that is closest to a target voltage. In one embodiment, the voltage calibration system may be used to calibrate a voltage regulator. Upon commencement of calibration, the voltage regulator's feedback loop is open, and the target voltage is selected as the input for the feedback port of the amplifier. The voltage regulator serves as a voltage comparator that compares each tap voltage to the target voltage. When the calibration is complete, regulator's feedback loop is closed and the closest tap voltage to the target voltage is used as the regulator's input.