Abstract: A power supply circuit outputs different set potentials in response to control signals, wherein a voltage detecting circuit changes levels of a first reference potential and a second reference potential in response to inputs of control signals, and a clock generating circuit increases a frequency of the frequency divided clock signal when the levels of the first reference potential and the second reference potential are greatly changed in response to the inputs of the control signals.

Abstract: A compensation circuit for compensating an output impedance of at least a first MOS device over PVT variations to which the first MOS device may be subjected includes a first current source generating a first current having a value which is substantially constant and a second current source generating a second current having a value which is programmable as a function of at least one control signal presented to the second current source. A comparator is connected to respective outputs of the first and second current sources and is operative to measure a difference between the respective values of the first and second currents and to generate an output signal indicative of relative magnitudes of the first current and the second current. A processor connected in a feedback arrangement between the comparator and the second current source receives the output signal generated by the comparator and generates the control signal for controlling the second current as a function of the output signal.

Abstract: A load controller includes: a first input circuit which detects that a drive instruction signal by an operation of a drive instructing unit is less or equal to a first input threshold value; a first constant current source activated in accordance with the detection; a PWM signal supply unit that is activated by the first constant current source and supplies a PWM signal having a prescribed frequency and a duty ratio; a constant control signal supply unit that supplies a constant control signal during failure of the first input circuit or the first constant current source; a drive control unit that generates a PWM drive control signal in accordance with the PWM signal and generates a constant drive control signal in accordance with the constant control signal; and a load driving element that is controlled by the PWM drive or constant drive control signal to drive a load.

Abstract: A semiconductor device is disclosed which can perform a stable data inputting operation by overdriving a terminal supplying an internal voltage used as a drive voltage for a write driver such that the internal voltage is maintained in a predetermined range irrespective of a continuous write operation. The semiconductor device includes an internal voltage generator which generates an internal voltage corresponding to a predetermined reference voltage, and outputs the generated internal voltage to an internal voltage supply terminal, an overdriver which overdrives the internal voltage supply terminal for a predetermined period of time in response to an enable state of a control signal, the control signal being enabled in a write operation, and a write driver which is enabled in response to the control signal, to drive data transferred via a global data bus line using a voltage supplied from the internal voltage supply terminal, and to output the driven data to a local data bus line.

Abstract: The present invention provides a method and apparatus for compensating for temperature effects in the operation of semiconductor processes circuitry, such as reference circuits. The method operates on the realization that the second order effects such as “curvature” in the reference voltage variation over a temperature range is removed. The reference voltage variation over a temperature range can be represented as a straight line. This method provides for the trimming of the absolute voltage by scaling the reference voltage at a first temperature to the desired value by a temperature independent voltage. Then, at a second temperature, the output voltage slope is corrected by adding or subtracting a voltage which is always zero at the first temperature.

Abstract: A reference voltage generating circuit is described. The circuit includes a current generating section that generates a first current having a positive temperature coefficient, a voltage generating section that generates a voltage having a negative temperature coefficient, a synthesis section that generates a voltage which is the sum of a voltage having a positive temperature coefficient and developed across both terminals of a resistor, where the voltage has a negative temperature coefficient, and a compensation current generating section that generates a second current having a positive temperature coefficient. The current corresponding to the sum of said first and second currents is caused to flow through the resistor. The synthesis section generates a voltage which is a sum of a terminal voltage of the resistor by the sum current of the first and second currents and the voltage having a negative temperature coefficient.

Abstract: A switching control circuit, controlling a transistor, of a voltage generating circuit generating an output voltage of a target level from an input voltage applied to the transistor, comprising: an error amplifier circuit outputting an error voltage obtained by amplifying an error between a voltage according to the output voltage and a first reference voltage; a first comparison circuit comparing the error voltage with a second reference voltage to output a first control voltage; a second comparison circuit comparing the error voltage with a third reference voltage to output first and second voltages a charging and discharging circuit for charging and discharging a capacitor based on the first and second voltages; a third comparison circuit comparing a charged voltage of the capacitor with a fourth reference voltage; and a control circuit outputting a second control voltage for turning off the transistor according to a result of the third comparison circuit.

Abstract: Circuits and methods that improve the performance of voltage reference driver circuits and associated analog to digital converters are provided. A voltage reference driver circuit that maintains a substantially constant output voltage when a load current is modulated by an input signal is provided. The voltage reference driver circuit synchronously decouples a voltage regulation circuit from the load circuit when modulating events such as pulses caused by the load circuit during a switching interval are generated, preventing disturbance of the regulation circuitry and keeping its output voltage substantially constant.

Abstract: A temperature sensor includes a proportional to absolute temperature (PTAT) current generator configured to generate a first current proportional to temperature, a first complementary to absolute temperature (CTAT) current generator configured to generate a second current inversely proportional to temperature, a second CTAT current generator configured to generate a third current inversely proportional to temperature, and a temperature sensing unit configured to convert the first current, the second current, and the third current into a signal related to the temperature.

Abstract: A voltage reference generator includes multiple closed loop voltage references. Each of the closed loop voltage references uses a flash cell with a variable threshold voltage and a feedback loop to trim a reference voltage. The voltage reference generator includes sample and hold capacitors in output stages to allow reference voltages to be refreshed during a standby mode of operation.

Abstract: A system for automatically transforming a given synchronous circuit description into an equivalent and provably correct desynchronized circuit description. Included in the automated transformation are techniques for synthesizing a variability-aware controller using a two-phase protocol, techniques for synthesizing a variability-aware controller using gated clocks and testability circuits, techniques for synthesizing a variability-aware controller optimized for performance, techniques for initializing the synthesized controller, techniques for dynamically minimizing power requirements, and techniques for interfacing the desynchronized circuit with external synchronous circuits. Also disclosed are techniques for implementing a system for automatically transforming a synchronous circuit description into an equivalent and provably correct desynchronized circuit description within the context of an electronic design automation design flow.

Abstract: An integration type A/D converter in which a dynamic range is enlarged while keeping a simple circuit configuration is provided. Offset potential of an integrator is to be variable. Specifically, offset potential in proportion to input potential is supplied to the integrator. Since an operation point of the integrator is changed in accordance with the input potential, a dynamic range can be enlarged. Further, reference potential input to the integrator in discharging is to be variable. Specifically, reference potential having a constant difference from the offset potential is input to the integrator. Accordingly, time necessary for discharging and the input potential are in proportion, so that a simple circuit configuration which is one feature of the integration type ADC can be maintained.

Abstract: A circuit of generation of a reference voltage by a first MOS transistor connected to a first terminal of application of a supply voltage, the first transistor being in series with a second MOS transistor controlled by an input stage of a transconductance amplifier and their junction point defining an output terminal providing the reference voltage, a first current source connecting the first supply terminal to a gate of the first transistor, a second current source connecting the second transistor to a second terminal of application of the supply voltage, at least one third MOS transistor connecting the two current sources, and a capacitive element directly connecting the output terminal to a conduction terminal of the third transistor to vary the conduction of this third transistor in case of a variation in output voltage.

Abstract: A detector circuit and a negative voltage generating circuit capable of performing a high-speed operation are provided. A negative voltage generating circuit includes a charge pump circuit, a first voltage divider circuit that makes a voltage division between an output of the charge pump circuit and a power supply to output a detect potential, a reference voltage generating circuit that generates a reference potential, and a comparator circuit that compares the detect potential and the reference potential. The charge pump circuit is driven by an output signal of the comparator circuit and generates the negative voltage. In the first voltage divider circuit, NMOS transistors make the voltage division between the negative voltage and the power supply to obtain the detect potential.

Abstract: A method of distributing an electric quantity through an electronic circuit for local exploitation by at least one circuit block of the electronic circuit that includes providing in the electronic circuit first and second conductive lines, the first conductive line distributing a first electric potential and the second conductive line carrying a second electric potential that is a dedicated reference electric potential for the first electric potential, the first and second electric potentials corresponding to the distributed electric quantity, and locally exploiting the distributed electric quantity by at least one circuit block of the electronic circuit, by locally reconstructing the distributed electric quantity from the first and second electric potentials without perturbing them, particularly without either sinking or injecting any significant current from or into the first and second conductive lines.

Abstract: A current difference circuit is provided. The currents difference circuit provides an output current that is the difference of two input currents, while employing feedforward to clamp the output current. The current difference circuit brings the lower of the two input currents along with the higher of the two such that the difference between them is always constant if the difference is beyond the clamp range.

Abstract: An H-tree driver circuit has pull-up and pull-down current sources, each of which is implemented using a low-voltage-cascode topology.

Abstract: An internal reference voltage generating circuit that reduces a standby current and the number of pins of a semiconductor memory device, in which a reference voltage is provided to an input buffer that receives a signal through an input to which an on die transmitor resistor is connected, includes: a voltage dividing circuit outputting the reference voltage by a power voltage; a pull down driver connected to an end of the voltage dividing circuit; and a calibration control circuit comparing a voltage level of the input and a voltage level of an end of the voltage dividing circuit, and controlling the on resistor value of the pull down driver according to a result of the comparison. The internal reference voltage generating circuit is operated while the memory controller inputs a signal into a mode register set (MRS) to enable the internal reference voltage generating circuit and the output signal of the MRS is activated.

Abstract: Bandgap reference circuits capable operating in low voltage environments. In the bandgap reference circuit, a current generation circuit generates an output current obtained by combining a first current, a second current and a third current. The first current is converted from a first voltage and a first forward voltage of a first constant voltage generation element. The second current and the third current are both converted from a voltage difference between the first forward voltage and a second forward voltage of the second constant voltage generation element. A current-to-voltage generator converts the output current to an output voltage.

Abstract: A semiconductor device 2 has a plurality of elements. It also has an F-V table storing unit for low voltage threshold cells 31 for storing an F-V table TB11 of an oscillation frequency f1 relying on the plurality of elements and a power supply voltage EV to be supplied to the plurality of elements. It has a process sensor block 12 having at least one of the plurality of elements, for monitoring the oscillation frequency f1 relying on at least one element. It further has a selector 33 for setting the power supply voltage EV associated with the oscillation frequency f1, as the supply voltage to be supplied to the semiconductor device 2 by selecting according to the F-V table TB11. The F-V table TB11 is obtained by mutually relating the combinations of random number models ?n between an F-? table TB20 and an ?-V table TB30.

Abstract: By controlled increase of the supply voltage of sophisticated integrated circuits, the performance degradation over a lifetime may be significantly reduced. For this purpose, the upper limits of the supply voltage and the thermal design power are taken into consideration when increasing the supply voltage, which may then compensate for a typical performance degradation resulting in a more stable overall performance of integrated circuits. Thus, greatly reduced guard bands for parts classification may be used compared to conventional strategies.

Abstract: A circuit for supplying an operation voltage in a memory device includes a voltage supplying section that supplies a constant voltage to an output section through a first path and constantly discharges a portion of the supplied voltage through a second path. A third path section provides the supplied voltage to the output section through a third path in accordance with a controlling signal and a fourth path section discharges a portion of the voltage supplied from the voltage supplying section through a fourth path different from the second path in accordance with the controlling signal. A controller is configured to output the controlling signal that controlling the third and fourth path sections in accordance with an operation mode in the memory device. The circuit controls a dead zone window in accordance with a mode, thereby preventing an unnecessary consumption of power.

Abstract: A reference supply voltage circuit includes a detecting device for detecting a first reference voltage, a comparator, and a preventing circuit for preventing any false operation during pre-operation indefinite time interval. The comparator outputs a signal which controls an operation circuit whose supply voltage is a second reference voltage equal to or lower than the first reference voltage. The preventing circuit maintains the second reference voltage to a circuit reference potential when the first reference voltage is lower than a first predetermined voltage, sets the second reference voltage to a voltage equal to the first reference voltage when the first reference voltage is equal to or higher than the first predetermined voltage and lower than a second predetermined voltage, and sets the second reference voltage to a voltage proportional to the first reference voltage when the first reference voltage is equal to or higher than the second predetermined voltage.

Abstract: A high-speed digital multiplexer is disclosed, The multiplexer includes a plurality of input pins for receiving a plurality of digital input signals ad switching circuitry coupled to the input pins. The switching circuitry has respective outputs coupled to a common node and is operative to enable a selected one of the plurality of input pins, The multiplexer further includes a local signal converter having a circuit branch set to a common voltage. The branch is connected to the common node to sense changes in current corresponding to an input signal received by an enabled input pin. An output pin is coupled to the local signal converter, whereby the local signal converter is operative to produce voltage changes at the output corresponding to the sensed current changes.

Abstract: Compensation is provided for signal drop in bond wires of an integrated circuit (IC) while minimizing the number of external terminals in the IC package. A functional circuit provides an output signal (e.g., voltage) on a pad of the IC, which is connected to an external terminal on the package via a bond wire. A second circuit contained in the IC determines the signal drop in the bond wire by examining a parameter (e.g., current) proportional to a strength of the output signal at or before the pad in a transmission path of the signal. Thus, additional external terminals to sense the signal strength at a point external to the IC to provide compensation for the drop may not be required.

Abstract: A voltage supply circuit which conducts a current from a power supply into a current supply line comprises a plurality of current drive circuits connected in parallel to the current supply line each of which conducts current from the power supply into the current supply line. Different reference voltages are respectively given to the plurality of current drive circuits, each of which compares a comparison voltage corresponding to a generated voltage developed across load resistors with the respective reference voltage and, when the comparison voltage exceeds the respective reference voltage, stops supplying current.

Abstract: Embodiments of the invention comprise methods, apparatuses and systems for a dynamic bias control circuit configured to dynamically bias an amplifier. The dynamic bias control circuitry includes four branches. Each of the four branches includes a transistor operably coupled in series between a current source and a reference voltage. Each branch also includes a storage element having a first terminal and a second terminal and configured for selectively coupling the first terminal to the reference voltage, selectively coupling the first terminal to a node located between the current source and a drain of the transistor, selectively coupling the second terminal to the node, and selectively coupling the second terminal to an output.

Abstract: A device, having temperature compensation, includes a constant voltage provider for providing a constant voltage; and a compensating load coupled to the constant voltage provider for providing a resistive load to transform the constant voltage into a substantially constant current. The compensating load contains a resistor, having a negative temperature coefficient and coupled to the constant voltage; and a compensating unit, having a positive temperature coefficient and coupled in series to the resistor, for compensating a resistance variation of the resistor for a temperature variation.

Abstract: Provided are an apparatus and method for generating an internal voltage adaptively with respect to an external supply voltage. The apparatus includes a class detector and an internal voltage generator. The class detector outputs detection signals indicating a class of a plurality of classes, which correspond to predetermined voltages, to which an input external voltage belongs with respect to a first reference voltage. The internal voltage generator generates and outputs an internal voltage corresponding to the class to which the external voltage belongs as indicated by the detection signals.

Abstract: A power supply voltage control apparatus capable of freely setting a clock period setting margin according to a system clock frequency, and capable of converging power supply voltage to minimum power supply voltage where normal operation is possible in a short period of time without errors in operation of internal circuits in response to changes in the system clock frequency is provided. Power supply voltage control apparatus 100 is provided with frequency-dividing circuit 121 that frequency-divides the system clock at frequency-dividing ratio 1, frequency-dividing circuit 122 that frequency-divides the output of voltage control oscillator circuit 110 at frequency-dividing ratio 2, phase comparator/frequency comparator 130 that carries out phase comparison/frequency comparison on the respective output signals of frequency-dividing circuits 121 and 122, and controller 145.

Abstract: A device for adaptively controlling a voltage supplied to circuitry in substantially close proximity to the device, comprising a processing module, a first tracking element coupled to the processing module and producing a first value indicative of a first estimated speed associated with the circuitry, and a second tracking element coupled to the processing module and producing a second value indicative of a second estimated speed associated with the circuitry. The processing module compares each of the first and second values to a target value and causes a voltage output to be adjusted based on said comparison.

Abstract: A method for sensing current independently of variations in operating conditions is provided that includes generating a switch signal at a switching element. A reference signal is generated at a reference signal generator that is operable to track the switching element. A sense signal is generated based on the switch signal. An output current of the switching element is sensed based on a difference between the reference signal and the sense signal.

Abstract: An integrated circuit device and a method for providing distributed voltage regulation. The device includes a plurality of memory cell arrays and access circuitry dependent on one or more regulated voltages generated on the device and a plurality of pulsed digital distributed output units configured to generate the one or more regulated voltages. The device also includes a voltage regulator control logic configured to generate one or more control signals to control the distributed output units based, at least in part, on a comparison between one or more reference voltages and the one or more regulated voltages.

Abstract: In a reference voltage generation circuit, a bandgap reference circuit (BGR circuit) 1 includes diode element D1 and D2 having different current densities, three resistive elements R1, R2 and R3, a P-type first transistor Tr1 for supplying a current to a reference voltage output terminal O, a P-type second transistor Tr2 for determining a drain current flowing through the first transistor Tr1 by a current mirror structure, and a feedback type control circuit 11. The BGR circuit 1 is connected to a pull-down circuit 2. The pull-down circuit 2 includes a resistive element R4 and a P-type transistor Tr4 which are connected in series. The resistive element R4 is connected to a drain terminal of the second P-type transistor Tr2. The P-type transistor Tr4 has a gate terminal connected to the reference voltage output terminal O and a grounded drain terminal.

Abstract: A low-dropout regulator is provided. The low-dropout regulator includes a p-type depletion transistor as a pass device. The low-dropout regulator further includes switch circuitry and a charge pump that provides, at its output, a voltage greater than VDD. The source of the p-type depletion transistor is coupled to VDD. Under normal operating conditions, the bulk of the p-type depletion transistor is coupled to the source of the p-type depletion transistor. However, if the voltage at the gate of the p-type depletion transistor gets close to VDD, the switch circuitry causes the bulk of the p-type transistor to be coupled to the output of the charge pump instead.

Abstract: A low supply voltage band-gap reference circuit is provided, which includes a positive temperature coefficient current generation unit and a negative temperature coefficient current generation unit, and it is implemented by way of current summing. Through the current-mode temperature compensation technique, the present invention is able to reduce the voltage headroom and the number of operational amplifiers required by the conventional voltage-summing method, as well as the influence to the output voltage due to the offset voltage, thereby providing a stable and low voltage band-gap reference voltage level. In addition, by reducing the number of operational amplifiers and resistors of high resistance, the circuit area is reduced, and chip cost is saved.

Abstract: A voltage converting circuit is able to convert an input voltage generated by a system to a voltage capable of being utilized by a chip, avoids the defects of conventional switching regulators and linear regulators, and achieves voltage regulation with extremely high power efficiency and without off-chip components. The voltage converting circuit is adapted in systems with a plurality of similar or identical circuits.

Abstract: A charge pump control circuit and a control method for controlling charge pumps are disclosed. The output terminal of the charge pump is coupled to a load circuit. The charge pump control circuit includes a detecting and controlling circuit and a controlled oscillator. The detecting and controlling circuit is used to detect the load status of the load circuit and output a control signal according to the load status. The controlled oscillator receives the control signal and outputs at least one clock signal. According to the control signal to control a frequency of the clock signal, the charge pump control circuit controls the charge pump.

Abstract: Techniques for providing precise transconductance values are disclosed. For instance, an apparatus includes a slave transconductance cell and a control loop. The control loop provides a tuning voltage to the slave transconductance cell. Moreover, the control loop includes a master transconductance cell that generates a master output current, and a current amplifier that generates the tuning voltage based on an error signal. The error signal reflects a difference between a reference current and the master output current. Further, the current amplifier provides the tuning voltage to the master transconductance cell.

Abstract: There is provided a reference voltage generating circuit generating a reference voltage to be applied to a current-to-voltage converting circuit in order to compensate for an offset voltage of the current-to-voltage converting circuit converting an input current into a voltage and outputting the voltage, the reference voltage generating circuit including: a sampling conversion circuit having the same circuit characteristics as the current-to-voltage converting circuit and adding a predetermined offset to the reference voltage to generate an output voltage; and a comparator controlling the reference voltage so that the output voltage of the sampling conversion circuit is equal to a predetermined voltage, wherein the reference voltage is applied as an input to the sampling conversion circuit.

Abstract: Techniques pertaining to a circuit architecture capable of controlling a current source to a predefined precision are disclosed. According to one aspect of the present invention, an automatic trimming circuit is proposed to automatically trim a current generated from a current generator or circuit in accordance with a reference current. The automatic trimming circuit includes a comparator, an ADC and a register. The comparator that may be implemented as a subtractor finds a difference between a generated current and a reference current. The difference is then digitized to an n-bit precision. A digital representation of the difference is then kept in a register and used subsequently correct or modify the generated current to produce a precisely controlled current.

Abstract: A circuit provides a bandgap reference voltage that is substantially insensitive to temperature variations of an operating reference circuit.

Abstract: A dual mode voltage supply circuit (50) includes an active mode voltage supply circuit (58) and a passive mode voltage supply circuit (60). The active mode voltage supply circuit (58) is selectively operative to supply a voltage (57) based on mode control information (22). The active mode voltage supply circuit (58) is operative to provide a first current capacity. The passive mode voltage supply circuit (60) is operatively coupled to the active mode voltage supply circuit (58). The passive mode voltage supply circuit (60) is operative to supply the voltage (57) when the active mode voltage supply circuit (58) is not supplying the voltage (57). The passive mode voltage supply circuit (60) is operative to provide a second current capacity that is less than the first current capacity.

Abstract: A semiconductor circuit according to an embodiment of the present invention includes a first current mirror operating between a first power supply potential and a second power supply potential, a third power supply potential generated by the first current mirror, a second current mirror operating between the first power supply potential and the second power supply potential, a fourth power supply potential generated by the second current mirror, a circuit operating between the third power supply potential and the fourth power supply potential, and a first conductive type transistor and a second conductive type transistor connected to the circuit in parallel and connected to each other in series.

Abstract: A step-down power supply receives an external power supply voltage and supplies power at a reduced voltage from an output node to a load. The power supply also receives a reference voltage and a control signal indicating the whether the load is active or not. The reduced power supply voltage is held equal to the reference voltage by adjustment of the voltage at an internal control node. To prevent fluctuations in the reduced power supply voltage at active-inactive transitions of the load, the power supply includes circuitry for pulling the voltage at the internal control node both up and down, circuitry for leaking current from the output node to ground, circuitry for temporarily raising and lowering the reference voltage, or a capacitor coupling the reference voltage signal line to the control signal line.

Abstract: Circuits for forming the inputs of a latch are provided. In some embodiments, circuits for forming inputs of a latch comprise: a first transistor having a first gate terminal, a first drain terminal, a first source terminal, a first gate length, and a first common mode level at the first gate terminal, wherein the first gate terminal provides a data input to the latch; and a second transistor having a second gate terminal, a second drain terminal, a second source terminal, a second gate length, and a second common mode level at the second gate terminal, wherein the second gate terminal provides a clock input to the latch, the second drain terminal is coupled to the first source terminal, and the first gate length and the second gate length are sized so that the first common model level and the second common mode level are substantially equal.

Abstract: A multilevel voltage generator includes a first positive voltage generator generating a first output voltage using a first capacitor which receives a reference voltage and is charged to a voltage level corresponding to two times of the reference voltage, a second positive voltage generator generating a second output voltage and a third output voltage using a second capacitor and a third capacitor which receive the first output voltage and are charged to voltage levels corresponding to predetermined multiples of the reference voltage, and a negative voltage generator generating a fourth output voltage having predetermined negative voltage levels using a fourth capacitor which receives the reference voltage, the second output voltage, or the third output voltage and is charged to a voltage level corresponding to a negative voltage of the second or third output voltage.

Abstract: An internal voltage generator that generates an internal voltage for a Delay Locked Loop (DLL) and an internal clock generator including the same, and an internal voltage generating method for a DLL. The internal voltage generator includes a standby voltage generator that generates the DLL internal voltage as a reference voltage level, a controller that generates an active control signal in response to a power-down signal and an active signal, and an active voltage generator that generates the DLL internal voltage of the reference voltage level in response to the active control signal. After the power-down mode is ended, the active voltage generator is additionally operated during a predetermined time when the DLL is initially enabled. It is therefore possible to generate stabilized DLL internal voltages.

Abstract: A regulated mirror current source circuit has an output transistor, a regulator for controlling the output circuit, and a current mirror having two or more current paths. The first path of the mirror is coupled in series with a current path of the output circuit, and the second path is coupled to the regulator, to provide feedback. The feedback can provide better precision, or reduced component area. The circuit can include cascode transistors, and the regulator can have integral control. The output transistor gate-source voltage is overdriven to reduce “on” resistance of the output transistor. When the output transistor is a high voltage transistor, its area can be reduced without sacrificing compliance.

Abstract: A CMOS voltage reference circuit for a low voltage (1v), low power supply application is described. The circuit achieves a temperature coefficient of 31 ppm for a relatively large temperature range of ?40 C to 125 C. A combination of subthreshold current characteristics and moderate inversion operation of MOSFET's are utilized in conjunction to achieve a fairly stable temperature independent output voltage reference (VREF) from the circuit.