Abstract: A disclosed structure includes a section (e.g., an always on (AON) section) with at least one N-channel transistor (NFET) and at least one P-channel transistor (PFET). The structure further includes a switch with first and second inputs connected to receive positive and negative bias voltages, respectively, and first and second outputs connected to bias back gates of the NFET(s) and PFET(s), respectively, of the section. The structure is also configured to generate select signals for controlling the input-to-output connections established by the switch. In a power saving mode, these signals cause the switch to establish input-to-output connections resulting only in reverse back biasing of the NFET(s) and PFET(s) of the section. In a functional mode, these signals can cause the switch to establish input-to-output connections resulting in either forward back biasing or reverse back biasing. Also disclosed is a method of operating the structure.

Abstract: A system on chip includes a core configured to maintain a clock gating state; a plurality of header switch circuits configured to deliver a supply voltage, which is reduced from an external supply voltage, to the core in response to a plurality of control signals; and a voltage regulator configured to monitor the supply voltage, change logic levels of the plurality of control signals according to a difference level corresponding to a difference between the supply voltage and a preset target voltage, and output the plurality of control signals of which the logic levels have been changed to the plurality of header switch circuits.

Abstract: An integrated circuit die includes memory sectors, each memory sector including a memory array. The die includes a voltage regulator with a first transistor driven by an output voltage to thereby generate a gate voltage, the output voltage being generated based upon a difference between a constant current and a leakage current. A selection circuit selectively couples the gate voltage to a selected one of the plurality of memory sectors. A leakage detector circuit drives a second transistor with the output voltage to thereby generate a copy voltage based upon a difference between a variable current and a replica of the constant current, increases the variable current in response to the copy voltage being greater than the gate voltage, and asserts a leakage detection signal in response to the copy voltage being less than the gate voltage, the leakage detection signal indicating excess leakage within the memory array.

Abstract: An electronic device includes a controller, a clock generator, a first operation interface and a first functional unit. The controller generates a first clock enable signal, and then generates a first operation instruction. The clock generator generates a first clock according to the first clock enable signal. The first operation interface generates a first power supply signal according to the first clock, and translates the first operation instruction into a first operation signal. The first functional unit is enabled according to the first power supply signal, and starts to operate according to the first operation signal.

Abstract: A low-pass filter circuit is provided. The low-pass filter circuit includes a low-pass filter and a discharging circuit. The low-pass filter receives an input voltage signal through an input terminal of the low-pass filter circuit during a first period, performs a low-pass filter operation on the input voltage signal to generate a filtered voltage signal, and provides the filtered voltage signal to an output terminal of the low-pass filter circuit. The discharging circuit suppresses a leakage current flowing between the output terminal and a reference low voltage in response to the input voltage signal during the first period.

Abstract: The embodiments herein describe technologies for back-gate biasing of clock trees using a reference generator. A circuit includes a set of clock buffers and a programmable voltage reference generator to apply a voltage to a back gate of a transistor of the set of clock buffers.

Abstract: An aspect relates to an apparatus including a first and second power rails; a first set of power switch cells coupled to the first and second power rails, the first set of power switch cells being cascaded from an output to an input of a control circuit; and a second set of power switch cells coupled to the first and second power rails, the second set of power switch cells being coupled to one of a pair of cells of the first set, the first output, and the first input of the control circuit. Another aspect relates to a method including propagating a control signal via a first set of cascaded power switch cells to sequentially couple a first power rail to a second power rail; and propagating the control signal via a second set of power switch cells coupled between a pair of cells of the first set.

Abstract: An optical communication system includes an optical transmitter and one or more processors. The optical transmitter is configured to output an optical signal, and includes an average-power-limited optical amplifier, such as an erbium-doped fiber amplifier (EDFA). The one or more processors are configured to receive optical signal data related to a received power for a communication link from a remote communication system and determine that the optical signal data is likely to fall below a minimum received power within a time interval. In response to the determination, the one or more processors are configured to determine a duty cycle of the optical transmitter based on a minimum on-cycle length and a predicted EDFA output power and operate the optical transmitter using the determined duty cycle to transmit an on-cycle power that is no less than the minimum required receiver power for error-free operation of the communication link.

Abstract: The present invention provides a single-pole double-throw switch circuit with a Type-C interface, an analog switch chip and an electronic device, which can generate a reverse bias voltage across a first diode, so that a capacitance value of a PN junction can be significantly reduced after the reverse bias voltage is applied to the PN junction. Further, a ground capacitance corresponding to a COM point when the first diode is turned off can be effectively reduced, avoiding the reduction of a bandwidth of a digital path due to excessive capacitance. It can be seen that the present invention can realize a large size of a first field effect transistor and a high bandwidth of the digital path simultaneously, thereby facilitating the simultaneous improvement of the THD performance of an analog audio path and the bandwidth of the digital path, and avoiding conflicts between the two.

Abstract: A semiconductor device is provided. The semiconductor device includes power supply lines extending in a first direction; first transistors, each of which is formed in a first region and has a first threshold voltage; and second transistors, each of which is formed in a second region and has a second threshold voltage higher than the first threshold voltage. One of the plurality of power supply lines is interposed between the first region and the second region, the first transistors implement a first portion of a multiplexer, a clock buffer and a first latch that are disposed on a data path, the second transistors implement a second portion of the multiplexer circuit and a second latch that are disposed on a feedback path, and the first portion of the multiplexer circuit and the second portion of the multiplexer circuit are disposed in a common location along the first direction.

Abstract: A retrieving device is adapted to be installed in an electric nail gun. The retrieving device includes at least one stationary seat that is adapted to be connected to a swing arm of the nail gun and that has at least one stationary elongated hole being elongated in an extending direction, at least one moving seat that is adapted to be co-movably connected to a movable impact member of the nail gun, and at least one resilient member that interconnects the at least one stationary seat and the at least one moving seat, and that has at least one first end coil extending through the at least one stationary elongated hole and being movable parallel to the extending direction along the at least one stationary elongated hole.

Abstract: Disclosed systems and methods relate to a power efficient voltage level translator. In a normal mode wherein a first supply voltage of the first voltage domain and a second supply voltage of the second voltage domain are different, the voltage level translator translates an input signal in a first voltage domain to an output signal in a second voltage domain. In a bypass mode wherein the first supply voltage and the second supply voltage are substantially the same, a bypass circuit is configured to bypass the voltage level translator and provide the input signal as the output signal in the first voltage domain, thus avoiding delay introduced by the voltage level translator in the bypass mode. Further, a power-down circuit is configured to power-down the voltage level translator in the bypass mode but not in the normal mode.

Abstract: Systems, methods and mechanisms for efficiently reporting sensor data of multiple processing units. In various embodiments, a computing system includes processing units and a power management unit. The processing units include multiple sensors for measuring a variety of types of sensor data. If the sensor values exceed corresponding thresholds, then a processing unit sends the sensor values to the power management unit. Logic in the power management unit stores received sensor values. When the logic determines behavior of a processing unit changes, the logic updates one or more sensor thresholds for the processing unit for changing a frequency of reporting one or more sensor values of the processing unit. The logic sends the updated one or more sensor thresholds to the processing unit. The logic updates more operating modes and operating states for the processing units based on the received sensor values.

Abstract: A semiconductor apparatus may include a degradation detection circuit and a circuit block. The degradation detection circuit may detect a degradation occurred in a semiconductor apparatus and generate degradation information. The circuit block may include at least one transistor configured to receive a variable bias voltage and a variable gate voltage.

Abstract: Power supply architectures and enhanced power control techniques are presented herein. In one example, a system includes a plurality of power supply phases and a system processor. The system processor comprises a processing unit comprising a plurality of processing cores, a plurality of power domains configured to segregate power distribution for the processing unit into sets of the plurality of processing cores, and external connections configured to couple individual ones the plurality of power domains to individual ones of the plurality of power supply phases.

Abstract: The present disclosure provides a phase locked loop-based power supply circuit and method, and a chip. The phase locked loop-based power supply circuit includes: a phase locked loop circuit, including a voltage-controlled oscillator (VCO), the phase locked loop circuit outputs, through an output end of the phase locked loop circuit, a control voltage for controlling the VCO; and a voltage regulator, an input end of the voltage regulator is connected with the output end of the phase locked loop circuit, to make the control voltage outputted by the phase locked loop circuit form a power supply voltage after passing through the voltage regulator; the power supply voltage is used for supplying power for a load circuit; the load circuit includes at least one logic gate. The phase locked loop-based power supply circuit reduces timing variations in a digital circuit, and is conducive to implementing timing closure.

Abstract: An integrated circuit is provided. The integrated circuit includes a power gating circuit configured to receive a power supply voltage from a first power line and to output a first driving voltage to a first virtual power line and a logic circuit electrically connected to the first virtual power line and configured to receive power from the power gating circuit. The power gating circuit includes a first p-type transistor and a first n-type transistor connected in parallel between the first power line and the first virtual power line.

Abstract: The disclosed technology includes techniques for preserving battery life of a mobile device by monitoring a mobile device to determine a state of inactivity. A state of inactivity may be determined if the screen of the mobile device is off and the mobile device remains stationary for a period of time. Battery life may be preserved by placing the mobile device and/or a mobile application of the mobile device into an idle state for successive idle periods separated by maintenance periods. When in an idle state, the mobile device and/or a mobile application of the mobile device may be prevented from utilizing various features or functions of the mobile device that may tend to drain the battery. The mobile device and/or mobile application may be granted temporary access to the various features and functions during the maintenance periods to temporarily allow the mobile device and/or mobile application to perform updates.

Abstract: Disclosed is a power converter including power conversion circuitry. The power conversion circuitry includes a converter coil. The power conversion circuitry includes a power source. The power conversion circuitry includes a switch connected to the converter coil to control current flowing through the converter coil from the power source, the power conversion circuitry including a converter output connectable to a converter load. The power conversion circuitry includes parallel snubber circuitry having resonant circuitry connected in parallel with the converter coil, the resonant circuitry including a parallel snubber circuitry coil and a capacitor connected in series, the parallel snubber circuitry including a parallel snubber output connectable to a parallel snubber circuitry load.

Abstract: A circuit includes a first regulation module, second regulation module, first monitoring module, and second monitoring module. The first regulation module is configured to generate, from a supply voltage, a first voltage. The second regulation module is configured to generate, from a first voltage, a second voltage that is less than the first voltage. The first monitoring module is configured to generate a first warning signal when the first voltage exceeds a first threshold and to generate the first warning signal when a first testing voltage exceeds the first threshold. The second monitoring module is configured to generate a second warning signal when the second voltage exceeds a second threshold and to generate the second warning signal when a second testing voltage exceeds the second threshold.

Abstract: A data driver includes pre-driver circuitry coupled to a digital-to-analog converter (DAC) via a plurality of bit lines. The pre-driver circuitry is configured to receive a plurality of first voltages corresponding to respective bits of a digital codeword. Each of the first voltages may have one of a first voltage value or a ground potential based on a value of the corresponding bit. The pre-driver circuitry is further configured to drive a plurality of second voltages onto the plurality of bit lines, respectively, by switchably coupling each of the bit lines to ground or a voltage rail based at least in part on the voltage values of the plurality of first voltages. The voltage rail provides a second voltage value that is greater than the first voltage value. The DAC converts the plurality of second voltages to an electrical signal which is an analog representation of the digital codeword.

Abstract: A hybrid battery system is provided for extending the shelf-life of rechargeable batteries. The hybrid battery system may contain sets of non-rechargeable and rechargeable batteries respectively. As the rechargeable batteries are discharged (e.g., from self-discharge), the hybrid battery system may utilize the non-rechargeable batteries to maintain the rechargeable batteries at a preferred state of charge. A preferred state of charge may be selected to extend the shelf-life of the rechargeable batteries. Alternatively, a signal may change the preferred state of charge to prepare the rechargeable batteries for use or for other reasons. The hybrid battery system may contain modular components, thereby allowing for easy replacement of defective or otherwise unsuitable non-rechargeable batteries, rechargeable batteries, or supporting electronics.

Abstract: A battery system includes a battery module; a cooling channel disposed adjacent to the battery module; a ground wire configured to electrically connect the cooling channel and a vehicle body; and a leakage current blocking device configured to interrupt an electrical connection of the cooling channel and the vehicle body when a leakage current occurs in the battery module.

Abstract: A power management controller is disclosed. Broadly speaking, the controller may, in response to receiving a timing signal, monitor a temperature of an integrated circuit including multiple processor clusters. The controller may generate a comparison of the temperature and a threshold value, and in response to a determination that the comparison indicates that the temperature is less than the threshold value, transition a particular processor cluster to a new power state.

Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

Abstract: An integrated circuit device comprising a power control unit for controlling the power of a power isle is disclosed. The power control unit comprises (i) a power gating switch implemented in the BEOL portion for switching ON/OFF the power to the power isle, (ii) a state recovery circuit comprising a memory element in the FEOL portion or BEOL portion and a transistor configuration in the BEOL portion, and (iii) a wake-up/sleep circuit in the BEOL portion adapted for receiving an identifier. The wake-up/sleep circuit is operatively connected with the power gating switch and with the state recovery circuit. Responsive to receiving the identifier, the wake-up/sleep circuit causes the power gating switch to switch OFF/ON the supply power to the power isle and causes the state recovery circuit to store/restore the state of the power isle.

Abstract: A system-on-a-chip includes an integrated circuit and an estimation circuit. The estimation circuit operates to acquire at least one physical parameter representative of the use of the integrated circuit and determine an instantaneous state of aging of the integrated circuit as a function of the at least one physical parameter. A margin of use of the integrated circuit is then calculated by comparing the instantaneous state of aging with a presumed state of aging.

Abstract: Supply voltage droop management circuits for reducing or avoiding supply voltage droops are disclosed. A supply voltage droop management circuit includes interrupt circuit configured to receive event signals generated by a functional circuit. Event signals correspond to an operational event that occurs in the functional circuit and increases load current demand to a power supply powering the functional circuit, causing supply voltage droop. The interrupt circuit is configured to generate an interrupt signal in response to the received event signal. Memory includes an operational event-frequency table having entries with a target frequency corresponding to an operational event. Operating the functional circuit at target frequency reduces the load current demand on the power supply, and supply voltage droop.

Abstract: When a transition control section stochastically determines on the basis of a temperature, an energy change, and a random number whether to allow one of a plurality of state transitions according to a relative relationship between the energy change and a thermal excitation energy, the transition control section adds an offset to the energy change and exercises control so as to set the offset at a local minimum, at which an energy is locally minimized, to be larger than an offset at the time of the energy not being minimized.

Abstract: Various embodiments are generally directed to the provision re-provision of encryption keys to access encrypted media. Encryption keys may be provisioned and re-provisioned to components, such as, processor elements, of a system based on power state transitions of the components. An encryption key may be provisioned to a component and then re-provisioned to the component before or after the component transitions from an active power state to another power state and back to the active power state.

Abstract: An electronic that includes an integrated circuit (IC) configured to regulate an output voltage for powering a light emitting diode (LED). A first transistor is configured to be switched on or off by the IC to inductively couple or decouple a main power supply bus voltage from a primary winding of a transformer to a secondary winding of the transformer connectable to the LED. A second transistor is coupled between the IC and the main power supply bus voltage, and configured to be switched on or off by the IC to selectively provide an IC power supply input voltage to the IC.

Abstract: An apparatus includes a master latch circuit including a first circuit and a second circuit, and a slave latch circuit including a third circuit and a fourth circuit. The first circuit and the second circuit may be coupled to a first shared circuit node, and the third circuit and the fourth circuit may be coupled to a second shared circuit node. The master latch circuit may be configured to store a value of an input signal in response to an assertion of a clock signal. The slave latch circuit may be configured to store an output value of the master latch circuit in response to a de-assertion of the clock signal. The master latch circuit may also be configured to de-couple the first shared circuit node from a ground reference node in response to the de-assertion of the clock signal.

Abstract: A system-on-chip and an electronic device including the system-on-chip are provided. The system-on-chip includes a power switch, a logic block, a memory device, and a buffer. The power switch is coupled between a first power supply line and a virtual power supply line, and turns on in response to a switch control signal. The logic block is coupled between the virtual power supply line and a ground line. The memory device is coupled between a second power supply line and the ground line. The buffer is coupled between the second power supply line and the ground line, and generates the switch control signal based on a sleep signal.

Abstract: Techniques and implementations pertaining to improvements in power delivery for multi-core processors are described. A method may involve determining whether one or more processing units of a plurality of processing units are starting. The method may also involve increasing power provided to the plurality of processing units before the one or more processing units are started responsive to a determination that the one or more processing units are starting.

Abstract: A display device including: a display panel including pixels and data lines; a data driver configured to apply data voltages to the data lines; an image pattern determiner configured to determine an image pattern based on an input image signal and to generate image pattern information; and a bias current control signal generator configured to generate a bias current control signal for determining a magnitude of a bias current of the data driver based on the image pattern information.

Abstract: A memory is provided that includes a row decoder that decodes an address into a plurality of decoded signals for selecting a word line to be asserted from a plurality of word lines. Each word line is driven through a decoder level-shifter that processes the decoded signals. Each decoder level-shifter corresponds to a unique combination of the decoded signals. The row decoder is in a logic power domain such that the decoded signals are asserted to a logic power supply voltage. When a decoder level-shifter's unique combination of decoded signals are asserted by the row decoder, the decoder level-shifter drives the corresponding word line with a memory power supply voltage for a memory power domain.

Abstract: Examples are given for techniques for entry to a lower power state for a memory device or die. The examples to include delaying transitions of the memory device or die from a first higher consuming power state to a second relatively lower power state using one or more programmable counters maintained at or with the memory device.

Abstract: An electronic device including a semiconductor memory. The semiconductor memory may include a cell array including a plurality of resistive storage cells; a current code generation block suitable for generating a current code which has a value corresponding to an average value of current amounts of test currents respectively flowing through at least two first resistive storage cells among the plurality of resistive storage cells, in a test operation; and a sensing block suitable for comparing a read current flowing through a second resistive storage cell selected among the plurality of resistive storage cells with a reference current, and thereby sensing data of the second resistive storage cell, wherein the semiconductor memory is operable to adjust a current amount of at least one current flowing through the sensing block based on the value of the current code.

Abstract: An integrated circuit comprises a first layer on a first level. The first layer comprises a set of first lines. The first lines each have a length and a width. The length of each of the first lines is greater than the width. The integrated circuit also comprises a second layer on a second level different from the first level. The second layer comprises a set of second lines. The second lines each have a length and a width. The length of each of the second lines is greater than the width. The integrated circuit further comprises a coupling configured to connect at least one first line of the set of first lines with at least one second line of the set of second lines. The coupling has a length and a width. The set of second lines has a pitch measured between the lines of the set of second lines in the first direction. The length of the first coupling is greater than or equal to the pitch.

Abstract: A pulse converter circuit includes a logic circuit to which a first signal is input and from which a second signal is output. The logic circuit includes a p-channel transistor which determines whether a voltage of the second signal is set to a first voltage depending on a voltage of the gate; and an n-channel transistor which determines whether the voltage of the second signal is set to a second voltage, which is higher than the first voltage, depending on a voltage of the gate. The p-channel transistor includes a semiconductor layer containing an element of a group 14. The n-channel transistor includes an oxide semiconductor layer.

Abstract: Hybrid circuits are CMOS circuits that can function in two different operation modes: a normal operation mode and a power saving mode. At normal operation mode, a hybrid circuit operates in the same ways as typical CMOS circuits. At power saving mode, the standby leakage current of the circuit is reduced significantly. Typically, most parts of a hybrid circuit stay in power saving mode. A circuit block is switched into normal operation mode when it needs to operate at full speed. The resulting circuits are capable of supporting ultra-low power operations without sacrificing performance. Hybrid circuits can be implemented on integrated circuits comprising multiple-gate MOS transistors.

Abstract: A system and method to implement an integrated circuit design are described. The method includes obtaining a timing database of current timing slack values based on current cell selection, placement, and routing for a plurality of cycles defined by a plurality of cycle boundaries, each cycle representing devices between a corresponding pair of the plurality of cycle boundaries, identifying candidate cycle boundaries among the plurality of cycle boundaries for slack redistribution, every one of the candidate cycle boundaries being associated with a positive timing slack, and selecting redistribution cycle boundaries among the candidate cycle boundaries. A modified timing database is generated based on redistributing the positive timing slack associated with the redistribution cycle boundaries, and power recovery is performed using the modified timing database to reduce power at one of more of the redistribution cycle boundaries.

Abstract: A lighting circuit, which is mounted in a vehicle lamp, can change the luminance at high speeds. The lighting circuit is used together with a semiconductor light source and makes up a vehicle lamp. A switching converter supplies power to the semiconductor light source. A converter controller controls the switching converter. A current detection circuit detects a current IDRV which is supplied from the switching converter to the semiconductor light source. A hysteresis comparator compares the detected current value with an upper threshold voltage and a lower threshold voltage and generates a control pulse according to the results of the comparison. A threshold voltage generating circuit receives a variable control voltage which indicates a target amount of a current and generates the upper threshold voltage and the lower threshold voltage according to the control voltage.

Abstract: A power controller, including a supercapacitor, a motor, a transistor switch, an electric signal processor, an output resistor, a sampling resistor, a filter capacitor, a voltage-stabilizing circuit, a flyback diode, and a switch. The supercapacitor is connected in parallel to the motor, the transistor switch, and the sampling resistor to form a main working circuit. The signal output end of the electric signal processor is connected to a trigger electrode of the transistor switch via the output resistor. The sampling end of the electric signal processor is connected to the sampling resistor. The motor is connected in parallel to the flyback diode. The sampling resistor is connected in parallel to the filter capacitor. The Vcc end of the electric signal processor is connected to the supercapacitor via the voltage-stabilizing circuit. The state control ends of the electric signal processor are connected to the GND or Vcc of the electric signal processor via the switch.

Abstract: Processing logic circuit has State Retention Power Gating logic circuit including at least two scan chains having different lengths and operable to collect state information about at least a portion of the processing logic circuit before the at least a portion of the processing logic circuit is placed from a first state into a second, different, state. The processing logic circuit includes a memory operable to store collected state information about the at least a portion of the processing logic circuit, and logic circuit operable to rearrange the collected state information data for scan chains shorter than a longest scan chain, to enable valid return of the collected state information data, for the scan chains shorter than a longest scan chain, to the at least a portion of the processing logic circuit when the at least a portion of the processing logic circuit returns to the first state.

Abstract: Hybrid Super Threshold (SupVt) circuits are CMOS circuits that can function in two different operation modes: a normal operation mode and a SupVt power saving mode. At normal operation mode, a hybrid SupVt circuit operates in the same ways as typical CMOS circuits. At SupVt mode, the standby leakage current of the circuit is reduced significantly, while the circuit still can function at high speed. Typically, most parts of a hybrid SupVt circuit stay in power saving mode. A circuit block is switched into normal operation mode when it needs to operate at full speed. The resulting circuits are capable of supporting ultra-low power operations without sacrificing performance.

Abstract: An application process unit executes a predetermined application program and a communication process unit performs a predetermined data communication process with another communication target. A communication stop determination unit determines whether or not to stop the data communication process performed by the communication process unit, on the basis of an instruction from the application process unit. When it is determined by the communication stop determination unit to stop the data communication process, the data communication process is stopped.

Abstract: Power gating control architectures. A memory device having at least a memory array and input/output (I/O) lines terminated on the memory device with termination circuitry coupled to receive a termination supply voltage (Vtt) with power gating circuitry to selectively gate the termination supply voltage in response to a power gating control signal (VttControl) is coupled with a processing core coupled with the memory device, the processing core to selectively assert and deassert the VttControl signal.

Abstract: A semiconductor integrated circuit includes: a first voltage line on which a specific one of a power-supply voltage and a reference voltage appears; a second voltage line; a plurality of circuit cells each receiving power generated as a difference between a voltage appearing on the second voltage line and the other one of the power-supply voltage and the reference voltage; a plurality of switch transistors connected in parallel between the first and second voltage lines to serve as switch transistors including switch transistors each having different conducting-state resistances; and a switch conduction control section for controlling a transition of each of the switch transistors from a non-conducting state to a conducting state by turning on the switch transistors at separate points of time.

Abstract: A semiconductor integrated circuit includes: a first voltage line on which a specific one of a power-supply voltage and a reference voltage appears; a second voltage line; a plurality of circuit cells each receiving power generated as a difference between a voltage appearing on the second voltage line and the other one of the power-supply voltage and the reference voltage; a plurality of switch transistors connected in parallel between the first and second voltage lines to serve as switch transistors including switch transistors each having different conducting-state resistances; and a switch conduction control section for controlling a transition of each of the switch transistors from a non-conducting state to a conducting state by turning on the switch transistors at separate points of time.