Abstract: An integrated circuit comprising: a first core circuit configured to operate at a first clock rate for carrying out a first range of tasks; and a second core circuit configured to operate in a first mode and a second mode, the second core circuit being configured to operate at a second clock rate for carrying out a second range of tasks in the second mode and being configured to operate in the second mode when the first core circuit carries out the first range of tasks, the second clock rate being greater than the first clock rate.

Abstract: Apparatus and method for supplying electrical power to a device. A system on chip (SOC) integrated circuit includes a first region having a processing core and a second region characterized as an always on domain (AOD) power island electrically isolated from the first region and having a power control block. A first power supply module is used to apply power to the first region, and a second power supply module is used to apply power to the second region. The second power supply module includes a main switch between the first power supply module and a host input voltage terminal. The power control block initiates a low power mode by transitioning the main switch to an open state. This causes the first region to receive no electrical power while the second region continuously receives power during the low power mode.

Abstract: A method and apparatus for dynamic clock and power gating and decentralized wakeups is disclosed. In one embodiment, an integrated circuit (IC) includes power-manageable functional units and a power management unit. Each of the power manageable functional units is configured to convey a request to enter a low power state to the power management unit. The power management unit may respond by causing a requesting functional unit to enter the low power state. Should another functional unit initiate a request to communicate with a functional unit currently in the low power state, it may send a request to that functional unit. The receiving functional unit may respond to the request by exiting the low power state and resuming operation in the active state.

Abstract: A semiconductor device includes a high voltage generator for generating a high voltage by raising a power source voltage, a transfer circuit for transferring the high voltage to an internal circuit in response to a transfer signal, and a first discharge circuit for discharging the high voltage of an output node of the high voltage generator or the high voltage of an input node or output node of the transfer circuit when the power source voltage drops.

Abstract: Disclosed is a dark current cutoff system and method for a vehicle junction. In particular, a controller is configured to monitor signal input through a CAN communication module to determine when other modules in the vehicle are in a sleep mode, cut off battery power to a load device by turning off a switching element when the controller determines that the other modules in the vehicle are in sleep mode, and forcibly maintains an off state of the switching element for a set period time after the power has been cut, regardless of signal input through the CAN communication module.

Abstract: The number of power-gating transistors on an integrated circuit used for power reduction in a sleep mode is controlled during a wake state to adjust the current flow and hence voltage drop across the power-gating transistors as a function of aging of these transistors and/or a function of temperature of the integrated circuit. In this way, the supply voltage to the integrated circuit may be better tailored to minimize current leakage when the integrated circuit is young or operating at low temperatures.

Abstract: There is provided a semiconductor package configured for externally controlled power management. Instead of integrating voltage regulation on-chip as done conventionally, power regulation is moved externally to the PCB level, providing numerous package advantages including size, simplicity, power efficiency, integration flexibility, and thermal dissipation. In particular, the use of flip-chip package configurations provides ready access to power supply bumps, which also allows the use of a universal receiving PCB and power supply through simple reconfiguring of voltage traces. As a result, flexible power management can be implemented, and portions of semiconductor packages may be managed for performance or thermal considerations, which may be of particular use for applications such as multi-core processors.

Abstract: Apparatuses for reducing power consumption in a programmable logic device (PLD) with a self power down mechanism are disclosed. Methods and a machine readable medium for restoring a prior known state are provided. The prior known state is stored in a memory module before the PLD is powered down and the same state is restored from the memory module when the PLD is powered up. The memory module may be an internal or an external non-volatile or volatile memory source. One sector of the memory may be used to store the previous known state. The memory sector can be partitioned into different sections. One section may be used as a header section associated with a data storage section. Partitioning the memory sector into different sections and utilizing multiple addresses from each section ensure less read and write cycles during the powering down and the powering up of the PLD.

Abstract: An electronic circuit includes a plurality of circuit blocks, a plurality of bias circuits, a switching circuit, and plurality of transistors. The plurality of circuit blocks each includes a high power terminal and a low power terminal. The switching circuit includes a plurality of switches for selectively coupling a bias circuit of the plurality of bias circuits to the low power terminal of a circuit block of the plurality of circuit blocks. Each bias circuit of the plurality of bias circuits is selectively couplable to the low power terminal of each of the plurality of circuit blocks. Each transistor of the plurality of transistors has a first current terminal coupled to a circuit ground terminal, and each transistor of the plurality of transistors has a control terminal for controlling the conductivity of the plurality of the transistors by a bias circuit of the plurality of bias circuits.

Abstract: A method for controlling the power supply of an integrated circuit, the power supply comprising a power supply unit powered by a main voltage and possessing several transistor groups, comprising turning on in succession at least two transistor groups in order to deliver, as an output from each group, to at least one part of the integrated circuit, an elementary supply voltage derived from the main voltage, characterized in that the method comprises at least one elementary power phase for supplying power to said at least one part of the integrated circuit, wherein the phase comprises defining voltage thresholds respectively associated with the transistor groups, turning on a first transistor group, the first group delivering a first elementary supply voltage and turning on at least one second group when the first elementary supply voltage is higher than or equal to the voltage threshold associated with the second group.

Abstract: A semiconductor device includes: a first power line to supply a first voltage to a plurality of internal circuits; a second power line to supply the first voltage to the plurality of internal circuits; a first switch provided between said first power line and each of the plurality of internal circuits; a second switch provided between said second power line and each of the plurality of internal circuits; and a control circuit to control the first switch of a second internal circuit included in the plurality of the internal circuits based on the amounts of noise and voltage drop at power-on in a first circuit included in the plurality of internal circuits.

Abstract: Supply voltage sequencing circuitry includes a first sequencer (10-1) that produces an active level of a Power Good signal PG if a first supply voltage VOUT1 exceeds an upper threshold V90% while a control signal EN_PG is active, and produces an inactive level of PG if EN_PG is inactive. The PG level is latched when a control signal EN is inactive. A Power Down signal PD is produced if VOUT1 is less than a lower threshold V10% while EN is inactive. An active level of PD is produced when EN is active. A power-up sequence of supply voltages VOUT1, VOUT2, and VOUT3 monitored by the first sequencer and similar second (10-2) and third (10-3) sequencers, respectively, is determined by connection of PG of each of the first and second sequencers to control the supply voltage monitored by the next sequencer.

Abstract: Disclosed herein is an integrated circuit including: a timing signal distribution circuit configured to distribute a timing signal that indicates predetermined timing; a synchronous operation circuit configured to operate in synchronization with the distributed timing signal; a logic circuit configured to perform predetermined logical operation based on an operation result of the synchronous operation circuit; and a power supply section configured to supply a voltage lower than a timing signal distribution circuit drive voltage to drive the timing signal distribution circuit as a logic circuit drive voltage to the logic circuit.

Abstract: According to one embodiment, there is provided a method of reducing the amount of power consumed by a galvanic isolator. A transmitter transmits a wake-up signal to a receiver located across an isolation medium when the transmitter is ready or preparing to transmit data or power signals to a receiver, which is operably connected to a sensing circuit. The sensing circuit receives the wake-up signal through the isolation medium, which may be operably connected to and powered substantially continuously or intermittently by a first power source. In response to the sensing circuit receiving the wake-up signal, the receiver is powered up from a sleep mode to an operating mode. After a period of time tRDY has passed since the wake-up signal was transmitted, a signature pattern is transmitted from the transmitter to the sensing circuit through the isolation medium. Next, the sensing circuit or the receiver verifies the validity of the signature pattern.

Abstract: Embodiments relate to integrated circuits with protection. In one embodiment the protection is coupled between a first circuit provided to control a low power mode of the integrated circuit and a supply voltage. The protection comprises in an embodiment a transistor being one of a depletion transistor or a junction field effect transistor.

Abstract: The voltage Vdd is set to be lower than in the normal operation (step S100), then voltage is applied to each of the power-supply voltage applied node Vdd, the ground voltage applied node Vss, the semiconductor substrate and the well so that relative high voltage between the gate of turn-on transistor and the semiconductor substrate or the gate of turn-on transistor and well (steps S110 and S120). This process accomplishes rising of the threshold voltage of the transistor that is turned on, the reduction of the variation in the threshold voltage between a plurality of the transistors of the memory cell including latch circuit, and the improvement of the voltage characteristic of the memory cell.

Abstract: A downconverter capable of being normally operated even in the case where a universal dual downconverter is made up by use of multiple downconverter circuits. The downconverter includes first and second downconverter circuits, and an amplification unit having at least a first amplifier LNA for receiving a horizontally polarized wave signal, and a second amplifier LNA for receiving a vertically polarized wave signal. If a Tone/Pola signal is a signal indicating a power-saving mode, a control circuit of the first downconverter circuit causes both a local oscillator and a frequency converter to be in a non-operating state, controlling a bias circuit such that power is supplied to the first amplifier LNA.

Abstract: A digital receiver is disclosed. In one aspect, the receiver includes a receiving module for receiving packetized data. The receive may further include a first processing module for packet detection having a first programmable processor. The receiver may further include a second processing module for demodulation and packet decoding having a second programmable processor. The receiver may further include a first digital receive controller having a third processor arranged for being notified of detection of data by the first processing module and for activating the second processing module.

Abstract: A diagnostic imaging device includes a signal processing circuit (22) processes signals from a detector array (16) which detects radiation from an imaging region (20). The hit signals are indicative of a corresponding detector (18) being hit by a radiation photon. The signal processing circuit (22) includes a plurality of input channels (321, 322, 323, 324), each input channel receiving hit signals from a corresponding detector element (18) such that each input channel (321, 322, 323, 324) corresponds to a location at which each hit signal is received. A plurality of integrators (42) integrate signals from the input channels (32) to determine an energy value associated with each radiation hit. A plurality of analog-to-digital converters (441, 442, 443, 444) convert the integrated energy value into a digital energy value. A plurality of time to digital converters (40) receive the hit signals and generate a digital time stamp.

Abstract: A method and a electronic circuit, the method includes: sending to a switching circuit, to a state retention power gating (SRPG) circuit and to a first power source a control signal indicating that the SRPG circuit should operate in a functional mode; coupling, by the switching circuit, a third power grid to a first power grid; supplying power from the first power source to the SRPG circuit via the first power grid, the switching circuit and the third power grid; supplying power from a second power source to a second circuit via a second power grid; sending to the switching circuit, to the SRPG circuit and to the first power source a control signal indicating that the SRPG circuit should operate in a state retention mode; coupling, by the switching circuit, the third power grid to the second power grid; supplying power from the second power source to the SRPG circuit via the second power grid, the switching circuit and the third power grid; supplying power from the second power source to the second circuit vi

Abstract: According to one embodiment, a semiconductor integrated circuit includes a semiconductor integrated circuit a voltage regulator providing a prescribed power-supply voltage, a plurality of delay test circuits, each of the delay test circuits being configured in each of areas where electrical current flows in response to each of operation modes, a test control unit executing a delay test using the delay test circuit under a test mode while decreasing a power-supply voltage in a stepwise fashion, a supply voltage decision unit deciding the power-supply voltage of the operation mode on a basis of the delay test, a memory unit storing the power-supply voltage of each operation mode, a supply voltage configuration unit reading out the power-supply voltage corresponding to the operation mode from the memory unit, and the supply configuration unit arranging the power-supply voltage as an output voltage of the voltage regulator when each of the operation modes starts to execute.

Abstract: The invention discloses a power gating for in-rush current mitigation. Firstly the circuit uses small power switch cells at first stage, such that those power switch cells run in saturation region. Secondly a delay unit delays a switch signal to control the dwell time of current to reduce the peak value of the current. Thirdly large power switch cells are used at the rest, such that those power switch cells operate in linear region.

Abstract: A semiconductor device includes: a first transistor having a control electrode coupled to an input node receiving a signal synchronized with a clock, a first conductive electrode coupled to an output node, and a second conductive electrode; a second transistor having a control electrode coupled to the input node, a first conductive electrode coupled to the output node, and a second conductive electrode coupled to a power supply node; and a first switch element connected between the power supply node and the second conductive electrode of the second transistor and turned on and off based on a first control signal indicating a detection result of a frequency of the clock.

Abstract: A buffer system is provided that reduces threshold current using a current source to provide power to one or more stages of the buffer system. The buffer system may also include delay management techniques that balances all of, or part of, a delay that may be imparted to an input signal by the current source. In addition, hysteresis techniques may be used to provide enhanced noise management of the input signal.

Abstract: A dynamic biasing circuit of the substrate of a MOS power transistor may include a first switch configured to connect the substrate to a current source which forward biases the intrinsic source-substrate diode of the transistor, when the gate voltage of the transistor turns the transistor on. The current source may include a stack of diodes in the same conduction direction as the intrinsic diode between the substrate and a supply voltage.

Abstract: To provide an internal power supply circuit that supplies a power supply voltage to an internal circuit of a semiconductor device via an internal power supply wiring, the internal power supply circuit includes a plurality of power supply units connected in common to the internal power supply wiring and an internal-power-supply control circuit that selects either activation or deactivation with regard to at least a part of the power supply units.

Abstract: A CMOS circuit and a semiconductor device having small leakage current and a low threshold voltage, and which is operated at high speed and with a small voltage amplitude, including an output stage circuit having MOSTs configured such that when their gates and sources are respectively set to an equal voltage, subthreshold leakage currents substantially flow between their drains and sources, and upon deactivation, a voltage is applied to the gate of each of the MOSTs to cause a reverse bias to be applied between the gate and source of the MOST. Upon activation of the circuit, the MOST is held in a reverse bias state or controlled to a forward bias state according to an input voltage.

Abstract: According to an aspect of an embodiment, an electric circuit device includes: a first and second voltage supply units to be applied with a first and second voltages, respectively; a first capacitor connected to the first voltage supply unit; a first switch connected between the first voltage supplying unit and the first capacitor; a first load circuit connected to the second voltage supply unit; a second switch connected between the second voltage supply unit and the first load circuit; a third switch connected to connect the first capacitor with the first load circuit; and a switch controller for turning on either the third switch or the first switch, and for turning off the third switch while the second switch is turned on.

Abstract: According to one embodiment, a power source controller has a first power source line supplied with a reference power source voltage, a second power source line connected to an internal circuit, a control circuit configured to control a connection between the first power source line and the second power source line, a control signal line connected to the control circuit, and configured to provide a control signal for controlling the connection, a transistor comprising a first terminal, a second terminal and a control terminal in the control circuit, the control terminal of the transistor being connected to the control signal line, a semiconductor substrate on which the transistor is formed, and first through third wires.

Abstract: The present invention discloses a power booting sequence control system and the control method thereof, which optimizes a power booting sequence of a plurality of power switches in an integrated circuit. An initial module initializes a target charge value, a preset current budget and a plurality of time intervals. A current lookup module obtains a booting current across a power switch from a built-in current lookup table. A first computing unit and a second computing unit compute a first and a second power switch numbers respectively. A processing module selects the small number of the first and the second power switch number to get a maximum number of power booting switches under the time intervals, and opens the maximum number of the power booting switches. Therefore, the system keeps the in-rush current value under the preset current budget and speeds up the ramp-up time in a power booting state.

Abstract: A circuit, an adjusting method, and use of a control loop for adjusting a data retention voltage and/or a leakage current of a CMOS circuit for a sleep mode, wherein the CMOS circuit is operated to control in a measuring mode, whereby in the measuring mode a leakage current exclusively flows through the CMOS circuit, the control loop in the measuring mode adjusts the data retention voltage and/or the leakage current, and the adjustments of the control loop for the sleep mode are stored.

Abstract: Circuits and methods to realize a power-efficient high frequency buffer. The amplitude of a buffered signal is detected and compared with the amplitude of the input signal. The comparison result can be fed back to the digitally-controlled buffer to keep the output gain constant. By using feedback control, the buffer can be kept at the most suitable biasing condition even if the load condition or signal frequency varies.

Abstract: An integrated circuit die stack including a first integrated circuit die mounted upon a substrate, the first die including pass-through vias (‘PTVs’) composed of conductive pathways through the first die with no connection to any circuitry on the first die; and a second integrated circuit die, identical to the first die, rotated with respect to the first die and mounted upon the first die, with the PTVs in the first die connecting signal lines from the substrate through the first die to through silicon vias (‘TSVs’) in the second die composed of conductive pathways through the second die connected to electronic circuitry on the second die; with the TSVs and PTVs disposed upon each identical die so that the positions of the TSVs and PTVs on each identical die are rotationally symmetrical with respect to the TSVs and PTVs on the other identical die.

Abstract: Various methods and apparatuses are described for a power distribution structure. In an embodiment, an integrated circuit contains power gating cells that each contain Metal Oxide Semiconductor (MOS) device switches located relative in the power distribution structure to power up and down a block of logic containing a plurality of individual cells using these MOS device switches. The MOS device switches can be tuned to requirements of a target block of logic in order to meet its optimal voltage drop requirements during its active operational state while minimizing leakage current in its off state.

Abstract: A start-up circuit to discharge EMI filter is developed for power saving. It includes a detection circuit detecting a power source for generating a sample signal. A sample circuit is coupled to the detection circuit for generating a reset signal in response to the sample signal. The reset signal is utilized for discharging a stored voltage of the EMI filter.

Abstract: A start-up circuit to discharge EMI filter is developed for power saving. It includes a detection circuit detecting a power source for generating a sample signal. A sample circuit is coupled to the detection circuit for generating a reset signal in response to the sample signal. The reset signal is utilized for discharging a stored voltage of the EMI filter.

Abstract: A low power reference device is disclosed. The low power reference device includes a precision reference module, a low power reference module, a calibration module, an output module and one or more sequencers. The precision reference module is configured to output a first reference signal while the low power reference module is configured to output a second reference signal. The calibration module is configured to receive the first and second reference signals and output a correction signal to the low power reference module. The output module is configured to receive the first and second reference signals and output a final reference signal. The one or more sequencers are configured to drive each of the precision reference modules, low power reference module, calibration module and output module according to a predetermined timing sequence.

Abstract: Power consumption is increased in an interface circuit having a signal processing function for waveform shaping due to influence of a circuit added for waveform shaping. Also, since a plurality of boards are connected to a backplane in a system, they are not exchanged in accordance with distances while there are boards being far or near are mixed, but a common board is used. Thus, it is necessary to prepare a configuration of an interface circuit meeting the longest transfer distance. An interface circuit disabling a part of or all of operations of a waveform shaping circuit is provided. Accordingly, in accordance with transfer distances, switching of operation ranges of waveform shaping circuit inside the interface circuit is possible, and operation ranges of the waveform shaping circuit can be limited, and power consumption of the interface circuit, an LSI including the interface circuit, and a server device can be reduced.

Abstract: A low leakage power management system is provided. An external voltage domain is selectively coupled to the internal voltage domain of an integrated circuit according to demand for the functions provided by the integrated circuit. An external voltage VDD is connected to the internal supply voltage plane of the integrated circuit when the integrated circuit is active. The external supply voltage VDD is disconnected from the integrated circuit chip during idle periods. A plurality of switch cells may be provided for connecting the external voltage VDD to the integrated circuit. A multi-step sequence is provided for connecting the external supply voltage VDD to the chip's internal supply voltage plane to prevent excessive current from flowing through any individual switch cell.

Abstract: A system for power management. The system includes a plurality of input/output pads and a plurality of input/output cells, where each input/output cell is coupled to one of the input/output pads. The system further includes a plurality of interrupt observe circuits, where each interrupt observe circuit is coupled to one of the input/output cells, and where the interrupt observe circuits are configured to generate an interrupt flag during a low power mode.

Abstract: The present invention is directed to perform fine low-voltage control without largely increasing the circuit layout area in a low-power consumption structure. In the case of shifting a region to a low-speed mode, a system controller outputs a request signal and an enable signal to a power switch controller and a low-power drive circuit, respectively, to turn off a power switch and to perform a control so that the voltage level of a virtual reference potential becomes about 0.2 V to about 0.3V. The region operates on voltages between a power supply voltage and a virtual reference potential, so that it is controlled in the low-speed mode.

Abstract: The semiconductor circuit device includes a power line receiving first voltage; each of internal circuits being provided with different operating voltages by the operation mode; a power supply circuit connected with one of internal circuits and the power line to provide second voltage lower than the first voltage to the one of internal circuits; and a control circuit controlling the power supply circuit in accordance with each of the operation modes, wherein when a change of a operation mode is performed, if a operating voltage after the change of a operation mode is higher than a operating voltage before the change of a operation mode, firstly the control circuit controls the power supply circuit to supply a second voltage higher than the operating voltage and secondly the control circuit controls the power supply circuit to supply the operation voltage after the change of a operation mode to the internal circuit.

Abstract: Circuits, and methods for reducing standby leakage power in Integrated Circuit (ICs) are disclosed. In an embodiment, an IC includes a core circuit, a first switch and a second switch, where the first switch is coupled between a power terminal of the core circuit and a power supply and the second switch is coupled between a ground terminal of the core circuit and a ground supply. The first switch and the second switch are configured to power ON and OFF the core circuit. The IC includes a first feedback circuit configured to control ON and OFF states of the first switch based on voltage at the power terminal, and a second feedback circuit configured to control ON and OFF states of the second switch based on voltage at the ground terminal of the core circuit during the standby mode for maintaining the logic state of the core circuit.

Abstract: An integrated circuit comprises a block of components to be power gated and power gating circuitry for selectively isolating the components from the source voltage supply to achieve such power gating. A voltage regulator provides a control voltage to the power gating circuitry when performing power gating operations. The control voltage may be set to any of a plurality of predetermined voltage levels. An adaptive controller receives operating parameter data from either or both of the block of components and the power gating circuitry, that operating parameter data being indicative of leakage current. The adaptive controller issues a feedback signal to the voltage regulator whose value depends on the received operating parameter data. The voltage regulator responds to the feedback signal to change the control voltage between the predetermined voltage levels until the operating parameter data indicates that a desired leakage current is obtained within the power gating circuitry.

Abstract: According to one embodiment, a semiconductor integrated circuit includes a first circuit, a second circuit, and a signal propagation control circuit. The first circuit is configured to have a first power supply terminal. The second circuit is configured to have a second power supply terminal independent of the first power supply terminal. The signal propagation control circuit is configured to provide a first fixed value to the second circuit for a predetermined period after power is supplied to the second circuit, and after the predetermined period, configured to control whether to transfer an output signal from the first circuit to the second circuit or provide the first fixed value to the second circuit.

Abstract: A computing device is disclosed comprising digital circuitry, and a gate speed regulator operable to generate a supply voltage applied to the digital circuitry. A frequency synthesizer generates a first reference frequency, and a propagation delay oscillator generates a first oscillation frequency in response to the supply voltage, wherein the first oscillation frequency is compared to the first reference frequency to generate a first error signal. A reference oscillator generates a second reference frequency in response to a reference voltage, and a startup oscillator generates a second oscillation frequency in response to the supply voltage, wherein the second oscillation frequency is compared to the second reference frequency to generate a second error signal. An adjustable circuit, responsive to the first and second error signals, adjusts the supply voltage applied to the digital circuitry.

Abstract: A method and an electronic circuit, the electronic circuit includes: a module that comprises multiple flip-flops and a control signal providing circuit; a power management circuit arranged to provide to the module a supply voltage of a functional level when the module is in a functional mode, and to provide to the module a supply voltage of an idle level when the module is in an idle mode; wherein the control signal providing circuit is arranged to provide to the multiple flip-flops, when the module is in the functional mode, a control signal that facilitates a state change of each of the multiple flip-flops; wherein the control signal providing circuit is arranged to provide to the multiple flip-flops, when the module is in the idle mode, a control signal that prevents a state change of each of the multiple flip-flops; wherein the each of the control signal providing circuit and a plurality of flip-flops of the multiple flip-flops comprises at least one hybrid circuit that comprises a low-threshold transisto

Abstract: A circuit for reducing power consumption in input ports of an integrated circuit is disclosed. The circuit comprises a plurality of receiver circuits of the integrated circuit for receiving input signals coupled to the integrated circuit; and a bias current generator coupled to the plurality of receiver circuits, the bias current generator providing a bias voltage for each receiver circuit of the plurality of receiver circuits to mirror the current in the bias current generator in each of the receiver circuits. A method of reducing power consumption in input ports of an integrated circuit is also disclosed.

Abstract: A mobile telephone is provided that includes a plurality of circuit blocks and adapted to cut off the supply of power source voltage to any one of the circuit blocks. The mobile telephone also includes an interblock interface circuit provided on a signal path between an elected circuit block and a branch point at which the signal path branches into different branch paths so as to connect to other circuit blocks. The interblock interface circuit includes a signal gate for preventing signal transmission from the elected circuit block to the other circuit blocks, and includes a storage unit for storing a signal right before the power cut-off.

Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.