Abstract: A semiconductor device includes two functional circuits, PMOS transistors and NMOS transistors. The PMOS transistors control whether or not a power supply potential is to be delivered to functional circuits, and the NMOS transistors control whether or not a power supply potential GND is to be delivered to the functional circuits. An external terminal supplied with a third power supply potential and another external terminal is supplied with a fourth power supply potential higher than the third power supply potential. A power supply control circuit delivers a control signal, having the fourth power supply potential as amplitude, to transistors to control the electrically conducting state or the electrically non-conducting state of transistors. The power supply control circuit also delivers a control signal, having the third power supply potential as amplitude, to transistors to control the electrically conducting or non-conducting state of the NMOS transistors.

Abstract: To provide an internal power supply circuit that supplies a power supply voltage to an internal circuit of a semiconductor device via an internal power supply wiring, the internal power supply circuit includes a plurality of power supply units connected in common to the internal power supply wiring and an internal-power-supply control circuit that selects either activation or deactivation with regard to at least a part of the power supply units.

Abstract: An electronic device includes a rechargeable battery, an electrical circuit, a battery safety circuit, and a power down mode circuit. The electrical circuit is configured to generate a power mode control signal. The power down mode circuit receives the power mode control signal. If the power mode control signal has a first value, the power down mode circuit is configured to force a voltage at a first port of the battery safety circuit to a voltage value that is less than an under voltage lock out (UVLO) threshold value of the battery safety circuit to transition the electronic device from a normal operating mode to a low current power down mode. The electronic device may further include a wake up mode circuit.

Abstract: Leakage current is reduced in a plurality of gates coupled between source storage elements and destination storage elements by waking the plurality of gates to allow current flow in response to assertion of any source clock enable signals that enable clocking of the source storage elements. The gates are slept to reduce leakage current in the plurality of gates, in response to assertion of a destination clock enable signal and all of the one or more source clock enable signals being deasserted, the destination clock enable signal enabling clocking of the destination storage elements.

Abstract: If a power supply is provided to a circuit necessary to control a switch for switching a path after wakeup, or if a buckle switch is switched while a microcomputer is asleep, an electrical current necessary for reliable operation of the buckle switch cannot be supplied during sleep, so that the buckle switch will not operate normally. This creates the possibility that wakeup cannot be performed. To permit the electrical current necessary for reliable operation of the buckle switch to be secured if the buckle switch is switched while the microcomputer is asleep, an FET capable of being kept ON or OFF by a power supply acting during sleep, a resistor connected with the FET, and a resistor of large resistance for blocking excessive dark current if the buckle switch is connected are arranged in parallel. The combined resistance of the parallel combination of these elements is used as a pull-up resistance at the input of a control unit.

Abstract: A control circuit includes a triangular wave generating circuit, a temperature sensing circuit, a first comparator, and a switching circuit. The triangular wave generating circuit outputs a triangular wave signal. The temperature sensing circuit senses a temperature surrounding a fan and outputs a temperature signal. A non-inverting terminal of the first comparator is connected to the triangular wave generating circuit. An inverting terminal of the first comparator is connected to the temperature sensing circuit. The first comparator compares the triangular wave signal with the temperature signal to output a control signal. The switching circuit is connected between a power supply and the fan. The switching circuit turns on or off according to the control signal.

Abstract: By classifying an electro-phoretic display integrated circuit (EPD IC) into a digital routine module, a digital non-routine module, and an analog routine module, and by switching off the digital non-routine module and the analog routine module, power consumption of the EPD IC may be effectively reduced, and an available time of an integrated circuit card utilizing the EPD IC may also be lengthened.

Abstract: The semiconductor device may include, but is not limited to, a first switching circuit, a second switching circuit, and a control circuit. The first switching circuit switches between first and second states. The second switching circuit switches between the first and second states. The second switching circuit reduces a first power impedance across the first switching circuit. The control circuit is coupled to the first and second switching circuits. The control circuit keeps the first switching circuit in the first state. The control circuit switches the second switching circuit from the second state to the first state.

Abstract: A liquid crystal display device includes a back light assembly that emits light on a liquid crystal panel; and an inverter that controls brightness of the light emitted from the back light assembly according to a difference between video data of at least three frames that are sequentially inputted to the liquid crystal panel.

Abstract: A voltage regulator regulates voltage at a node and has circuitry coupled to the node for providing a current to the node. A regulating transistor coupled between the node and a first power supply voltage terminal has a disabling transistor coupled in parallel and is selectively disabled by directly connecting the first power supply voltage terminal to the node. An inverting stage has an output connected to the regulating transistor. A load transistor has a first current electrode coupled to a second power supply voltage terminal, and a control electrode and second current electrode connected together and coupled to an input of the inverting stage. A sensing transistor has a first current electrode coupled to the second current electrode of the load transistor, a control electrode connected directly to the node and a second current electrode coupled to the first power supply voltage terminal.

Abstract: The present invention is directed to perform fine low-voltage control without largely increasing the circuit layout area in a low-power consumption structure. In the case of shifting a region to a low-speed mode, a system controller outputs a request signal and an enable signal to a power switch controller and a low-power drive circuit, respectively, to turn off a power switch and to perform a control so that the voltage level of a virtual reference potential becomes about 0.2 V to about 0.3V. The region operates on voltages between a power supply voltage and a virtual reference potential, so that it is controlled in the low-speed mode.

Abstract: A circuit, an adjusting method, and use of a control loop for adjusting a data retention voltage and/or a leakage current of a CMOS circuit for a sleep mode, wherein the CMOS circuit is operated to control in a measuring mode, whereby in the measuring mode a leakage current exclusively flows through the CMOS circuit, the control loop in the measuring mode adjusts the data retention voltage and/or the leakage current, and the adjustments of the control loop for the sleep mode are stored.

Abstract: A circuit having a local power block for leakage reduction is disclosed. The circuit has a first portion and a second portion. The first portion is configured to operate at a substantially greater operating frequency than the operating frequency of the second portion. The second portion has a local power block configured to decouple the second portion if the second portion is inactive to reduce leakage current associated with the second portion without sacrificing performance of the first portion.

Abstract: A pair of power nodes of a logic circuit that needs to output a high level at the time of standby is connected to third and fifth dummy power lines and a pair of power nodes of a logic circuit that needs to output a low level at the time of standby are connected to second and sixth dummy power lines. Fourth, third, sixth, and fifth potentials of the second, third, fifth, and sixth dummy power lines satisfy fourth potential<third potential<first potential, and sixth potential>fifth potential>second potential. With this configuration, a leakage current flowing between a substrate and a gate of a transistor that becomes on at the time of standby, and a leakage current flowing between the substrate and a drain of a transistor that becomes off at the time of standby can be reduced.

Abstract: There is provided an output stage circuit including such MOSTs (M) that when their gates and sources are respectively set to an equal voltage, subthreshold leakage currents substantially flow between their drains and sources, wherein upon its deactivation, a voltage is applied to the gate of each of the MOSTs (M) in such a manner than a reverse bias is applied between the gate and source of the MOST (M). That is, when the MOST (M) is of a p channel type, a voltage higher than that of a p type source is applied to its gate. When the MOST (M) is of an n channel type, a voltage lower than that of an n type source is applied to its gate. Upon activation of the circuit, the MOST is held in a reverse bias state or controlled to a forward bias state according to an input voltage. A CMOS circuit and a semiconductor device can be realized each of which is small in leakage current even though its threshold voltage is low and which is operated at high speed and with a small voltage amplitude.

Abstract: A power-up signal generation circuit of a semiconductor apparatus includes a driver configured to generate a power-up signal in response to a first voltage. The power-up signal generation circuit may also comprise a power control unit configured to provide the first voltage or a second voltage as a power supply voltage to the driver in response to the power-up signal.

Abstract: A system for reducing power consumption in a transistor-based system includes a measurement circuit and a comparator. The measurement circuit measures a delay of a transistor-based device and produces a control signal corresponding to the measured delay. The comparator compares the control signal to a predetermined threshold. Adjusting a power supply voltage of the transistor-based system based at least in part on a result of the comparison reduces the power consumed by the system.

Abstract: A circuit, an adjusting method, and use of a control loop for adjusting a data retention voltage and/or a leakage current of a CMOS circuit for a sleep mode, wherein the CMOS circuit is operated to control in a measuring mode, whereby in the measuring mode a leakage current exclusively flows through the CMOS circuit, the control loop in the measuring mode adjusts the data retention voltage and/or the leakage current, and the adjustments of the control loop for the sleep mode are stored.

Abstract: An integrated circuit die stack including a first integrated circuit die mounted upon a substrate, the first die including pass-through vias (‘PTVs’) composed of conductive pathways through the first die with no connection to any circuitry on the first die; and a second integrated circuit die, identical to the first die, shifted in position with respect to the first die and mounted upon the first die, with the PTVs in the first die connecting signal lines from the substrate through the first die to through silicon vias (‘TSVs’) in the second die composed of conductive pathways through the second die connected to electronic circuitry on the second die; with the TSVs and PTVs disposed upon each identical die so that the positions of the TSVs and PTVs on each identical die are translationally compatible with respect to the TSVs and PTVs on the other identical die.

Abstract: The present invention is directed to perform fine low-voltage control without largely increasing the circuit layout area in a low-power consumption structure. In the case of shifting a region to a low-speed mode, a system controller outputs a request signal and an enable signal to a power switch controller and a low-power drive circuit, respectively, to turn off a power switch and to perform a control so that the voltage level of a virtual reference potential becomes about 0.2 V to about 0.3V. The region operates on voltages between a power supply voltage and a virtual reference potential, so that it is controlled in the low-speed mode.

Abstract: A low leakage power management system is provided. An external voltage domain is selectively coupled to the internal voltage domain of an integrated circuit according to demand for the functions provided by the integrated circuit. An external voltage VDD is connected to the internal supply voltage plane of the integrated circuit when the integrated circuit is active. The external supply voltage VDD is disconnected from the integrated circuit chip during idle periods. A plurality of switch cells may be provided for connecting the external voltage VDD to the integrated circuit. A multi-step sequence is provided for connecting the external supply voltage VDD to the chip's internal supply voltage plane to prevent excessive current from flowing through any individual switch cell.

Abstract: A method is provided that permits the detection of ‘standby’ state’ in linear and non-linear loads connected to the power grid and their automatic disconnection. The method includes five main stages: a) detecting the normal operating state of at least one load by a detection device, b) obtaining the maximum value of the current in the operating state, c) detecting entry into ‘standby’ mode’ by the load by establishing the ‘standby’ state’ when the current value measured at a specific time in each load is less than a percentage P of the maximum value of the current of each load in normal operating state, d) evaluating the value for each load for a predetermined time T, and e) disconnecting the load and the detection device when value T of time is reached without the load having returned to the normal operating state. A system is also provided.

Abstract: A resume device is provided. The device detects voltage variation in standby mode. When a big voltage variation is detected, a resume process is run and a sound is played. Volume of the sound is adjustable and power is maintained within a proper range. Thus, power consumption is saved, efficiency is improved and resume process is enhanced.

Abstract: A device and a method for estimating a current; the method includes: setting an impedance of a power gating circuit to a measurement value; wherein the power gating circuit selectively provides power to a circuit of an integrated circuit; measuring, during a measurement period, an electrical parameter indicative of a current that flows through the power gating circuit; and reducing an impedance of the power gating circuit to a power provision value to reduce a voltage developed on the power gating circuit during a power provision period.

Abstract: A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.

Abstract: A power consumption of a light-receiving device is reduced while a power consumption of a microcomputer that controls the light-receiving device is reduced as well. The microcomputer is structured to include a drive circuit, a sampling/detection circuit, a timer, a system clock generation circuit, a CPU, a ROM and a RAM. The CPU stops providing the light-receiving device with a power supply by turning off a P channel type MOS transistor with the drive circuit and sets the microcomputer in a standby state for a predetermined period of time. When the microcomputer is released from the standby state, the CPU starts providing the light receiving device with the power supply by turning the P channel type MOS transistor on with the drive circuit.

Abstract: A method and apparatus is taught for reducing drain-source leakage in MOS circuits. In an exemplary CMOS inverter, a first transistor causes the body of an affected transistor to be at a first body potential. A second transistor brings the body potential of the affected transistor to a second body potential by providing an accurate body voltage from a body voltage source. Exemplary body bias voltage sources are further described that can drive one or more gate transistors of different gate circuits.

Abstract: A method and system for conserving battery power in a portable communication device. When a user puts the device into a media player mode such as by invoking a media player application on the device, the device will automatically reduce the extent to which it engages in background wireless transmissions, such as radio link control messaging, presence update messaging, and so forth, to help conserve battery power. In turn, when the device exits the media player mode, the device may then automatically revert to its normal extent of background wireless transmission.

Abstract: A system includes first, second, and third circuits and first and second capacitors. The first capacitor has a first power supply terminal coupled to positive power supply terminal, a second power supply terminal, and an input/output. The second capacitor has a first power supply terminal coupled the second power supply terminal of the first circuit, a second power supply terminal, and an input/output. The third circuit has a first power supply terminal coupled the second power supply terminal of the second circuit, a second power supply terminal, and an input/output. The first capacitor has a first terminal coupled to the input/output of the first circuit and a second terminal coupled to the input/output of the second circuit. The second capacitor has a first terminal coupled to the second terminal of the first capacitor and a second terminal coupled to the input/output of the third circuit.

Abstract: A system and method are disclosed to accomplish power savings in an electronic device, such as a memory chip, by performing selective frequency locking and subsequent instantaneous frequency switching in the DLL (delay locked loop) used for clock synchronization in the electronic device. By locking the DLL at a slow clock frequency, the operational frequency may be substantially instantaneously switched to an integer-multiplied frequency of the initial locking frequency without losing the DLL lock point. This DLL locking methodology allows for faster frequency changes from higher (during normal operation) to lower (during a power saving mode) clock frequencies without resorting to gradual frequency slewing to conserve power and maintain DLL locking. Hence, a large power reduction may be accomplished substantially instantaneously without adding complexity to the system clock generator. Because of the rules governing abstracts, this abstract should not be used in construing the claims.

Abstract: Embodiments of the present invention may provide a power-gating switch circuit. The power-gating switch circuit may comprise a first switch to connect a power supply to a virtual power supply and a second switch to connect the power supply to the virtual power supply in parallel to the first switch. The first switch may have a lower impedance than the second switch. When a wake up signal is received, the second switch may be turned on first and the first switch may be turned on after the virtual power supply reaches a predetermined voltage level.

Abstract: A system on chip (SoC) has a digital domain. An adaptive voltage/frequency scaling circuit includes a critical path replica circuit with respect to that digital domain. The critical path replica circuit generates a margin signal, and the adaptive voltage scaling circuit responds to the margin signal by decreasing bias voltage (and/or increasing clock frequency) applied to the digital domain of the system on chip so as to recover available margin. A fail-safe timing sensor is included within the digital domain of the system on chip. The timing sensor generates a flag signal when timing criteria within the digital domain are violated. The adaptive voltage scaling circuit responds to the flag signal by increasing the bias voltage (and/or decreasing the clock frequency) applied to the digital domain of the system on chip so as to implement a recovery operation.

Abstract: A semiconductor integrated circuit including: a circuit block having an internal voltage line; an annular rail line forming a closed annular line around the circuit block and supplied with one of a power supply voltage and a reference voltage; and a plurality of switch blocks arranged around the circuit block along the annular rail line, the plurality of switch blocks each including a voltage line segment forming a part of the annular rail line and a switch for controlling connection and disconnection between the voltage line segment and the internal voltage line.

Abstract: A semiconductor device includes a power-supply control portion and a latch portion. The power-supply control portion supplies power to an internal circuit in response to an input signal synchronized with rising of clock. The latch portion latches the input signal in synchronization with falling of the clock and supplies the latched input signal to the internal circuit.

Abstract: A leakage manager system for adequately minimizing static leakage of an integrated circuit is disclosed. The leakage manager system includes a generator configured to generate a control signal to be applied to a sleep transistor. A monitor is configured to determine whether to adjust the control signal to adequately minimize the static leakage. In some embodiments, the monitor includes an emulated sleep transistor. A regulator is configured to adjust the control signal depending on the determination.

Abstract: A leakage current suppressing circuit includes a bias generating unit and a switch unit. The bias generating unit is adapted to be coupled to a power source and an output terminal, and generates a bias voltage substantially equal to a voltage at the power source when the power source is turned on, and substantially equal to a voltage at the output terminal when the power source is turned off. The switch unit includes a first P-type transistor having a first terminal adapted to be coupled to the power source, a second terminal adapted to be coupled to the output terminal, a gate terminal, and a body terminal coupled to the bias generating unit for receiving the bias voltage therefrom.

Abstract: In an electronic device with power saving function, when the power saving function of the electronic device is active, the electronic device detects the distance between any object in a proximal area of the electronic device and the electronic device and stores the detected distance as an original distance, and then periodically detects the distance between the object and the electronic device, and stores the detected distance as a current distance. The electronic device is put into power saving mode if an difference between the original distance and the current distance does not fall into the predetermined range.

Abstract: An integrated circuit, that includes: (i) a power gating switch, the power gating switch includes (a) an input port for receiving an input supply voltage; (b) an output port for outputting an output supply voltage; and (c) a control port for receiving a control signal that determines a difference between a value of the input supply voltage and a value of the output supply voltage; (ii) a power gated circuit, coupled to the output port of the switch, for receiving the output supply voltage; (iii) a mode indicator generator for generating a mode indicator that indicates of a desired mode of the power gated circuit; (iv) a leakage indicator generator for generating a leakage indicator that indicates of a leakage level of the power gated circuit; and (iv) a control circuit, for receiving the mode indicator and the leakage indicator, and for selecting the value of the control signal based on the mode indicator and on the leakage indicator.

Abstract: Power management systems and methods that facilitate efficient and effective power conservation are presented. In one embodiment a power management method comprises: performing an initiation metric determination process, and adjusting operations of a logic component based on said threshold value. In one exemplary implementation, the initiation metric determination process includes monitoring activity of a logic component, and establishing a power conservation initiation threshold value. The initiation metric determination process can include performing a system architecture characteristic analysis in which a system architecture power-consumption break-even time (BE) is determined for the system. The initiation metric determination process can also include performing a system utilization analysis process is performed in which idle period durations detected during said monitoring are sorted into a variety of different length intervals and analyzed accordingly.

Abstract: A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.

Abstract: A semiconductor integrated circuit includes: an internal circuit; a detecting circuit which detects an element characteristic of the internal circuit; a calculating circuit which calculates a first consumption energy consumed when a power gating operation is performed on a task processed by the internal circuit and a second consumption energy consumed when an operation of reducing a voltage and a frequency is performed in accordance with the element characteristic; and a switching circuit which performs the power gating operation on the internal circuit when the first consumption energy is smaller than the second consumption energy and performs the operation of reducing a voltage and a frequency when the second consumption energy is smaller than the first consumption energy.

Abstract: An integrated circuit, comprises a wakeup terminal; a supply voltage terminal configured to receive a supply voltage; and a power control circuit. The power control circuit comprises an enable circuit coupled to the wakeup terminal and configured to generate a voltage monitoring enable signal as a response to a wakeup signal received at the wakeup terminal, and a voltage monitoring circuit for generating a supply voltage level indication signal. The voltage monitoring circuit is coupled to the supply voltage terminal and comprises an operation switch controlled by the voltage monitoring enable signal. The voltage monitoring circuit is configured to determine if the supply voltage is above a threshold voltage and set the supply voltage level indication signal accordingly. The integrated circuit further comprises processing circuitry, with the supply voltage level indication signal controlling the switching between a normal operation state and a standby state of the processing circuitry.

Abstract: A mobile telephone is provided that includes a plurality of circuit blocks and adapted to cut off the supply of power source voltage to any one of the circuit blocks. The mobile telephone also includes an interblock interface circuit provided on a signal path between an elected circuit block and a branch point at which the signal path branches into different branch paths so as to connect to other circuit blocks. The interblock interface circuit includes a signal gate for preventing signal transmission from the elected circuit block to the other circuit blocks, and includes a storage unit for storing a signal right before the power cut-off.

Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.

Abstract: The present invention is directed to perform fine low-voltage control without largely increasing the circuit layout area in a low-power consumption structure. In the case of shifting a region to a low-speed mode, a system controller outputs a request signal and an enable signal to a power switch controller and a low-power drive circuit, respectively, to turn off a power switch and to perform a control so that the voltage level of a virtual reference potential becomes about 0.2 V to about 0.3V. The region operates on voltages between a power supply voltage and a virtual reference potential, so that it is controlled in the low-speed mode.

Abstract: A system and method for managing battery slump in a battery-powered communications device including: an input configured for receiving battery voltage level information; an output configured for sending a signal for terminating a transmission; and a controller connected to the input and the output and configured to receive the battery voltage level information from the input; monitor the battery voltage level information; and send a signal via the output to terminate a transmission if the battery voltage level information crosses a predetermined threshold during the transmission. In particular, the system and method may further include an input connected to the controller and configured for receiving a signal indicating when a transmission is beginning or occurring and the controller is further configured to receive and monitor the battery voltage level information only when the transmission is occurring.

Abstract: In a two-conductor technology circuit the use of certain ASIC components is made possible which, for instance, allow for the supply of contact-free rotational angle sensors, although said ASIC components have a high current consumption.

Abstract: A current mirror circuit is provided with a first current mirror including first and second mirror transistors sharing a common control terminal; the first mirror transistor has a conduction terminal for receiving, during a first operating condition, a first reference current, and the second mirror transistor has a respective conduction terminal for providing, during the first operating condition, a mirrored current based on the first reference current. The current mirror circuit is provided with a switching stage operable to connect the control terminal to the conduction terminal of the first mirror transistor during the first operating condition, and to disconnect the control terminal from the same conduction terminal of the first mirror transistor, and either letting it substantially float or connecting it to a reference voltage, during a second operating condition, in particular a condition of stand-by.

Abstract: A semiconductor integrated circuit that carries out intermittent operation, includes a processor block; an logical operation block other than a processor; a first switch part configured to supply a normal operation voltage to the logical operation block other than a processor; a second switch part configured to supply the normal operation voltage to the processor block; a third switch part configured to supply a data holding voltage lower than the normal operation voltage to the processor block; and a fourth switch part configured to be turned on, when the second switch means is turned off and the third switch means is turned on, and supply the data holding voltage to the processor block.

Abstract: A semiconductor integrated circuit includes: a first flip-flop, a combined circuit and a second flip-flop that form a critical path; a first delay circuit and a third flip-flop that are provided in the post-stage of the combined circuit; a second delay circuit and a fourth flip-flop that are provided in the post-stage of the combined circuit; a first comparison circuit that compares the output of the second flip-flop with the output of the third flip-flop; a second comparison circuit that compares the output of the second flip-flop with the output of the fourth flip-flop: and a control circuit that controls a source voltage supplied to the combined circuit in accordance with the outputs of the comparison circuits. A delay time by the first delay circuit is different from a delay time by the second delay circuit.