Abstract: This disclosure is directed to a method, computer program product and mobile communication device configured for managing radio states in a mobile communication device using device mobility information. A mobility state is determined from the number of cell changes over a predefined period of time. If the mobility state transitions to medium or high, such as when the user is in a vehicle, a Bluetooth™ radio is enabled. If a connection to a Bluetooth™-enabled device is available, a connection is established. When the connection is disconnected, a configurable timer is started. If the timer expires without re-establishing the connection or the mobility state transitioning to medium or high, the Bluetooth™ radio is disabled to reduce power consumption. According to an embodiment, a Wi-Fi radio may then be enabled to establish a Wi-Fi connection. Various configurations of computer program products and mobile communication devices are also described.

Abstract: Circuits (1) for receiving output signals from transformers (2) comprise filters (11) and switches (12). In the case of magnetic/electronic transformers, the filters (11) are activated/deactivated, for example for filtering/not filtering unwanted signals coming from converters (4). The filters (11) may comprise capacitors. The switches (12) may comprise fuses. Output signals of magnetic/electronic transformers comprise relatively low/high frequency signals that result in relatively small/large currents flowing through the capacitors, which currents will not blow/blow the fuses. The capacitors, when activated, form, together with leakage inductances of the magnetic transformers, electromagnetic interference filters. Alternatively, the circuits (1) may further comprise detectors (13) for detecting transformer types and for controlling the switches (12) in response to detection results.

Abstract: A circuit according to an example includes a digital-to-time converter configured to receive an oscillator signal and to generate a processed oscillator signal based on the received oscillator signal in response to a control signal, and a time-interleaved control circuit configured to generate the control signal based on a time-interleaved technique.

Abstract: Methods, apparatus, and integrated circuits that provide radiation hardening through chip level integrated recovery are provided. The apparatus may include first and second circuits within a partition of an integrated circuit and a state machine configured to monitor current leakage of the first circuit while the first circuit is powered on and to power on the second circuit and power off the first circuit when the monitored first circuit current leakage exceeds a first current leakage threshold. The method may include powering a first circuit of a partition within an integrated circuit, monitoring current leakage of the first circuit while the first circuit is powered on and the second circuit is powered off, and powering off the first circuit and powering on the second circuit when the monitored first circuit current leakage exceeds a first current leakage threshold.

Abstract: A semiconductor device includes first power lines through which first power is supplied, a plurality of unit regions defined by the first power lines, and second power lines through which second power is supplied. Each of the unit regions includes a logic circuit suitable for operating by receiving the first power from at least one of the first power lines during a normal mode, and a retention circuit suitable for operating by receiving the second power from at least one of the second power lines, receiving data from the logic circuit when an operation mode changes from the normal mode to a sleep mode, and keeping the data during the sleep mode. The logic circuit is electrically separated from the second power lines.

Abstract: Internal voltage generation circuits are provided. The internal voltage generation circuit includes a drive controller and an initialization unit. The drive controller detects a level of an internal voltage signal in response to a reference voltage signal to generate a drive signal and drives the internal voltage signal in response to the drive signal. The initialization unit initializes the drive signal in synchronization with an internal command signal and terminates an initialization of the drive signal during a predetermined period.

Abstract: A scan flip-flop circuit includes an input unit and an output unit. The data output unit is configured to provide a data output terminal with a data output signal in response to a data input signal and a first control signal in a first operation mode, and the data output unit is configured to prohibit the data output terminal from being provided with a power supply voltage and a ground voltage applied to the scan flip-flop circuit in response to the data input signal and the first control signal in a second operation mode. The scan output unit is configured to provide a scan output terminal with a scan output signal in response to a scan input signal and a second control signal in the second operation mode.

Abstract: A quadrature phase signal generator comprises a relative delay unit, a phase detector, a first amplifier and a loop filter. The relative delay unit delays differential input signals and generates four delayed signals. The phase detector generates quadrature four phase output signals, a first voltage signal and a second voltage signal according to the four delayed signals. A difference of the first and the second voltage signals indicates a phase error of the quadrature four phase output signals. The first amplifier amplifies the voltage difference of the first and the second voltage signals. The loop filter filters the amplified voltage difference and generates a tuning voltage signal. The loop filter is further communicatively coupled to the relative delay unit. The relative delay unit adjusts a delay of the quadrature four phase delayed signals according to the tuning voltage signal.

Abstract: A charge pump system includes a comparator having a first input coupled to a first reference voltage, a second input coupled to a feedback signal and an output coupled to control operation of a voltage controlled oscillator. The feedback signal is coupled to an output of the charge pump system. An amplifier has a first input coupled to a second reference voltage, a second input coupled to the feedback signal, and an output coupled as input to the voltage controlled oscillator. A gain of the amplifier is lower than a gain of the comparator.

Abstract: A voltage detecting system is configured for detecting a voltage supplied to an electronic device. The voltage detecting system includes a voltage measuring circuit configured to measure the voltage, a voltage converting circuit electrically coupled to the voltage, and a voltage comparing circuit. The voltage measuring circuit has a first measuring range and a second measuring range that is wider than the first measuring range. The voltage converting circuit is capable of the converting the voltage to an output voltage according to a predetermined ratio. The voltage comparing circuit compares the output voltage with a reference voltage. If the output voltage is greater than the reference voltage, the voltage comparing circuit informs the voltage measuring circuit to select the second measuring range. If the output voltage is not greater than the reference voltage, the voltage comparing circuit informs the voltage measuring circuit to select the first measuring range.

Abstract: An aging monitor circuit that provides a more accurate estimate of aging and/or delay in a circuit and/or circuit path. The aging monitor circuit employs a separate aging path with driving and receiving flip flops (FFs) and a tunable replica circuit (TRC) to enable measurements of single-transition DC-stressed path delay that only propagates through stressed transistors or other circuit element(s). A finite state machine (FSM) in the aging monitor circuit is configured to adjust a frequency of a clock signal output by a digitally controlled oscillator (DCO) in response to an error signal output by the receiving FF. The error signal is generated in response to single-transition DC-stressed path delay; and therefore enables the adjustment of the frequency of the dock signal to correspond to an amount or effect of the delay.

Abstract: A communication device using a current wireless network via a first access point confirms availability of a second access point before breaking the current connection. To confirm availability of the second access point, the communication device sends a power management message that causes the first access point to store packets during the power management period. After the connection to the second access point is confirmed, the second session may be put on hold using the same technique while the connection to the first access point is restored, the stored packets processed and the connection closed. Then the connection to the second access point may be reactivated and further communication made through the second access point.

Abstract: A data buffer system includes a plurality of data buffer modules and a plurality of switching units. The data buffer module is configured for buffering a corresponding data signal. The data buffer module includes a plurality of buffers. The buffers are electrically coupled in series. The switching unit is configured for supplying power to the corresponding buffer in accordance with a regulated voltage. Each of the switching units is electrically coupled between the corresponding one of the buffers and the supply voltage. A power control method for a data buffer system is also provided.

Abstract: A pulse converter circuit includes a logic circuit to which a first signal is input and from which a second signal is output. The logic circuit includes a p-channel transistor which determines whether a voltage of the second signal is set to a first voltage depending on a voltage of the gate; and an n-channel transistor which determines whether the voltage of the second signal is set to a second voltage, which is higher than the first voltage, depending on a voltage of the gate. The p-channel transistor includes a semiconductor layer containing an element of a group 14. The n-channel transistor includes an oxide semiconductor layer.

Abstract: A capacitance sensing module includes a timer circuit configured to generate a repetitive trigger signal, a low power oscillator block configured to generate a clock signal having a higher frequency than the repetitive trigger signal, a sensing block coupled with the timer circuit and the oscillator block and configured to, in response to the repetitive trigger signal, detect a presence of a conductive object at a capacitive sensor button by applying an excitation signal based on the clock signal to the capacitive sensor button, and a wake logic block coupled with the sensing block and configured to transition a processing unit from a low power consumption state to a high power consumption state in response to the sensing block detecting the presence of the conductive object at the capacitive sensor button.

Abstract: An electronic device includes a power supply, a current measuring unit, a converter, a plurality of devices, and a control unit. The current measuring unit measures a current value of current that is output from the power supply. The voltage and the current from the power supply are input into the converter, and the converter converts the input voltage into voltage of a different voltage value, and outputs the voltage thus converted and the current. The control unit controls the converter to output voltage of a voltage value corresponding to a minimum current value measured by the current measuring unit, in which the voltage is voltage of a voltage value between a maximum value of lower limit voltage and a minimum value of upper limit voltage within an operating voltage range of one or a plurality of devices that operate in the energy saving mode.

Abstract: Embodiments of transceiver circuits and methods for operating a transceiver circuit are described. In one embodiment, a transceiver circuit includes a feedback loop connected to a bus and a control circuit connected to the bus. The feedback loop includes a tunable low-pass filter. The control circuit is configured to detect a radio frequency (RF) disturbance on the bus and control the bandwidth of the tunable low-pass filter in response to detection of the RF disturbance on the bus. Other embodiments are also described.

Abstract: A power-gating circuit and devices including the same are provided. The power-gating circuit includes a flip-flop configured to receive a first power supply voltage and a gated clock signal to operate and a switch circuit connected between a first power supply voltage source configured to supply the first power supply voltage and a second power supply voltage source configured to supply a second power supply voltage. The switch circuit includes a first switch configured to be connected between the first power supply voltage source and the second power supply voltage source and to operate in response to a clock enable signal and a second switch configured to be connected between the first power supply voltage source and the second power supply voltage source and to operate in response to the first power supply voltage.

Abstract: A power supply unit includes a first power supply configured to supply electric power to a load using electric power supplied from an external power source; a second power supply configured to store the electric power supplied from the external power source and supply the stored electric power to the load; a no-power detecting unit configured to monitor a voltage of the external power source and detect no electric power from the external power source; and an output switching unit configured to switch the electric power to be supplied to the load to the electric power supplied from the second power supply when the no-power detecting unit detects no electric power. A first setting value that is a target output voltage of the first power supply is larger than a second setting value that is a target output voltage of the second power supply.

Abstract: Inventive aspects include a method, apparatus, and system for reducing power switch cells in MTCMOS circuits. Such may include disposing columns of real and virtual power straps orthogonally over rows of logic cells. A first power switch cell can be disposed over a real and a virtual power strap in a first column, and collinear with a first row of logic cells. A second power switch cell can be disposed over a real a virtual power strap in a second column, and collinear with a fifth row of logic cells. A third power switch cell can be disposed over a real a virtual power strap in a third column, and collinear with a third row of logic cells. A fourth power switch cell can be disposed over a real a virtual power strap in a fourth column, and collinear with a seventh row of logic cells.

Abstract: The present invention relates to a bidirectional semiconductor switch (M1, M2) with extremely low control power consumption and a bootstrap circuit which allows reliable start of operation of the switch and the hosting device after unlimited duration of mains interruptions. Intelligent control options are provided by operating from a small energy storage and no extra means are required to recover from a depleted energy storage condition. The absence of audible noise and mechanical wear also enables more frequent recharging cycles and allows smaller and thus cheaper energy storage components.

Abstract: A system and method are disclosed to accomplish power savings in an electronic device, such as a memory chip, by performing selective frequency locking and subsequent instantaneous frequency switching in the DLL (delay locked loop) used for clock synchronization in the electronic device. By locking the DLL at a slow clock frequency, the operational frequency may be substantially instantaneously switched to an integer-multiplied frequency of the initial locking frequency without losing the DLL lock point. This DLL locking methodology allows for faster frequency changes from higher (during normal operation) to lower (during a power saving mode) clock frequencies without resorting to gradual frequency slewing to conserve power and maintain DLL locking. Hence, a large power reduction may be accomplished substantially instantaneously without adding complexity to the system clock generator. Because of the rules governing abstracts, this abstract should not be used in construing the claims.

Abstract: A semiconductor integrated circuit and an integrated circuit, each of which includes multiple regions containing at least one switchable region to switch between supplying power and blocking power individually; a power supply controller to control switching supplying power and blocking power in the switchable region that switches supplying power and blocking power individually; a power supply variable impedance circuit to change a power supply impedance of the semiconductor integrated circuit; and a power supply impedance controller to obtain the power supplying state of the region from the power supply controller, to cause the power supply variable impedance circuit to change the power supply impedance, based on a supply state of the power in the switchable region.

Abstract: In one embodiment, an integrated circuit (IC) device includes a first logic block having performance characteristics, a first critical path monitor (CPM) configured to monitor the performance characteristics of the first logic block, and a first CPM envelope circuit enveloping the first CPM. The first logic block is configured to operate in at least one of a first functional mode and a first scan mode. The first CPM is adapted to operate in at least one of a second functional mode and a second scan mode. The first and second functional modes use higher clock frequencies, respectively, than the first and second scan modes. The first CPM envelope circuit comprises a clock-gate circuit adapted to allow the IC device to operate in a mixed mode, wherein the first CPM operates in the second functional mode while the first logic block operates in the first scan mode.

Abstract: Embodiments described in the present disclosure relate to a method for providing power for an integrated system, including acts of: providing the system with power, ground and body bias voltages, the body bias voltages comprising a body bias voltage of p-channel MOS transistors, greater or lower than the supply voltage, and a body bias voltage of n-channel MOS transistors, lower or greater than the ground voltage, selecting by means of the system out of the voltages provided, depending on whether a processing unit of the system is in a period of activity or inactivity, voltages to be supplied to bias the bodies of the MOS transistors of the processing unit, and providing the bodies of the MOS transistors of the processing unit with the voltages selected.

Abstract: A digital power gating system for performing power gating to reduce a voltage of a gated supply bus to a state retention voltage level that reduces leakage current while retaining a digital state of a functional circuit. The power gating system includes gating devices and a power gating control system. Each gating device has current terminals coupled between a global supply bus and the gated supply bus, and a control terminal controlled by a bit of a digital control value. The power gating control system successively adjusts the digital control value to reduce a voltage of the gated supply bus to the state retention voltage level. Adjustment gain and/or adjustment periods may be changed, such as when the digital control value reaches certain values or when the gated supply reaches certain voltage levels. Various parameters are programmable to adjust for particular configurations or to achieve desired operation.

Abstract: The application discloses a voltage regulation method, and a corresponding HPM, chip, and chip system. The method is used to regulate a working voltage of the chip, which includes an AVS module and at least one HPM. The method includes: outputting, by the AVS module, a clock signal to the HPM; generating, by the HPM, a corresponding pulse signal according to the clock signal and at least performing first delaying for the pulse signal to acquire a first actual output value and performing second delaying for the pulse signal to acquire a second actual output value; and fitting, by the AVS module, the first and second actual output values at least according to weights of the first and second actual output values to acquire a fitting output value and determine, by comparing the fitting output value with a predetermined reference value, whether to regulate the working voltage of the chip.

Abstract: An integrated circuit (IC) includes an adaptive voltage scaling (AVS) controller configured to control a voltage supplied to a portion of the IC and at least one sensor configured to sense at least one state of the IC and to provide an output signal indicative of the at least one sensed state to the AVS controller, the IC having a first setting and a second setting, the AVS controller being configured to use the output signal to control the voltage in the first setting and the AVS controller being configured to control the voltage independently of the output signal in the second setting. Also a method of performing AVS is provided.

Abstract: There is disclosed a switching arrangement comprising a switch with a plurality of individually controllable elementary switches connected in parallel between a first supply rail and a second supply rail. Each of the elementary switches can be in either one of a closed state and an open state independently of the others. A controller is adapted to dynamically control the closing or opening of the elementary switches, depending on the intensity of a current flowing through the switch. The number of elementary switches in the closed state is variable. The higher is the intensity of the current, the higher the number of elementary switches in the closed state. Thus, the impedance of the switch decreases when the current increases, and vice versa, and the voltage drop across the switch may be kept substantially constant.

Abstract: An integrated circuit including a global supply bus, a gated supply bus, and a digital power gating system with controlled resume. The digital power gating system includes gating devices and a power gating control system. Each gating device has a pair of current terminals coupled between the global supply bus and the gated supply bus and each has a control terminal. The power gating control system controls a digital control value which controls activation of the gating devices. The power gating control system is configured to successively adjust the digital control value to increase a voltage of the gated supply bus from a reduced voltage level to a normal operating voltage level in response to a resume indication. The reduced voltage level may be a state retention level or full power gating. Successive adjustment may be with constant or adjusted gain using a constant clock or a dynamically adjusted clock.

Abstract: A semiconductor device that makes isolation circuits unnecessary and that also resolves the problem of through-current flowing during power supply shutdown transitions and during power supply recovery and that even flows between the regions during power shutdown. A semiconductor device of the present invention including a first power supply line, and a second power supply line coupled to a first power supply line by way of a first switch, a macro cell containing a macro cell core coupled to the second power supply line, and a third power supply line coupled by way of a second switch to a first power supply line, and a circuit block coupled to the third power supply line and also coupled to at least either the macro cell core input or output; and the second power supply line is coupled to the third power supply line.

Abstract: A diagnostic imaging device includes a signal processing circuit (22) processes signals from a detector array (16) which detects radiation from an imaging region (20). The hit signals are indicative of a corresponding detector (18) being hit by a radiation photon. The signal processing circuit (22) includes a plurality of input channels (321, 322, 323, 324), each input channel receiving hit signals from a corresponding detector element (18) such that each input channel (321, 322, 323, 324) corresponds to a location at which each hit signal is received. A plurality of integrators (42) integrate signals from the input channels (32) to determine an energy value associated with each radiation hit. A plurality of analog-to-digital converters (441, 442, 443, 444) convert the integrated energy value into a digital energy value. A plurality of time to digital converters (40) receive the hit signals and generate a digital time stamp.

Abstract: A well-biasing circuit for an integrated circuit (IC) includes a well-bias regulator for providing well-bias voltages (n-well and p-well bias voltages) to well-bias contacts (n-well and p-well bias contacts) of each cell of the IC when the integrated circuit is in STOP and STANDBY modes. A switch is connected between a core power supply and the well-bias contact for connecting and disconnecting the core power supply and the well-bias contact when the IC is in RUN and STOP modes, and STANDBY mode, respectively. A voltage inverter circuit and a CMOS inverter circuit enable and disable the switch when the IC is in the RUN mode, and STOP and STANDBY modes, respectively.

Abstract: A power gating circuit includes a first current switch, a second current switch, and a switching controller. The first current switch is connected between a power rail and a circuit block operated by an operating supply voltage, and provides a first current when turned on. The second current switch is connected between the power rail and circuit block, and provides a second current larger than the first current when turned on. The switching controller turns on first current switch when transitioned from a sleep mode to an active mode to change the operating supply voltage using the first current, generates a reference voltage based on the operating supply voltage that changes more slowly than the operating supply voltage, and turns on the second current switch based on the reference voltage to provide the second current to the circuit block.

Abstract: A method and apparatus for controlling a device in electronic equipment having a plurality of devices are provided. The apparatus includes a power supply for supplying power, a slave device including a driving circuit operated according to the supplied power for transmitting and receiving data to and from another device, a switching circuit for connecting the driving circuit to a ground terminal when the switching circuit is turned-on and for opening the driving circuit from the ground terminal when the switching circuit is turned-off, and a host device for transmitting a control signal for turning-on the switching circuit when driving the slave device and for turning-off the switching circuit when not driving the slave device. When the device is not driven, the switching circuit may open a driving circuit from a ground terminal, thereby cutting-off leakage of an electric current through the device.

Abstract: An apparatus for monitoring timing of a plurality of critical paths of a functional circuit includes a plurality of canary circuits, each configured to be coupled to a critical path of a functional circuit for detecting and outputting critical timing events. Each canary circuit includes an adjustable delay element and an analyzer circuit for receiving a count of the critical timing event output from at least one of the plurality of canary circuits for a predetermined time interval for a plurality of delay values of the adjustable delay elements and for determining a probability distribution of critical timing events of the at least one of the plurality of critical paths for the predetermined time interval for the plurality of delay values.

Abstract: A semiconductor device comprises a plurality of circuit blocks, a plurality of local wirings which supply power to the plurality of circuit blocks, respectively, a global wiring which supplies the power to the plurality of local wirings, a plurality of first switches which are disposed between the plurality of local wirings, respectively, and the global wiring, and a second switch which is disposed between two local wirings. A power control unit controls open/close of the plurality of first switches and the second switch based on the potential difference between the two local wirings.

Abstract: An apparatus includes a processor and a device. The processor generates an output signal and a control signal. The device consumes power while operating in first and second states. The device consumes less power while in the first state than while in the second state. The processor: accounts for a transition time for the device to transition among a powered off state, the first state, and the second state; and generates the control signal based on the transition time. The device: in response to the control signal, transitions to the second state at a speed of periodicity of a periodic signal of the processor; subsequent to the transitioning to the second state, performs a function based on the output signal; and subsequent to performing the function, transitions from the second state to either the first state or the powered off state.

Abstract: Power management systems and methods that facilitate efficient and effective power conservation are presented. In one embodiment a power management method comprises: performing an initiation metric determination process, and adjusting operations of a logic component based on said threshold value. In one exemplary implementation, the initiation metric determination process includes monitoring activity of a logic component, and establishing a power conservation initiation threshold value. The initiation metric determination process can include performing a system architecture characteristic analysis in which a system architecture power-consumption break-even time (BE) is determined for the system. The initiation metric determination process can also include performing a system utilization analysis process is performed in which idle period durations detected during said monitoring are sorted into a variety of different length intervals and analyzed accordingly.

Abstract: A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.

Abstract: A digital signal processing apparatus includes a digital circuit device having one or more elements configured to process digital data; a power supply configured to deliver a controllable operating voltage for the one or more elements; control logic configured to receive feedback signals from each of the one or more elements, the feedback signals indicative of a rate at which data is moving through each individual element; and the control logic configured to output a control signal to the power supply so as to cause the power supply to reduce the operating voltage for the one or more elements responsive to a decreasing workload detected therein, and to cause the power supply to increase the operating voltage for the one or more pipelines responsive to an increasing workload detected therein.

Abstract: Systems, methods, and computer readable media that can mitigate the effects of semiconductor aging in a semiconductor device are described. Traditional methods of mitigating semiconductor aging can be wasteful since they overcorrect for aging using a high operational voltage. The approach discussed herein steps up the operational voltage for the electronic device with time based on predetermined aging models. This allows power consumption by the electronic device, particularly early in the designed operational life, to be much less than it would otherwise be.

Abstract: A semiconductor memory circuit includes: a plurality of memory regions; a plurality of driving units configured to be enabled in response to a plurality of enable signals, respectively, and generate a predetermined voltage used for operations of the plurality of memory regions; and an enable control unit configured to count a control pulse and activate one or more enable signals among the plurality of enable signals.

Abstract: An exemplary embodiment of the present invention relates to an active damper and a driving method thereof. An AC input passed through a dimmer is transmitted to an active damper through a rectification circuit. The active damper includes a damper resistor connected to the rectification circuit, a damper switch connected to the damper resistor in parallel, and a delay circuit delaying a turn-on time of the damper switch by a predetermined initial period from a turn-on time of the dimmer.

Abstract: In a multiphase electrical power assignment, a processor: receives instructions to connect a bi-directional power device to a multiphase premise power source; determines that the power device is to be coupled to a target phase's phase connection; confirms that the power device is not coupled to any phase connections; and couples the power device to the phase connection, where the power device's power signal is synchronized with the phase connection's power signal. When the power device is in a connected state, the processor: issues a command to place each phase connection switch in an open state; in response to confirming that the phase connection switches are in the open state, issues commands to the power device so that a power signal of the power device will be synchronized with the target phase; and closes the phase connection switch corresponding to the target phase.

Abstract: Adaptive voltage scalers (AVSs), systems, and related methods are disclosed. The AVSs are configured to adaptively adjust voltage levels powering a functional circuit(s) based on target operating frequencies and delay variation conditions to avoid or reduce voltage margin. In one embodiment, the AVS includes an AVS database. The AVS database can be configured to store voltage levels for various operating frequencies of a functional circuit(s) to avoid or reduce voltage margin. The AVS database allows rapid voltage level decisions. The voltage levels stored in the AVS database may be initial, minimum, learned, populated, explored, backed out, temperature-based, and/or age-based voltage levels according to disclosed embodiments to further avoid or reduce voltage margin. An AVS module may be a software-based module that consults the AVS database to make voltage level decisions. Providing the AVS module as a software-based module may allow flexibility in configuring the AVS module and/or the AVS database.

Abstract: A semiconductor device includes a semiconductor element; a body bias controller configured to generate a standby mode body bias control signal in a standby mode; and a body bias voltage generator configured to receive the standby mode body bias control signal from the body bias controller, generate a standby mode body bias voltage, and apply the standby mode body bias voltage to a body of the semiconductor element. The semiconductor device is capable of retaining data stored in a semiconductor element and blocking leakage current in the standby mode by controlling a body bias voltage, thereby increasing the integration degree of the semiconductor device.

Abstract: A semiconductor integrated circuit includes a logic circuit having a plurality of operation modes, a power source circuit that generates a power source voltage to be supplied to the logic circuit, a power source wiring that couples the power source circuit and the logic circuit, and a charge control block that holds charges for controlling the voltage of the power source wiring. The power source circuit generates a first power source voltage for causing the logic circuit to operate in a computing mode and a second power source voltage for causing the logic circuit to operate in a sleep mode. The charge control block includes a capacitor, a first switch, and a voltage supply unit that supplies the second power source voltage or a third power source voltage lower than the second power source voltage, to the capacitor.

Abstract: An analog interface processing circuit includes a first and second signal processing interface, a processing system connected to the first and second signal processing interfaces, a biasing voltage source switchably coupled to said first signal processing interface via a first switch assembly and switchably coupled to said second signal processing interface via a second switch assembly, and a first control output of said processing system controllably coupled to said first switch assembly and a second control output of said processing system controllably couple to said second switch assembly.

Abstract: A semiconductor integrated circuit includes: a first voltage line on which a specific one of a power-supply voltage and a reference voltage appears; a second voltage line; a plurality of circuit cells each receiving power generated as a difference between a voltage appearing on the second voltage line and the other one of the power-supply voltage and the reference voltage; a plurality of switch transistors connected in parallel between the first and second voltage lines to serve as switch transistors including switch transistors each having different conducting-state resistances; and a switch conduction control section for controlling a transition of each of the switch transistors from a non-conducting state to a conducting state by turning on the switch transistors at separate points of time.