Abstract: A memory subsystem is provided including an interface circuit adapted for communication with a system and a majority of address or control signals of a first number of memory circuits. The interface circuit includes emulation logic for emulating at least one memory circuit of a second number.

Abstract: An apparatus includes a current source, a current monitor circuit which monitors a current amount of the current source, and outputs a current amount signal corresponding to the current amount being monitored, a counter circuit which counts a count value based on the current amount signal, the count value corresponding to a period being taken until when the current amount reaches a predetermined value, and a control circuit which modifies an operation parameter for operating a circuit unit according to the count value.

Abstract: An apparatus and method for detecting noise in a power supply voltage. A circuit may include a voltage generation unit coupled to receive a power supply voltage, and a detection unit. The voltage generation unit may generate first and second voltages using the power supply voltage, and may vary the relationship therebetween responsive to fluctuations in the power supply voltage. A detection unit may detect the variations in the relationship between the first and second voltages that result from fluctuations in the power supply voltage. Responsive to detecting the variations, the detection unit may generate pulses to be provided to a counter. The counter may update a count value responsive to receiving pulses.

Abstract: In a semiconductor integrated circuit including plural types of transistors having different threshold voltages, a plurality of oscillators including respective types of transistors are provided. The respective oscillation frequencies of these oscillators are counted, and based on the count values, a voltage to be set on a power supply voltage device for the semiconductor integrated circuit is determined according to the count values.

Abstract: A low leakage power management system is provided. An external voltage domain is selectively coupled to the internal voltage domain of an integrated circuit according to demand for the functions provided by the integrated circuit. An external voltage VDD is connected to the internal supply voltage plane of the integrated circuit when the integrated circuit is active. The external supply voltage VDD is disconnected from the integrated circuit chip during idle periods. A plurality of switch cells may be provided for connecting the external voltage VDD to the integrated circuit. A multi-step sequence is provided for connecting the external supply voltage VDD to the chip's internal supply voltage plane to prevent excessive current from flowing through any individual switch cell.

Abstract: A semiconductor integrated circuit device includes: a target circuit whose at least power supply voltage is variable; a power supply voltage providing circuit feeding the target circuit with a power supply voltage; and a minimum energy point monitor circuit detecting an energy-minimizing power supply voltage which minimizes a change in the energy consumed by the target circuit upon a change in the power supply voltage. The power supply voltage delivered by the power supply voltage providing circuit is controlled so as to be equal to the energy-minimizing power supply voltage detected by the minimum energy point monitor circuit.

Abstract: Power switch units for microelectronic devices are disclosed. In one aspect, a microelectronic device may include a functional circuit, and a power switch unit to switch power to the functional circuit on and off. The power switch unit may include a large number of transistors coupled together. The transistors may include predominantly positive-channel, insulated gate field effect transistors, which have a gate dielectric that includes a high dielectric constant material. Power switch units having such transistors may tend to have low power consumption. In an aspect, an overdrive voltage may be applied to the gates of such transistors to further reduce power consumption. Methods of overdriving such transistors and systems including such power switch units are also disclosed.

Abstract: According to one exemplary embodiment, a power managing semiconductor die with reduced power consumption includes a power island including an event detection block and an event qualification block. The event detection block is configured to activate the event qualification block in response to an input signal initiated by an external event. The input signal is coupled to the event detection block, for example, via a bond pad situated in an I/O region of the power managing semiconductor die. The event qualification block is configured to determine if the external event is a valid external event. The event qualification block resides in a thin oxide region and the event detection block resides in a thick oxide region of the semiconductor die. The power managing semiconductor die further includes a power management unit configured to activate the event qualification block in response to power enable signal outputted by the event detection block.

Abstract: A circuit for reducing sleep state current leakage is described. The circuit includes a hardware unit selected from at least one of a latch, a flip-flop, a comparator, a multiplexer, or an adder. The hardware unit includes a first node. The hardware unit further includes a sleep enabled combinational logic coupled to the first node, wherein a value of the first node is preserved during a sleep state.

Abstract: In a semiconductor integrated circuit device, a circuit block has a first MOS transistor, and a leakage current control circuit having a second MOS transistor and a current source, a source and drain circuit of the second MOS transistor is formed between the power supply line of the circuit block and a voltage point where operating voltage is supplied. This current source is connected to the power supply line and in a first state, the power supply line is driven to a first voltage by the second MOS transistor. In a second state, the power supply line is controlled at a second voltage by current flow in the current source and, the voltage applied across the source and drain of the first MOS transistor in the second state is smaller than the voltage applied across the source and drain of the first MOS transistor in the first state.

Abstract: A leakage manager system for adequately minimizing static leakage of an integrated circuit is disclosed. The leakage manager system includes a generator configured to generate a control signal to be applied to a sleep transistor. A monitor is configured to determine whether to adjust the control signal to adequately minimize the static leakage. In some embodiments, the monitor includes an emulated sleep transistor. A regulator is configured to adjust the control signal depending on the determination.

Abstract: A system for reducing power consumption in a transistor-based system includes a measurement circuit and a comparator. The measurement circuit measures a delay of a transistor-based device and produces a control signal corresponding to the measured delay. The comparator compares the control signal to a predetermined threshold. Adjusting a power supply voltage of the transistor-based system based at least in part on a result of the comparison reduces the power consumed by the system.

Abstract: A microprocessor according to one embodiment includes a supply node providing a core voltage, a functional block, a charge node, select logic, and substrate bias logic. The functional block has multiple power modes and includes one or more semiconductor devices and a substrate bias rail routed within the functional block and coupled to a substrate connection of at least one semiconductor device. The select logic couples the substrate bias rail to the charge node when the functional block is in a low power mode and clamps the substrate bias rail to the supply node when the functional block is in a full power mode. The substrate bias logic charges the charge node to a bias voltage at an offset voltage relative to the core voltage when the functional block is in the low power mode. Semiconductor devices may be provided to clamp or otherwise couple the bias rail.

Abstract: Methods and circuits for optimizing performance and power consumption in a circuit design and circuit employing one or more lower threshold voltage (Lvt) cells or devices are described. A base supply voltage amplitude is determined for providing operating power for the circuit. The base supply voltage amplitude is a low or lowest voltage level that still satisfies a performance specification for the circuit. Providing a low or lowest base supply voltage level reduces or minimizes the standby (i.e., non-switching) power consumption in the Lvt device(s) since current leakage is reduced as the supply voltage level is reduced. Reducing the supply voltage level used to power the Lvt device(s) also reduces active power consumption for the circuit as well. Thus, total power consumption is optimized or reduced while still receiving the benefit of using Lvt devices to optimize or increase performance of a circuit layout and circuit.

Abstract: An example method for optimizing power consumption of digital circuits using dynamic voltage and threshold scaling (DVTS) is provided. A propagation delay of a signal through a portion of the circuit is determined and if the propagation delay does not meet a specified delay requirement, then a supply voltage and/or threshold voltage of the circuit is adjusted. Subsequently, a power consumption level of the circuit is determined and compared to previous power consumption levels. The supply and/or threshold voltage of the circuit can be readjusted to enable the circuit to meet specified power consumption requirements and the specified delay requirement, for example.

Abstract: A compensation circuit for reducing power consumption in at least one digital circuit includes a first sample circuit connected to a first supply voltage, a second sample circuit connected to a second supply voltage, and a controller connected to the first and second sample circuits. The first and second sample circuits are substantially functionally equivalent to one another but optimized for different regions of operation within a specified range of PVT conditions. The controller is operative to receive respective output signals from the first and second sample circuits, to monitor a functionality of the second sample circuit relative to the first sample circuit, and to adjust a level of the second supply voltage to ensure correct operation of the second sample circuit throughout the specified range of PVT conditions. The digital circuit is operative from the second supply voltage.

Abstract: A method and a device for controlling power of a mobile terminal are provided. The method of controlling power of a mobile terminal includes, activating a low power mode, and applying a predefined setting value for reducing power consumption by limiting some functions of the mobile terminal in the low power mode. Therefore, by providing a low power mode of limiting some functions of the mobile terminal, unnecessary battery consumption can be prevented.

Abstract: A semiconductor integrated circuit includes: a first voltage line on which a specific one of a power-supply voltage and a reference voltage appears; a second voltage line; a plurality of circuit cells each receiving power generated as a difference between a voltage appearing on the second voltage line and the other one of the power-supply voltage and the reference voltage; a plurality of switch transistors connected in parallel between the first and second voltage lines to serve as switch transistors including switch transistors each having different conducting-state resistances; and a switch conduction control section for controlling a transition of each of the switch transistors from a non-conducting state to a conducting state by turning on the switch transistors at separate points of time.

Abstract: A power-off controlling circuit and a power-off controlling method that control power-off of an integrated circuit based on the size of leakage currents. The power-off controlling circuit includes a model circuit section that includes a model circuit made by modeling a basic circuit of an integrated circuit, a voltage comparing circuit section that compares an output voltage charged by a leakage current occurred at the model circuit and a preset reference voltage, a decision circuit section that measures an arrival time until the output voltage reaches the reference voltage from the compared result and decides a size of the leakage current from the measured result, and a power-off controlling circuit section that controls power-off of the integrated circuit on the basis of the decided size of the leakage current.

Abstract: A semiconductor memory circuit includes: a plurality of memory regions; a plurality of driving units configured to be enabled in response to a plurality of enable signals, respectively, and generate a predetermined voltage used for operations of the plurality of memory regions; and an enable control unit configured to count a control pulse and activate one or more enable signals among the plurality of enable signals.

Abstract: Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.

Abstract: A method for reducing power consumption of an electronic device is disclosed. In one embodiment, an indication that an electronic device is oriented in a first orientation is received. An indication of rotation of the electronic device around an axis is received. A command is then generated to cause an electronic compass module disposed within the electronic device to transition from an idle operating state to an active operating state and to generate a compass heading.

Abstract: An apparatus is used to awake an electronic device to an active mode from a standby mode in case of change in the voltage of a power supply of the electronic device. The apparatus includes a power supply for supplying electricity, a switch connected to the power supply, a low-voltage reset unit connected to the switch, a micro-controller unit connected to the switch and a monitoring and awaking unit. The monitoring and awaking unit includes an actuator connected to the switch, a bias generator and the actuator through a comparator connected to the micro-processing unit. The control over the power supply by the switch causes change in the voltage of the actuator which cooperates with the bias generator and the comparator to generate an awaking signal to awake the micro-processing unit.

Abstract: A leakage current measurement circuit measuring a substrate leakage current and a gate leakage current in response to a variation in the size of an MOS transistor and a leakage current comparison circuit judging which one of the substrate leakage current and the gate leakage current is dominant. The leakage current measurement circuit includes a charge supply, a leakage current generator and a detection signal generator. The leakage current comparison circuit includes a charge supply, a leakage current comparator and a detection signal generator.

Abstract: A system and circuit for virtual power grid is disclosed. In one embodiment, a switch system for a virtual power grid includes a first transistor for connecting a power supply to a node of a virtual power grid for an isolated region of circuitry via the first transistor upon a receipt of a first control signal to turn on the first transistor. The switch system further includes a second transistor for connecting the power supply to the isolated region of circuitry via the second transistor upon a receipt of a second control signal to turn on the second transistor. In addition, the switch system includes a self-timed enable module for generating and forwarding the second control signal when a voltage level at the node of the virtual power grid which is charged by the power supply via the first transistor reaches a threshold voltage.

Abstract: An integrated circuit is provided that comprises a power switch that includes a control terminal and that is coupled between a power source node and a power sink node; first data storage circuit includes a data storage input and a data storage output, wherein the data storage output is coupled to the power switch control terminal; and a second data storage circuit includes a data storage input and a data storage output, wherein the data storage input is coupled to the power sink node.

Abstract: An integrated circuit includes a number of pads. The integrated circuit further includes a cascode transistor having an open drain connection to a first one of the pads. A bias generator circuit is included in the integrated circuit. The bias generator circuit has an output connected to a gate terminal of the cascode transistor. In a first mode of operation, the bias generator outputs a bias signal that is derived from an integrated circuit supply voltage present at a second one of the pads. However, in a second mode of operation provided when the integrated circuit supply voltage is not present, the bias generator generates the bias signal derived from a voltage present at the first one of the pads.

Abstract: By classifying an electro-phoretic display integrated circuit (EPD IC) into a digital routine module, a digital non-routine module, and an analog routine module, and by switching off the digital non-routine module and the analog routine module, power consumption of the EPD IC may be effectively reduced, and an available time of an integrated circuit card utilizing the EPD IC may also be lengthened.

Abstract: A logic gate is constructed of an insulated gate field effect transistor (MIS transistor) having a thin gate insulation film. An operation power supply line to the logic gate is provided with an MIS transistor having a thick gate insulation film for switching the supply and stop of an operation power source voltage. A voltage of the gate of the power source switching transistor is made changing in an amplitude greater than an amplitude of an input and an output signal to the logic gate. Current consumption in a semiconductor device configured of MIS transistor of a thin gate insulation film can be reduced and an power source voltage thereof can be stabilized.

Abstract: A power consumption of a light-receiving device is reduced while a power consumption of a microcomputer that controls the light-receiving device is reduced as well. The microcomputer is structured to include a drive circuit, a sampling/detection circuit, a timer, a system clock generation circuit, a CPU, a ROM and a RAM. The CPU stops providing the light-receiving device with a power supply by turning off a P channel type MOS transistor with the drive circuit and sets the microcomputer in a standby state for a predetermined period of time. When the microcomputer is released from the standby state, the CPU starts providing the light receiving device with the power supply by turning the P channel type MOS transistor on with the drive circuit.

Abstract: A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power gating power domain netlist from the parsed design of the integrated circuit, and placing and routing the automatic power gating power domain netlist to produce a layout for the integrated circuit. The parsing partitions a high-level power domain of the integrated circuit into one or more automatic power gating power domains. The automatic power gating power domains have substantially zero-cycle power up times, thereby enabling transparent operation. Furthermore, the automatic power gating power domains may be automatically inserted into designs of integrated circuits, thereby relieving integrated circuit designers of the task of inserting power domains and associated hardware and software.

Abstract: A microprocessor including a substrate bias rail providing a bias voltage during a first operating mode, a supply node providing a core voltage, a clamp device coupled between the bias rail and the supply node, and control logic. The control logic turns on the clamp device to clamp the bias rail to the supply node during a second operating mode and turns off the clamp device during the first operating mode. The clamp devices may be implemented with P-channel and N-channel devices. Level shift and buffer circuits may be provided to control the clamp devices based on substrate bias voltage levels. The microprocessor may include a substrate with first and second areas each including separate substrate bias rails. The control logic separately turns on and off clamp devices to selectively clamp the substrate bias rails in the first and second areas based on various power modes.

Abstract: An exemplary voltage regulating circuit for a motherboard includes a selecting switch and a first switch module, the selecting switch comprising a first input terminal arranged to receive a standby power provided by a power supply, a first control terminal arranged to receive a state signal from the motherboard via a first switch module controlled by a power good signal generated by the power supply, and an output terminal, wherein, when the motherboard is turned off, the state signal is at a high level and the first switch module is turned on by the power good signal for turning off the selecting switch to stop outputting the standby power.

Abstract: A dormant mode target semiconductor device within a leakage current target unit is identified for mitigating leakage current to prevent it from reaching catastrophic runaway. A leakage current shift monitor unit is electrically connected to the output node of the leakage current target unit and collects leakage current from the selected target semiconductor device for two consecutive predefined temporal periods and measures the difference between the collected leakage currents. A comparator receives and compares the outputs of the current shift monitor unit and a reference voltage generator. The comparator propagates an alert signal to the leakage current target unit when the leakage voltage output from the leakage current shift monitor unit exceeds the reference voltage, a condition that indicates that the leakage current is about to approach catastrophic runaway levels.

Abstract: A method is provided for optimizing power consumption of a digital circuit which provides operational functionality based upon operating demands. The digital circuit is subject to a supply voltage level and a clock frequency. The method includes determining an acceptable delay value, from a plurality of predetermined acceptable delay values, for the digital circuit based upon current operating demands and the clock frequency. The supply voltage level and the clock frequency are applied to a delay monitor circuit. The delay experienced by the delay monitoring circuit is measured. The measured delay is compared with the determined acceptable delay value. Based on the outcome of the comparing step, the supply voltage level applied to the digital circuit is selectively adjusted. An arrangement for implementing the method is also provided.

Abstract: In a semiconductor integrated circuit device using a ZSCCMOS circuit, a combinational circuit includes a plurality of logic gate circuits, and receives an output of a data holding circuit. The data holding circuit can continue to hold data during cut-off of power supply, and when receiving a predetermined value as a control signal, outputs a predetermined fixed value. A logic gate circuit which outputs “L” when the output of the data holding circuit has the predetermined fixed value has power supply ends connected to a pseudo-power supply line VDDV and a low potential power supply line VSS. A logic gate circuit which outputs “H” when the output of the data holding circuit has the predetermined fixed value has power supply ends connected to a high potential power supply line VDD and a pseudo-power supply line VSSV.

Abstract: A system and method for controlling an IC in different operational modes involves automatically loading operational configurations of target circuitries in the IC for a determined operational mode into at least one register and operating the target circuitries in the IC according to the operational configurations that are automatically loaded into the at least one register.

Abstract: A voltage circuit and method charges a circuit node to a first predetermined voltage. The first predetermined voltage charged onto the circuit node is used for a first predetermined function during a first time period. A portion of charge from the circuit node is removed to circuitry coupled to the circuit node. The portion of the charge is reused during a second time period subsequent to the first time period. In one form a voltage generator has diode configurable transistors for passing current in only one direction depending upon whether the circuit node is being charged or discharged. In another form a switch couples the circuit node between a reference terminal and another circuit for charge reuse. Reuse of charge permits increased power savings.

Abstract: A semiconductor integrated circuit includes a core circuit, a power supply switch situated on a path providing a current to the core circuit and configured to control a state of current supply to the core circuit in response to a control signal applied to a control node, a clamp circuit configured to clamp a voltage of the control signal, and a switching circuit configured to control whether to enable or disable a clamp operation of the clamp circuit.

Abstract: Power control circuitry is provided for controlling connection of a power source having a source voltage level to a switched power rail to provide power to an associated circuit block. The power control circuitry comprises a switch block for selectively connecting the switched power rail to the power source, and a switch controller for controlling operation of the switch block. A ring oscillator circuit is powered from the switched power rail and produces an oscillating output signal, and analysis circuitry is then used to analyse change in frequency of the oscillating output signal produced by the ring oscillator circuit during a period of time when the switched power rail is not at the source voltage level. The switch controller is then arranged to control at least one aspect of the operation of the switch block in dependence on the analysis. This technique provides a simple and effective digital technique for observing voltage changes on the switched power rail.

Abstract: A test circuit that compares test results between two tests with different local supply voltages is provided. The output of each stage of the logic circuits is stored in a first register of each test circuit. Each test is performed with a critical test vector and a local supply voltage that decreases from test to test. The outputs of successive tests are compared in each test circuit. The tests are performed iteratively with successive reduction in the value of the local supply voltage until at least one stage of the logic circuits produces non-matching results between the first and second register. The voltage immediately before producing such non-matching results is the minimum operational voltage for the local voltage island.

Abstract: A system that causes a computing device to enter a hibernation mode. During operation, the system creates a hibernation image for the computing device by identifying processes that do not have visible user interface elements, and generating the hibernation image so that processes with visible user interface elements can be reanimated from the hibernation image first to get the computing device reanimated quickly, while the identified processes are reanimated later. Next, the system stores the hibernation image in non-volatile storage. The system then causes the computing device to enter the hibernation mode, wherein the active state of the computing device is preserved in non-volatile storage while power to volatile storage is turned off.

Abstract: Devices and methods are disclosed for logic gate devices to provide reduced leakage while improving performance. The device is configured for low leakage logic application where high threshold voltage devices are used to reduce leakage at the expense of reduced logic speed. Better performance is achieved than a high threshold voltage stack.

Abstract: A converter includes an analog to digital converter having a bias current input, a control input, and an analog input to provide a digital output as a function of the analog input. A bias module is coupled to the bias current input to provide bias current to the analog to digital converter. A controller is coupled to the bias module and to the control input of the analog to digital converter. The controller controls the analog to digital converter to sample an analog input and controls the bias module to provide an operating bias current during sampling of the analog input and an idle bias current when not sampling the analog input.

Abstract: A digital circuit implementing pulse width modulation controls power delivered in what one can model as a second order or higher order system. An exemplary control plant could embody a step-down switch mode power supply providing a precise sequence of voltages or currents to any of a variety of loads such as the core voltage of a semiconductor unique compared to its input/output ring voltage. An algorithm produces a specific sequence of pulses of varying width such that the voltage or current delivered to the load from the system plant closely resembles a critical damped step response. The specific pulse width modulation sequence controls a plant that provides a near critical damped step response in one embodiment without a feed-forward or feedback loop physically embodied in the control system thereby reducing the parts cost or control semiconductor production yield cost while enhancing noise immunity and long term reliability of the control system.

Abstract: Techniques in which an optimal set of clock gating elements is determined for a selected circuit design. Those clock gating elements are coupled to selected flip-flops, with the effect that those selected flip-flops will consume less dynamic power during operation of the logic circuit. The selected set of clock gating elements provides an optimal savings in overall power consumption after modification of that selected circuit design.

Abstract: A semiconductor integrated circuit device for fast and low power operations, comprising a plurality of circuit blocks of a chip, each of which has a plurality of states with different power consumption values. A power management circuit determines the state of each of the circuit blocks so as not to exceed a maximum power consumption value of the semiconductor integrated circuit device by considering the power consumption of each circuit block and by each state transition in each circuit block. The maximum power consumption value may be preset or adjustable after fabrication.

Abstract: A semiconductor device 2 has a plurality of elements. It also has an F-V table storing unit for low voltage threshold cells 31 for storing an F-V table TB11 of an oscillation frequency f1 relying on the plurality of elements and a power supply voltage EV to be supplied to the plurality of elements. It has a process sensor block 12 having at least one of the plurality of elements, for monitoring the oscillation frequency f1 relying on at least one element. It further has a selector 33 for setting the power supply voltage EV associated with the oscillation frequency f1, as the supply voltage to be supplied to the semiconductor device 2 by selecting according to the F-V table TB11. The F-V table TB11 is obtained by mutually relating the combinations of random number models ?n between an F-? table TB20 and an ?-V table TB30.

Abstract: A charge pump includes a first transistor, a second transistor, a first, a second and a third selectors. The first transistor includes a gate electrode, a first electrode, and a second electrode which serves as an output port of the charge pump. The second transistor includes a gate electrode, a first electrode and a second electrode, where the gate electrode of the first transistor is coupled to the gate electrode of the second transistor, and the gate electrode of the second transistor is coupled to the second electrode of the second transistor. The first selector is utilized for selectively connecting the first transistor to a first supply voltage. The second selector is utilized for selectively connecting the first transistor to a second supply voltage. The third selector is utilized for selectively connecting the second transistor to the second supply voltage.

Abstract: An electric circuit device operable under a power supply includes: a circuit; a first switch connected between the power supply and the circuit; a capacitor tending to produce a first leakage current; a second switch connected between the power supply and the capacitor, the second switch producing a second leakage current when it is cut off, the second leakage current being less than the first leakage current; and a switch controller for turning on the second switch while both the first switch and the second switch are turned off, and after a first time passes for turning on the first switch.