Abstract: In an apparatus for encrypting an information signal into an encryption-resultant signal, a first encryption key peculiar to the present apparatus is generated. Key information is read out from a replaceable recording medium. A decision is made as to whether or not the read-out key information has been generated by an apparatus different from the present apparatus. A second encryption key is generated in response to the read-out key information when it is decided that the read-out key information has been generated by an apparatus different from the present apparatus. One is selected from the first encryption key and the second encryption key as a final encryption key. An information signal is encrypted in response to the final encryption key.

Abstract: An apparatus includes logic to determine a discharge drop of a capacitor and to adjust an enablement charge level of the capacitor according to the discharge drop.

Abstract: Methods and circuitry for lowering the capacitance of interconnects, particularly Through Wafer Interconnects (TWIs), using signal level adjustment are disclosed. Embodiments of the invention seek to bias the midpoint voltage level of the signals on the TWIs towards inversion, where at high frequencies capacitance is at its minimum. In one embodiment, reduced swing signals are used for the data states transmitted across the TWIs, in which the reduced swing signals use a midpoint voltage level tending to bias the TWI capacitance towards inversion. In another embodiment, signals are AC coupled to the TWI where they are referenced to an explicit bias voltage directly connected to the TWI. This allows signals to propagate through the TWI while the TWI is biased towards inversion. In a third embodiment, the potential of the substrate is explicitly lowered with respect to the TWI potential.

Abstract: A constant current bias circuit and associated method is disclosed. The constant current bias circuit comprises an output stage for amplifying a radio frequency (RF) signal, wherein the output stage is operably coupled with a voltage. The constant current bias circuit further comprises a bias circuit operably coupled with the output stage for generating a substantially constant current bias to the output stage. The constant current bias circuit still further comprises a plurality of bias transistors operably coupled with the voltage and the output stage.

Abstract: Improved dispersion compensating circuits for optical transmission systems are disclosed. According to the improved method, there is provided a compensation circuit comprising a varactor diode network. The network is preferably inserted between a source of laser modulating signal and the laser. A low-pass filter or all pass filter constructs the network. The network preferably includes an inductor or inductors and a combined circuit, which includes varactors. The network preferably provides an amplitude dependent delay of the modulating signal applied to the laser or to the optical receiver as post dispersion correction circuitry. In a first embodiment, a fixed capacitor is in series with a varactor and connected to a DC bias through inductor. Additional embodiments, using multiple varactors in different circuit configurations, with particular advantages for various applications identified.

Abstract: A power noise immunity circuit includes a unidirectional device and a switch both connected between a power input terminal and a power output terminal, and a noise detector to control the switch. The power input terminal is for being connected to an external voltage source, and the power output terminal is for being connected to the circuit of an IC. The switch is normally closed and is opened by the noise detector if the noise detector detects power noise at the power input terminal. The power noise immunity circuit thus prevents the IC from power breakdown and provides a stable voltage thereto.

Abstract: An oscillation circuit includes a constant current source, a current mirror circuit configured to receive a constant input current from the constant current source and to output a current proportional to the constant input current, a first inverter configured to be driven with a quartz resonator to oscillate, an operational amplifier configured to supply a power to the first inverter with a voltage equal to an input voltage thereof and a second inverter having a power supply terminal connected to the current mirror circuit and to the operational amplifier and configure to generate the input voltage for the operational amplifier.

Abstract: A stable voltage generating circuit for a delay locked loop for generating a stable internal voltage for a delay locked loop and a semiconductor memory device including the same, and a method of generating a stable voltage for a delay locked loop is disclosed. The voltage generating circuit includes a first detector which compares a feedback voltage that represents the internal voltage for the delay locked loop with a reference voltage and outputs the comparison result as a first detection signal. A second detector detects the escape timing of a power down mode to provide a second detection signal having a configurable enable width interval after the escape timing of the power down mode. Finally, the voltage generating circuit includes a voltage driver which drives and outputs the internal voltage either the first detection signal or the second detection signal is enabled to maintain a stable internal voltage level.

Abstract: A voltage divider of a voltage regulator system is disclosed utilizing divided diffused resistors. In one embodiment, a feed-forward capacitor network is connected across the resistors and the voltage divider output. The feed-forward capacitor network allows the output to rise and fall quickly with a change in the voltage divider input. Accordingly, an improved frequency response should be obtained utilizing divided diffused resistors.

Abstract: Systems and methods for current management for digital logic devices are provided. In one embodiment, a method of current management for a digital logic circuit comprises drawing power to drive a digital logic integrated circuit; determining a priori information about an impending current need of the digital logic integrated circuit; and controlling a bypass current in parallel with the digital logic integrated circuit based on the a priori information, wherein the bypass current is controlled to reduce discontinuities in the current supplied by a power supply.

Abstract: A fuse circuit comprises at least one fuse circuit unit and a current blocking module. The fuse circuit unit comprises a voltage establishing module and a latch. The voltage establishing module is coupled to a first reference voltage source and includes a fuse that is capable of being selectively blown according to an initial setting signal. The fuse has a first terminal coupled to a node and a second terminal. The voltage establishing module establishes a voltage level on the node according to the blown-off status of the fuse. The latch is coupled to the voltage establishing module through the node for latching the voltage level of the node and generating the output signal. The current blocking module is coupled between a second reference voltage source and the second terminal of the fuse for blocking the current flowing through the fuse while initial setting.

Abstract: The present invention discloses a source driver and a method for restraining noise output by a source driver during power on/off of a power supply. The source driver includes a data bus, a plurality of channels, a multiplexer and a plurality of output pads. The channels are connected to the output pads via the multiplexer. Each channel has a latch unit. Data is transmitted on the data bus and stored in the latch units. The source driver is powered by a first supply voltage from the power supply. The method comprises determining whether the first supply voltage is insufficient, and if yes, performing the following steps. First, set the data transmitted on the data bus to be a predetermined value. Then, keep the latch units turned on, thereby the data is sent out from the latch units. Then, keep the multiplexer turned on for outputting a driving voltage based on the data via the output pads.

Abstract: A semiconductor integrated circuit is provided including a plurality of circuit blocks and adapted to cut off the supply of power source voltage to any one of the circuit blocks. The integrated circuit includes an interblock interface circuit provided on a signal path between an elected circuit block and a branch point at which the signal path branches into different branch paths so as to connect to other circuit blocks. The interblock interface circuit includes a signal gate for preventing signal transmission from the elected circuit block to the other circuit blocks, and includes a storage unit for storing a signal right before the power cut-off.

Abstract: A dual mode voltage supply circuit (50) includes an active mode voltage supply circuit (58) and a passive mode voltage supply circuit (60). The active mode voltage supply circuit (58) is selectively operative to supply a voltage (57) based on mode control information (22). The active mode voltage supply circuit (58) is operative to provide a first current capacity. The passive mode voltage supply circuit (60) is operatively coupled to the active mode voltage supply circuit (58). The passive mode voltage supply circuit (60) is operative to supply the voltage (57) when the active mode voltage supply circuit (58) is not supplying the voltage (57). The passive mode voltage supply circuit (60) is operative to provide a second current capacity that is less than the first current capacity.

Abstract: A semiconductor integrated circuit is provided including a plurality of circuit blocks and adapted to cut off the supply of power source voltage to any one of the circuit blocks. The integrated circuit includes an interblock interface circuit provided on a signal path from the elected circuit block to other circuit blocks, wherein a single output of the interblock interface circuit is branched out to other circuit blocks. The interblock interface circuit includes a signal gate for preventing signal transmission to other circuit blocks and includes a storage unit for storing a signal right before the power cut.

Abstract: A semiconductor integrated circuit is provided including a plurality of circuit blocks and adapted to cut off the supply of power source voltage to any one of the circuit blocks. The integrated circuit includes an interblock interface circuit provided on a signal path from the elected circuit block to other circuit blocks, wherein a single output of the interblock interface circuit is branched out to other circuit blocks. The interblock interface circuit includes a signal gate for preventing signal transmission to other circuit blocks and includes a storage unit for storing a signal right before the power cut.

Abstract: Systems and methods for Current Management of Digital Logic Devices is provided. In one embodiment, a method of current management for a digital logic circuit is provided. The method comprises drawing power to drive a digital logic integrated circuit; performing one or more switching operations with the digital logic integrated circuit; learning at least one bypass current setpoint based on a voltage powering the digital logic integrated circuit while performing the one or more switching operations.

Abstract: In an encryption storage apparatus (data storage apparatus) (1), when entered an allocation request signal (a1), a key management section (7) outputs a generation request signal (b) to a random number generation section (3). The random number generation section (3) generates a pseudorandom number as an encryption key (c) at the entering timing of the generation request signal (b), and the key management section (7) causes a volatile key storage section (4) to store the encryption key (c) and returns a corresponding key number (a2) to a user side. When the user enters an encryption instructing signal (a3) and the key number (a2) to the key management section (7), the key management section (7) reads out the corresponding encryption key (c), and an encryption section (5) converts entered data (d1) into encrypted data (d2) and stores the encrypted data (d2) in a nonvolatile storage section (2).

Abstract: There is provided a circuit for preventing latch-up in a DC-DC. The circuit for preventing a latch-up phenomenon in a DC-DC converter, the DC-DC converter having a first and a second DC-DC converters coupled with each other in one chip for receiving an input voltage to generate a positive voltage and a negative voltage, respectively, in which a parasitic block with a PNP transistor and an NPN transistor causing a latch-up phenomenon is embedded, the circuit includes a first pathway for controlling an input current flowing to the first DC-DC converter from an input terminal receiving the input voltage in order that the PNP transistor is turned on and the NPN transistor is not turned on; and a second pathway for supplying the input current to the first DC-DC converter intactly at a timing that both the positive and negative voltages reach target voltages.

Abstract: An integrated circuit core power supply event monitor is disclosed. The integrated circuit core power supply event monitor includes a plurality of sub-circuit power supply event monitors. Each sub-circuit power supply event monitor includes a first input for receiving a first voltage, a second input for receiving a second voltage, a comparator for comparing the first voltage to the second voltage in order to detect an occurrence of a voltage deviation of the first voltage from a predetermined magnitude and an output for outputting an indicator of the occurrence of a voltage deviation of the first voltage from a predetermined magnitude if a voltage deviation of the first voltage from a predetermined magnitude occurs. A register for receiving the indicator of the occurrence of the voltage deviation of the first voltage from a predetermined magnitude and for registering the indicator of the occurrence of the voltage deviation from a predetermined magnitude.

Abstract: A method is described. A total number of traps to be filled in a detector of an imaging system is estimated based on a measured signal sensed by the detector. The measured signal is adjusted based on the estimated total number of traps and a current trap state of the detector. The trap state of the detector is subsequently updated.

Abstract: A reverse polarity protected system comprises a voltage source that includes positive and negative terminals. A polarity-sensitive device has a first terminal that communicates with the positive terminal of the voltage source, and that includes a second terminal. A low-resistance switch communicates with the first and second terminals of the voltage source, and communicates with the second terminal of the polarity-sensitive device. The low-resistance switch assumes a conducting state between the second terminal of the polarity-sensitive device and the negative terminal of the voltage source when a first voltage at the positive terminal of the voltage source minus a second voltage at the negative terminal of the voltage source is greater than a threshold voltage. Otherwise, the low-resistance switch assumes a non-conducting state.

Abstract: A reset detection circuit for a logic circuit and a RAM includes a first determining circuit, a second determining circuit and a reset signal generating circuit. The first determining circuit operates with a first voltage and determines whether a second voltage is equal to or higher than a reset voltage for the logic circuit. The second determining circuit operates with the first voltage and determines whether the first voltage is equal to or higher than a minimum operating voltage as a guarantee voltage for an operation of the first determining circuit. The reset signal generating circuit outputs a reset signal for resetting the logic circuit and the RAM, when the first voltage is lower than the minimum operating voltage and the second voltage is lower than the reset voltage.

Abstract: A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the external voltages that those circuits can handle. By placing input and output devices, in series, external voltages can be divided between the devices thereby reducing junction voltages seen by internal devices. By using external voltages as part of a biasing scheme for integrated circuit devices, stress created by the differential between external voltages and internal voltages can be minimized. Additionally device wells can be biased so that they are at a potential that is dependant on the external voltages seen by the low voltage integrated circuit.

Abstract: A bandgap reference circuit is proposed. To remove parasitic effects, this includes the combination of a first circuit section (1), which generates a temperature-proportional voltage, and a second circuit section (2), which generates an inversely temperature-proportional voltage. The bandgap reference circuit generates a bandgap reference voltage (Ubg) as the sum of the temperature-proportional voltage of the first circuit section (1) and the inversely temperature-proportional voltage of the second circuit section (2). To remove the parasitic effects, both circuit sections (1, 2) include bipolar transistor circuits with multiple bipolar transistors (Q1-Q4; Q5-Q8), so that both the temperature-proportional voltage and the inversely temperature-proportional voltage are generated in the form of a sum and difference formation of multiple base-emitter voltages of the appropriate bipolar transistors.

Abstract: An oscillation circuit includes a constant current source, a current mirror circuit configured to receive a constant input current from the constant current source and to output a current proportional to the constant input current, a first inverter configured to be driven with a quartz resonator to oscillate, an operational amplifier configured to supply power to the first inverter with a voltage equal to an input voltage of the operational amplifier and a second inverter having a power supply terminal connected to the current mirror circuit and to the operational amplifier and configure to generate the input voltage for the operational amplifier.

Abstract: A bias-voltage supply circuit of a radio-frequency amplification circuit has the constant-voltage power supply generating a constant voltage higher than the bias voltage, a rectifier transistor and a constant-current power supply supplying a constant current to the rectifier transistor. The rectifier transistor is connected between a supply point of a bias voltage connected to an input terminal of the radio-frequency amplification transistor via an element for bias supply and a power supply voltage supply line, wherein a control terminal is kept by the constant voltage that the constant-voltage power supply generates. Since descent of the electric potential of the input terminal of a radio-frequency signal does not arise because of circuit composition, the radio-frequency amplification circuit has a good saturation characteristic.

Abstract: A high voltage switching circuit of a NAND type flash memory device that includes a clock level shifter for increasing an amplitude of a clock signal, a pass voltage generator for outputting a pass voltage by pumping a power source voltage in response to a clock signal with an increased amplitude, and a high voltage pass transistor for transferring a high voltage according to the pass voltage.

Abstract: A selection circuit having a comparator with comparator inputs connected to first and second voltage inputs), respectively, and a comparator output connected to a control input of a first controllable switch and an inverter. The selection circuit also has a second controllable switch having a second control input connected to the inverter. The first voltage input is connectable to a selection circuit output by the first controllable switch and the second voltage input is connectable to the selection circuit output by the second controllable switch. The inverter has a power supply connector connected to the first voltage input and the comparator has a power supply connector connected to the second voltage input.

Abstract: A bias generator that automatically adjusts its slew rate is disclosed to generate an output bias current and adjust the output bias current according to the frequency of a clock signal. The slew rate of the amplifier is thus controlled to save power. It includes: a current mirror for receiving a feedback voltage and generating an output bias current; a storage capacitor with a first end and a second end and the latter being coupled to the ground; a charging switch coupled between the output of the current mirror and the first end of the storage capacitor; a discharging switch coupled between the first end of the storage capacitor and the ground; a comparator whose input is coupled to the first end of the storage capacitor and a reference voltage; and a feedback unit coupled to the output of the comparator for outputting a feedback voltage to the current mirror.

Abstract: A structure and method for damping LC (inductance-capacitance) ringing in integrated circuit (IC) power distribution systems. The structure comprises a resistance electrically connected in parallel with a plurality of electrical switches. The resistance and electrical switches are electrically connected in series with the package and on-chip power distribution circuit. When on-chip switching activity creates a sudden and appreciable change in IC power demand the electrical switches are opened to temporarily increase the resistance in series with the power supply. This serves to dampen the power-distribution LC ringing. Later, the electrical switches are closed to shunt the series resistance and reduce the level of steady-state voltage drop in the power structure.

Abstract: A method of ground level compensation includes measuring a voltage of at least one signal with respect to a primary ground potential and measuring, with respect to the primary ground potential, a voltage level associated with a secondary ground potential. A difference between the voltage level associated with the secondary ground potential and an expected value is calculated. The measured voltage of the at least one signal is adjusted by an amount corresponding to the calculated difference.

Abstract: A compensation circuit is disclosed for compensating bias levels of an operational circuit in response to variations in a supply voltage. The compensation mechanism identifies variations in the supply voltage by comparing the voltage of a selected node of the operation circuit with a relatively constant or fixed reference voltage. Based on the results of the comparison, the compensation mechanism adjusts selected bias levels in the operational circuit, preferably using current stealing circuitry, so that the functionality and performance of the operational circuit can be substantially maintained. A biasing circuit for biasing one or more differential pairs is also disclosed.

Abstract: A system and method are described for receiving differential currents in a current mode circuit. When conditions occur where the receiver inputs are floating, undriven, shorted together, or one or both shorted to ground, the output of the system remains stable. Diode connected MOS transistors receive the unequal currents, and current mirrors amplify the received currents. Those amplified mirrored currents are differentially amplified and converted into voltage signals suitable of typical computer and logic systems. The current mode differential nature of the invention provides high common mode current and voltage noise immunity. A threshold for the unequal currents helps provide high differential current and voltage noise immunity.

Abstract: The invention relates to a circuit arrangement which includes a subvoltage generating unit and a voltage multiplier for generating at least one voltage Vmult, it being arranged to control the voltage multiplier by switching the voltage multiplier to a direct mode during a start time. The invention also relates to an arrangement for driving a display device, to a display device which includes such an arrangement, to an electronic apparatus which is provided with a display device for the display of image data which includes an arrangement for driving the display unit, and to a method of starting a circuit arrangement 15 which includes a subvoltage generating unit 40, a voltage multiplier 20 and a start control unit 30.

Abstract: A semiconductor integrated circuit is provided including a plurality of circuit blocks and adapted to cut off the supply of power source voltage to any one of the circuit blocks. The integrated circuit includes an interblock interface circuit provided on a signal path from the elected circuit block to other circuit blocks, wherein a single output of the interblock interface circuit is branched out to other circuit blocks. The interblock interface circuit includes a signal gate for preventing signal transmission to other circuit blocks and includes a storage unit for storing a signal right before the power cut.

Abstract: A new method to control a switchable decoupling capacitor in an integrated circuit device is achieved. The method comprises providing an integrated circuit device comprising a switchable decoupling capacitor. The switchable decoupling capacitor is initialized by a method comprising connecting the switchable decoupling capacitor between a power supply and ground. The state of the switchable decoupling capacitor is stored as enabled. The switchable decoupling capacitor is then controlled during operation of the integrated circuit device by a method comprising monitoring a voltage on a terminal of the switchable decoupling capacitor. The switchable decoupling capacitor is disconnected if the voltage exceeds a threshold level. The state of the switchable decoupling capacitor is stored as disabled if the switchable decoupling capacitor is disconnected.

Abstract: A system for improving the power efficiency of an electronic device includes a threshold voltage selector and a supply voltage selector. The threshold voltage selector selects a value of a threshold voltage for operation of the device in response to a present operating condition of the device. The supply voltage selector selects a value of a supply voltage to be applied to the device in response to the present operating condition of the device. The value of the threshold voltage and the value of the supply voltage control a power consumption of the device.

Abstract: A sensing circuit. The circuit includes an integrator to sense charge release from a passive electronic device and a comparator to interpret the charge release as one of at least two data states. The circuit also includes a compensation module to generate a compensation signal as needed and a direct-timing module to time a period of integrator sensing based upon a predefined time period.

Abstract: A current mirror and method for operating such a mirror include nonlinearly converting an input current (Iin+=I0 and, respectively, Iin−=I0) into a voltage in a current sink, the voltage being used for driving a current source (Iout+=−n·I0 and, respectively, Iout−=n·I0) with substantially the same transfer characteristic. According to the invention, the current mirror is configured to contain a further voltage-controlled current source that supplies an auxiliary current a·Iout=−a·n·I0.

Abstract: A sensing circuit. The circuit includes an integrator to sense charge release from a passive electronic device and a comparator to interpret the charge release as one of at least two data states. The circuit also includes a compensation module to generate a compensation signal as needed and a direct-timing module to time a period of integrator sensing based upon a predefined time period.

Abstract: A circuit for generating internal power voltage comprising: a comparison unit for comparing reference voltage and internal voltage; a buffer unit, its input terminal comprising CMOS inverters, for buffering an output signal of the comparison unit; a buffer control unit for controlling current flowing through the CMOS inverters of the buffer unit less than a predetermined amount in regular operations and for controlling current flowing through the CMOS inverters of the buffer unit more than a predetermined amount in active operation; a first current supply unit for supplying current according to an output signal of the buffer unit; and a load unit for generating internal voltage by current supply from the first current supply unit.

Abstract: A sensing circuit. The circuit includes an integrator to sense charge release from a passive electronic device and a comparator to interpret the charge release as one of at least two data states. The circuit also includes a compensation module to generate a compensation signal as needed and a direct-timing module to time a period of integrator sensing based upon a predefined time period.

Abstract: Integrable current supply circuit An integrable current supply circuit for feeding a supply current to a signal line (12) having a current source (14) for producing a source current which is emitted via a connection line (18) to an input of a current amplifier (20), which amplifies the source current and feeds the amplified source current as a supply current via a current output (2) of the current supply line to the signal line (12), with the current source (14) and the current amplifier (20) having parasitic capacitances, distinguished by a compensation capacitor (28) which is connected to the current output (2) and whose capacitance corresponds to the parasitic capacitances, and a current mirror circuit (31) which emits the charging current that flows through the compensation capacitor (28) in order to compensate for the charging currents flowing through the parasitic capacitances in mirrored form onto the connection line (18) connected between the current source (14) and the current amplifier (20).

Abstract: A power voltage driver circuit includes: a constant voltage generating unit for generating a first constant voltage and a second constant voltage; a clock input buffer unit using an internal step-down voltage as a power source; a control unit for receiving an operation control signal indicating the low power operation mode; a voltage comparing unit controlled in response to the output signal from the control unit, for stopping the operation in the low power operation mode, and receiving the first and second constant voltages in the other operation modes, and generating a signal by comparing and amplifying the first and second constant voltages with a reference voltage; and a driver unit controlled in response to the output signal from the control unit.

Abstract: A charge pump circuit comprising: a first reverse current prevention circuit connected between an external power supply and a first internal node; a first output node, connected to the first internal node, for outputting a first output potential; a second reverse current prevention circuit connected between a second power supply node receiving ground potential and a second internal node; and power supply generation circuit, connected between the first internal node and second internal node, for enhancing the potential of the second internal node as compared to that of the first internal node, wherein the power supply generation circuit is formed on or within a semiconductor substrate, and includes a diode element provided so as to flow a current from the first internal node to the second internal node, and a capacitor having one electrode connected to the first and second nodes, and the other electrode provided with a clock signal, thereby enabling higher outputs on both positive and negative voltages.

Abstract: An evaluation circuit 16 repeats processing in which an output VD thereof is reset, there is obtained repeatedly given times a difference between sampled output voltages Vo of a replica circuit 11R when respective times t1 and t2 have elapsed after a voltage Vi is step-inputted to the replica circuit 11R, and the differences are successively summed. A comparator circuit 20 compares a difference cumulation voltage VD with a reference voltage VS. A bias adjustment circuit 15 steps up the bias currents of the replica circuit 11R and an adjusted circuit 11 at every this given times if VD>VS, and ceases the adjustment if VD<VS.

Abstract: The object of this invention is to minimize a simultaneous switching noise of the mutual inductor on PCB and a noise generated by large buffers' simultaneous switching. An instant large current in the power line is half-divided flowing through two different but closely coupled layers in opposite directions. This configuration is effective to minimize the simultaneous switching noise. This mutual inductance between two power layers enables us to significantly minimize the switching noise.

Abstract: A system is provided for supplying current to a dynamic load subject to transient current requirements. A sense unit coupled to the dynamic load is configured to sense the rate of change of supply current required by the dynamic load during a transient event. A current source coupled to the sense unit is configured to supply a current pulse to the dynamic load in response to the sense unit determining that the rate of change of supply current (di/dt) exceeds a predetermined threshold. The current pulse preferably has a shape characterized by a first region and a second region subsequent to the second region, wherein the first region includes a first boost current which exceeds the transient current requirement, and wherein the second region includes a second boost current which is less than the transient current requirement. More generally, a wideband transient suppression system is provided for controlling a wide spectrum of transients.

Abstract: A single-ended circuit, such as an LNA (300), in accordance with the present invention includes an input power matching circuit (310) and a bias circuit (305) connected to an output transistor (Qin) which provides the amplification. A degeneration inductance (Le) and load impedance (Lo) couple to the emitter and collector of the output transistor (Qin), respectively. The bias circuit (305) is configured to eliminate base shot-noise of the mirror transistor (Q1) which generates the amplification. The bias circuit (305) in accordance with the present invention also eliminates the noise of the bias resistor (Rx1) that is included within the bias circuit (305). Specifically, the bias circuit (305) includes a current reference source (Iref) and an emitter follower circuit (315) connected to a current mirror circuit (Q1, Q2, Rx2) that connects to a bias resistor (Rx1). This bias circuit (305) can be implemented in a wide-class of single-ended circuits.