Abstract: A circuit for biasing epitaxial wells of a semiconductor integrated circuit includes a first transistor and a second transistor driven in phase opposition to the first; when the supply voltage is positive, the first transistor, being connected between the power supply and the epitaxial well, is conducting whereas the second transistor is cut off. When, on the contrary, the supply voltage is negative, the second transistor, being connected between the epitaxial well and the ground reference GND, goes into saturation, thereby holding the epitaxial well biased to ground since, at that time, it is the highest potential present on the device. In this way, it becomes possible to always ensure reverse biasing of the parasitic diodes which form at the junctions between the epitaxial wells and the adjacent regions thereto.

Abstract: According to the present invention, there is provided an integrated circuit useful in an electronic encoding device having a voltage source, a user interface and a transmitter. In one embodiment the integrated circuit includes a wake-up circuit which generates a signal responsive to an input received from the user interface; power switching logic which provides power from the voltage source to a non-regulated power bus and a voltage regulating circuit, the power switching logic being responsive to the signal from the wake-up circuit; a regulated power bus in communication with the voltage regulating circuit; non-volatile memory in communication with the regulated power bus; encoder logic in communication with the regulated power bus, the encoder logic having output logic which provides a signal to the transmitter.

Abstract: A protection circuit for a CMOS integrated circuit which is biased with a first voltage and a second voltage includes a voltage divider, a voltage comparator, and a switch. The full level of the first voltage is higher than that of the second voltage. The voltage divider divides the first voltage to be compared with the second voltage in the voltage comparator. The switch is controlled by the voltage comparator. The switch isolates the CMOS integrated circuit from the first voltage when the first voltage is lower than the second voltage. Therefore, no forward bias current path exists in the CMOS integrated circuit even though the voltage levels of the first and second voltages reach their full levels at different times.

Abstract: The present invention is directed toward a circuit for receiving an input current and for producing an output voltage proportional to the input current. The circuit includes a first transistor which receives the input current, and a second transistor connected to the first transistor, wherein the first and second transistors comprise a current mirror topology. A third transistor is connected in series with the first transistor, and an operational amplifier has an output which is connected to the base of the third transistor. The third transistor has a collector coupled to a base junction of the current mirror. The operational amplifier has a positive input terminal coupled to a collector of the second transistor through a first resistor, and a negative input terminal coupled to an emitter of the third transistor through a second resistor, the first and second resistors having substantially similar impedance values.

Abstract: A method and an apparatus for generating an output voltage for an integrated circuit having multiple power supplies. A comparator circuit is coupled to receive power supply lines from the power bus of an integrated circuit. The power supply lines received from the power bus have different voltages which may vary depending on the particular application. The comparator compares the voltage potentials present on the power supply lines and determines which power supply line carries a voltage having the highest potential. The comparator then generates a corresponding select signal wherein the value of the select signal indicates which particular power supply line has the highest voltage potential. A multiplexor is coupled to receive the select signal as well as the power supply lines from the power bus.

Abstract: An integrated circuit providing two output functions from a single output controlled by an input with a single switch responsive to an input level.

Abstract: A variable load current supply unit supplies a current to be consumed by a constant voltage output unit to a power source terminal thereof, and supplies a current to be consumed by a load circuit thereto through a reference voltage output terminal. The constant voltage output unit maintains a potential of the power source terminal thereof, i.e., a potential of the reference voltage output terminal, at a fixed potential. A base potential control unit negatively feeds back changes in the potential on the reference voltage output terminal to a base of an emitter follower transistor in the variable load current supply unit. In this way, when the current consumed by the load current is reduced and the potential on the reference voltage output terminal thereby slightly increases the current supplied by the variable load current supply unit decreases.

Abstract: A semiconductor chip incorporating a current generating circuit that will both power-down selected circuitry during inactive or standby periods and yet maintain a bias current to other parts of the chip. More specifically, the current generating circuit has output lines for providing output currents that mirror the current source during chip power-on operation periods. During chip power-down operation periods, the current generating circuit uses a current bias generator to supply current only to circuits needing to be operational during a partial chip operational mode.

Abstract: A substrate clamp for non-isolated integrated circuits is disclosed. The substrate clamp comprises a circuit that controls the voltage on a substrate so that the substrate is connected to a specific node if the parasitic PN diodes at all the circuit nodes are not forward biased. If a specific node is then forced with an applied voltage to forward bias, the substrate is disconnected from its original node and maintains itself at a forward biased diode voltage drop away from the powered node. Various embodiments are disclosed. In one embodiment of the invention, a set of bipolar transistors which utilize the substrate as a common base, is implemented. The emitters of these transistors are connected to a set of nodes which may be driven to voltages outside the range between that provided by the power supply and ground, or any other pair of applied voltages. The collectors of these bipolar transistors are connected together.

Abstract: An LSI device can provide a desired constant value of a step-down voltage even if there are variations due to the production processes and a stable characteristic of internal circuits is obtained. The LSI device such as a DRAM includes a first input terminal of the high-voltage-side external supply voltage, a constant current source and a second input terminal of the low-voltage-side supply voltage. Further, the device includes a circuit which makes a voltage between two terminals variable due to the disconnection of each fuse. A step-down circuit is formed by the constant current source and the load circuit and provides a step-down voltage V.sub.B for stepping down the external supply voltage V.sub.CC.

Abstract: A method and circuit for preventing forward bias of a collector-substrate diode in an integrated circuit with a bipolar transistor where a load driven by the transistor may be offset from a reference voltage, such as circuit ground, by a varying voltage offset. The difference between the bipolar transistor collector voltage and the reference voltage is sensed, and the bipolar transistor base current is varied responsive to the sensed difference so that the base current is zero when the collector voltage is equal to the reference voltage, whereby the collector current will be less than .beta. times the base current when the emitter voltage is less than the reference voltage and the diode will not become forward biased.

Abstract: An integrated circuit configuration for generating a reference current by bipolar technology includes a transistor of one conduction type having a control terminal being acted upon by a reference voltage and having a load path. An externally connectable resistor is to be connected between the load path of the transistor and a reference potential. A current mirror configuration has an input side connected between the load path of the transistor and a supply voltage source and has an output for picking up a reference current.

Abstract: A method and an apparatus for the detection of the current distribution in at least one conductor (W1, W2) of an electric machine are specified, which indirectly permit, in a simple manner, the metrological determination of said distribution. The conductors or Roebel bars (W1, W2) are arranged in a slot (4) of a stator laminate stack (3) of the electric machine and each has a plurality of mutually electrically insulated and transposed conductor elements (W1nl, W1nr; W2nl, W2nr). A probe holder (6) which can be displaced radially with regard to the electric machine and contains, in recesses, 2 magnetic field probes (M1, M2) with a predeterminable center-to-center distance (d) is provided, adjacent to these conductors (W1, W2) in a probe channel (17) within the slot (4). The magnetic transverse field within the slot (4) is measured using said probes.

Abstract: The SHF output power and channel frequency switching apparatus having an SHF power amplifier for amplifying an SHF signal and supplying the amplified SHF output power signal to a transmitting antenna, an amplification degree control circuit for controlling the amplification degree of the amplifier, an output power change-over switch for switching a plurality of levels of the SHF output power, a channel frequency change-over switch for switching channel frequencies of the output power signal, a memory having stored therein a table of control signals which are selected to have proper values for the respective positions of each of the output power change-over switch and the channel frequency change-over switch in order that a necessary output power level can be produced each time the channel frequency change-over switch is operated to switch, a control signal supply unit for reading from the table the control signals corresponding to the output power and channel frequency specified by the SHF output power change

Abstract: A system for controlling the application of power by a power supply to a load. The inventive system includes a first circuit for drawing power from the power supply and a second circuit for controlling the amount of power drawn by the first circuit from the power supply. The amount of power drawn from the power supply is gradually increased prior to the application of power to the load and gradually decreased after removal of power from the load. In the illustrative embodiment, the first circuit is a digitally controlled resistance and the second circuit is a digital counter which supplies a control word for the digitally controlled resistance. A high order bit from the counter enables the gating of clock pulses to the load circuit. As a result, activation of the load circuit is delayed while the invention gradually varies the amount of power drawn from the power supply to a desired threshold level.

Abstract: A multi-phase charge pump continuously pumps to establish a DC voltage outside the range of supply and reference voltages. The multi-phase charge pump in one embodiment includes four stages operating in a ring with a four-phase clock. Each stage includes a three-mode charge pump that generates and provides reset and control signals to other stages. Each stage includes a pass transistor having a gate driven in excess of the DC voltage for efficient transfer of charge. The gate drive signal from a first stage is coupled to a next stage in the ring where it is used to generate the next gate drive signal. Each gate drive signal corresponds to one waveform having a phase skewed in time so that each stage in the ring is operating in a different mode. In a method of use, a first stepped voltage is developed on a first capacitor and selectively coupled to a second capacitor to develop a second stepped voltage of greater absolute value.

Abstract: The semiconductor device comprises: an internal supply voltage deboosting circuit for inputting an external supply voltage, deboosting the inputted external supply voltage, and outputting a deboosted voltage as an internal supply voltage; a first control circuit for deactivating the internal supply voltage deboosting circuit when the external supply voltage is lower than a predetermined value; and a second control circuit for outputting the external supply voltage as the internal supply voltage when the external supply voltage is lower than the predetermined value. When the external supply voltage is lower than a predetermined value, since the internal supply voltage deboosting circuit is deactivated by the first control circuit, the current consumption can be reduced. Further, since the external supply voltage is outputted as the internal supply voltage by the second control circuit, the deboosting operation is not required.

Abstract: In order to reduce noise in a controlling circuit including digital circuitry and analog circuitry constructed together on a single CMOS integrated circuit, a regulator is constructed as part of the integrated circuit. A power supply is directly connected to the digital circuitry, and a voltage output of the regulator is supplied to the analog circuitry. The output state of the regulator may be controlled by a switch. Degradation of the performance characteristics of the analog circuitry while the digital circuitry is being operated can be prevented by electrically isolating the power supply to the digital circuitry from the power supply to the analog circuitry. Since the regulator is built into the integrated circuit, the number of externally provided components is thereby reduced, further contributing to the downsizing of an electronic device such as a camera. Furthermore, even when the power supply of the digital circuitry fluctuates greatly, the effects on the analog circuitry are minimized.

Abstract: A power-up circuit with hysteretic characteristics for regulating the activation of one or more output buffers of an extended logic circuit. The hysteresis of the power-up circuit of the invention permits turn on of a switching transistor of the circuit at one threshold voltage level and maintains the active state of that switching transistor until a second lower threshold voltage level. The hysteresis is achieved by providing two separate and electrically isolated control paths that are connected to the control node of the switching transistor. The first control path includes a plurality of diode devices designed to regulate the power supply level required to turn on the switching transistor. The second control path also includes diode devices but in lesser numbers so that, once the switching transistor is turned on by the first control path, it remains on in spite of fluctuations at the power supply rail.

Abstract: A circuit and method for sensing and limiting current. An output driving transistor (M1) is coupled between a circuit output terminal and a power supply terminal. A replicator circuit is formed in a cross-coupled quad configuration from bipolar transistors (Q11, Q12, Q13 and Q14) and is coupled to a second transistor (M2) which generals a voltage proportional to the current flowing in the output driving transistor (M1). The current sensing circuit generates an output current which is proportional to the current flowing in the output driving transistor multiplied by a ratio of the sizes of the second transistor and the output driving transistor. In a current limiting configuration, the output of the cross-coupled quad is used to reset a flip-flop (FF1) that drives the gate terminal of the output transistor (M1), thus shutting down the output transistor before it is damaged due to excess current. The circuitry of the invention may be applied to a high side driver or a low side driver output circuit.

Abstract: A programmable current mirror circuit suitable for incorporation into circuit designs and programmably tailored to produce a ratio of current output over current input based upon the status of a plurality of binary weighted switches. The resulting circuit is readily tailored so as to be insensitive to the "on" characteristics of the switches. Alternatively, the switches may comprise transistors controlled by accompanying circuitry operable to produce an equivalent switching function. An input current divider circuit network formed from an array of current mirrors fractionally divides an input current into a plurality of equivalent currents. A binary weighting circuit receives such fractional input currents, and applies a binary weight to each of same. A voltage to current converter receives the binary weighted voltage and converts the voltage to a weighted output current proportional to the input current directly in relation to the binary weighting applied via the binary weighting circuit.

Abstract: A semiconductor device includes a semiconductor switch connected between a power supply terminal and a signal input terminal, and a latch circuit for controlling the ON/OFF of the semiconductor switch, wherein the content of the latch circuit is reset only by a first reset signal and is not reset by a second reset signal for resetting a circuit other than the latch circuit.

Abstract: A method of including power control features to analog integrated circuits does not require the addition of separate power control input signal pin(s). One or more existing externally applied reference signals are sensed to determine if the signals are within specified operational limits. When the reference signals are outside of the operational limits the internal circuit blocks are switched off to their non-power dissipating state. When the reference signals are within the operational limits the internal circuit blocks are switched on to their normal operating state. This switching can be accomplished in various ways, including but not limited to a single switch in a series with the power supply or many distributed switches in each circuit block or stage.

Abstract: A regulated power supply can be derived from a battery supply input and a regulator, but in order to conserve battery power, alternative power supplies can be provided each with a switch responsive to the regulator to connect that alternative power supply to the output when it rises to the level of the battery supply.

Abstract: In a switching circuit, a first input terminal and a second input terminal are connected to an output terminal by switching transistors which are selectively activated to supply the desired input signal to the output terminal. In order to output selectively, a voltage detector detects a level of a first input voltage at the first input terminal so that either the first switching transistor or the second switching transistor turns on. The voltage at the output terminal is controlled by a voltage controlling circuit in accordance with the stability of the output signal. The voltage controlling circuit does this by controlling the conducting state of the first switching transistor so that a stable output voltage can be obtained. Since the voltage controlling circuit drives the gate of the first switching transistor, it may be a small device operable with low consuming current, thereby the chip size can be reduced.

Abstract: A BiCMOS power-up circuit for delaying the operation of an extended circuit until the voltage available to the high-potential power rail of the extended circuit is sufficiently high that all elements of the extended circuit will be powered at a high enough voltage to function correctly. The power-up circuit of the present invention has its most direct application to three-state output buffers connected to a common bus, and in this context this circuit can maintain the output buffers in their high-Z, inactive state until the voltage available from the circuit-energizing power-supply has risen high enough that all of the stages of the buffers will operate correctly, and in particular will not be current-sourcing and current-sinking simultaneously.

Abstract: A clamp circuit (50) for protecting a MOSFET (52) from destructive voltages includes a clamping element (56), a Zener diode (64), two current mirrors (66 and 62), a current switch (58), a reference current source (68), and a voltage detector (72). When a drain voltage of the MOSFET (52) rises above a clamping voltage of the clamp circuit (50), a clamping current exceeding a current in the current switch (58) flows through the clamping element (56) and activates the MOSFET (52). During the activation, the two current mirrors (66 and 62) generate an output current exceeding a reference current in the reference current source (68) and raise a voltage at an input terminal of the voltage detector (72). The voltage detector (72) generates a signal indicating the activation of the clamp circuit (50), thereby indicating that the clamp circuit (50) and its inductive load (74) are intact.

Abstract: In a semiconductor integrated circuit device including a step-down circuit for stepping down an external power supply voltage to obtain an internal power supply voltage, the external power supply voltage can be applied to an internal signal processing circuit using a conventional terminal.

Abstract: A device that provides a control system which is capable of positively preventing a semiconductor from suffering from latch up. In order to prevent this latch up, a control circuit controls the semiconductor through a power source switch. The control circuit is capable of supplying a constant voltage to a power source terminal of the semiconductor when it is electrically connected to the power source circuit by turning on the power source switch, and thereafter supplying a control signal to a control terminal of the semiconductor. The control circuit is capable of stopping the output of the control signal to the control terminal and then stopping the supply of voltage to the power source terminal when disconnected from the power source circuit by turning off the power source.

Abstract: A supply voltage detect circuit is described which generates a control signal indicating the status of VCC to be at 5.0 or 3.3 volts. This control signal is used to generate analog reference signals used by A/D and/or D/A circuitry in an audio processing integrated circuit and by other circuitry to control clock frequencies or current drive.

Abstract: A communication line driver for a communication interface includes on one chip, a trimming circuit for adjusting a reference voltage generated by a reference voltage generating circuit, a driving device for transmitting a signal to a communication line; a buffer for applying a constant voltage to the driving device by a constant voltage control based on an output of the trimming circuit, and a bias circuit for deciding an internal operating current of the buffer on the basis of the output of the trimming circuit. The buffer further includes an MOS transistor which operates as a current limiter and functions to limit the current in case of an overload. Thus, a resistor for the current control is unnecessary. An electric power consumption can be reduced by the current limitation at the time of overload.

Abstract: A voltage generating circuit for providing a prescribed voltage, such as 1/2V.sub.DD of the power source voltage V.sub.DD, wherein the capacity of the current and the response time of the voltage generating circuit is significantly improved. When the output voltage V.sub.OUT of the voltage generating circuit drops suddenly from a reference value 1/2V.sub.DD and goes below the lower limit of an allowable voltage level VM-, an n-type MOS transistor MN5A of an output voltage detecting circuit 14 turns on. The potential of the gate terminal for a p-type MOS transistor MP6A in a digital output circuit 16 is pulled to the level of the output voltage V.sub.OUT via the transistor MN5A that was turned on, and said p-type MOS transistor MP6A is turned on in the saturated area more or less perfectly.

Abstract: An interface circuit is provided for connecting to a multi-mode signal bus. The signal bus (e.g., a PCI local bus) can operate in either a first or second signaling mode. The first signaling mode is one in which discrete logic levels (e.g., binary "0" and "1") are represented by a first set of voltage levels (e.g., 0V-5V). The second signaling mode is one in which discrete logic levels are represented by a different, second set of voltage levels (e.g., 0V-3.3V). The interface circuit includes an intermediate level generator circuit for generating, from the first voltage level (5V), an intermediate voltage level (V4) between the possible voltage levels of the first and second signaling modes (V5 and V3). A comparator compares the power level of the signal bus against the intermediate voltage level (V4) and determines which signaling mode the signal bus is operating in. Configurable I/O cells of the interface circuit are then automatically configured to operate in the corresponding signaling mode (V5 or V3).

Abstract: A circuit for rapidly charging a capacitor for a transition between operating states is provided. A controlled reference voltage is provided to reference the circuit. A comparator compares signals at the comparator inputs and provides an output dependent upon the comparator input signals. The output of the comparator enables or disables a controlled current charging circuit. The current charging circuit rapidly charges the capacitor when enabled.

Abstract: A charging circuit for a random access memory (RAM) backup battery for supplying a first charge current from a voltage supply to the battery for as long as the voltage supply is present, comprised of a first resistance apparatus for limiting the first charge current to a low predetermined value, a bypass conducting switch connected in parallel with the first resistance apparatus, and apparatus for detecting a low voltage condition of the voltage supply and for enabling operation of the bypass conducting switch thereby bypassing the first resistance apparatus and allowing discharge current to flow from the battery to the RAM.

Abstract: A reference voltage generating circuit of a DRAM includes a current mirror circuit constituted of first to fourth transistors. The gate of the third transistor is connected to the source of a fifth transistor. When a zero-power on reset signal, which becomes L on turn-on of the power supply, and becomes H after a predetermined period, is applied to the gate of the fifth transistor, and an external power supply voltage is forced to be applied to the gate of the third transistor on turn-on of the power supply, a reference voltage following the rise of the external power supply voltage is provided from the output of the current mirror circuit.

Abstract: A circuit for converting a system supply voltage having one of two levels to a voltage for use by an integrated analog circuit connected to the system upon power-up. The circuit uses a diode-connected transistor to generate a reference voltage necessary for a regulator to regulate the supply voltage when the supply voltage is first powered up. The regulated supply voltage is doubled to a voltage level sufficient to activate the integrated analog circuit's bandgap voltage. The activated bandgap voltage is thus switched on to supply a more precise reference voltage to the regulator so that the diode-connected transistor may be de-activated to conserve power. The circuit also provides a bypass path for connecting the supply voltage directly to the integrated analog circuit when the supply voltage is the same level as the necessary voltage for the integrated analog circuit.

Abstract: An input buffer circuit includes an output circuit and supplies a plurality of signals in response to an input signal. A delay line is constituted of a plurality of delay cells connected in series and delays the signals supplied from the input buffer circuit. A PLL circuit connected to the delay line, includes a level converter which outputs a control signal for controlling a delay time of the delay line. An output signal generation circuit generates a signal having a multiplied frequency from the output signal of the input buffer circuit and the output signal of a tap of the delay line. Each of the delay cells has an output circuit having the same arrangement as that of the output circuit provided in the input buffer circuit, and a clocked inverter circuit included in each of the output circuits of the delay cells and input buffer circuit is controlled by the control signal output from the level converter.

Abstract: Novel high voltage amplifiers that are capable of being monolithically integrated using low voltage semiconductor fabrication processes are described and claimed. A cascade of low voltage current mirrors is described that can act as a high voltage amplifier output circuit. A high voltage current source circuit also is described and is constructed from the series combination of a low voltage transistor and a parasitic field oxide transistor. Additionally, a differential amplifier having bias current shunting transistors is described that can be used to limit quiescent current from the power supply of the high voltage amplifiers.

Abstract: The present invention allows initializing operations such as loading configuration data and preloading registers to begin before a user has released a reset signal. A circuit is provided which responds to the leading edge of a user's reset signal to generate an internal reset signal which begins the initializing operation. The circuit simultaneously starts a delayed signal which ends the internal reset signal. If the MRX signal is long, the chip becomes ready for operating upon release of the MRX signal, whereas if the MRX signal is short, the chip becomes ready for operating upon completion of any steps necessary for resetting the chip. In either case, after a reset signal is received, the chip becomes ready for operation in a shorter time than with the prior art circuits.

Abstract: A multi-phase charge pump continuously pumps to establish a DC voltage outside the range of supply and reference voltages according to the apparatus and methods of the present invention. The multi-phase charge pump in one embodiment includes four stages operating in a ring with a four-phase clock. Each stage includes a three-mode charge pump that generates and provides reset and control signals to other stages. Each stage includes a pass transistor having a gate driven in excess of the DC voltage for efficient transfer of charge. The gate drive signal from a first stage is coupled to a next stage in the ring where it is used to generate the next gate drive signal. Each gate drive signal corresponds to one waveform having a phase skewed in time so that each stage in the ring is operating in a different mode.

Abstract: A supply-voltage detector having a low minimum operational voltage while having a large variation is combined with a supply-voltage detector having a high detection precision while having a high minimum operational voltage, so that the supply voltage is detected at a high accuracy without malfunctioning even on a low voltage. A system, such as a microcomputer, could then be reset when the detected supply voltage falls below a certain value. This combined circuit will improve the accuracy of detecting this supply voltage.

Abstract: A smart power integrated circuit with dynamic isolation. A P-type isolation region surrounds the small signal devices (npn bipolar transistors and possibly other devices). This isolation region is held at ground in normal operation; but one or more pilot circuits continually monitor the collector voltages of the small-signal and power npn transistors, and instantly reconnect this isolation region, in real time, to the lowest collector voltage, whenever any of the collector voltages go below ground. Preferably a large capacitor provides a dedicated supply to the pilot circuit, so that the reconnection operation can proceed even when a power supply glitch occurs.

Abstract: The present invention is a closed-loop peak detection circuit comprising switching means, comparing means, control means, two current sources, and a holding capacitor. The switching means selectively provides one of a plurality of input signals to the comparing means. The control means is coupled to the comparing means. The control means receives first and second control signals for selecting one of three modes: reset, peak detect, and hold. First and second current sources are coupled to the control means. A capacitor is coupled to the first and second current sources for generating an output signal. The output signal is feedback coupled to the comparing means. The comparing means determines when one of the plurality of input signals exceeds the output signal. The control means enables and disables the current sources in response to the comparing means and to the first and second control signals.

Abstract: A feedback circuit (10) for use with a feedback arrangement includes an input terminal (12) for receiving a feedback signal from an output of the feedback arrangement. An output terminal (14) is coupled to a regulating arrangement of the feedback arrangement. A sampling arrangement (16) is coupled to the input terminal for providing a delayed feedback signal. A further arrangement (18,20,22,24,26,28) is coupled to the output terminal (14) for comparing the feedback signal with the delayed feedback signal and with a predetermined reference signal, such that the further arrangement (18,20,22,24,26,28) disables the regulating arrangement if a certain relationship exists between the compared signals.

Abstract: A clocked comparator circuit compares the primary and backup power supply voltages to a system. When the primary voltage falls a given amount below the backup, the circuit provides a signal that may be used to switch to the backup power supply. When the primary voltage is again present, the circuit can switch back to primary power. Alternatively, or additionally, a signal may be generated to initiate graceful shutdown of the system. The clock to the comparator typically operates at a higher frequency when operating on the primary voltage, and a lower frequency when operating on the backup voltage. This circuit is typically used with a portable system that uses a rechargeable battery as its primary power supply. The backup power supply may be a long-life battery that provides power to only a portion of the system. For example, in a computer, only a static memory may be powered by the backup, to allow the full system to retain its proper configuration when the primary power supply is again activated.

Abstract: A CMOS power-on reset circuit has a delay capacitor to provide a predetermined delay period. Charging and discharging of the delay capacitor is controlled by the state of a flipflop circuit. An input comparator monitors a power supply input voltage. An invalid input voltage level immediately changes the reset output signal to the invalid state and discharges the capacitor. Even after the input voltage has recovered to a valid level, recharging the capacitor is delayed until the capacitor has substantially discharged, thereby ensuring at least a predetermined delay period after the last fault condition. The reset output signal is coupled in a feedback configuration so as to lower the threshold voltage when the reset output switches to the valid state, to allow limited power supply sag, for example due to motor start-up, without resetting the circuit.

Abstract: In a memory unit having a sense amplifier for reading data, the dependence of the memory cell current detection level of the sense amplifier on the power source voltage is restrained. A memory-unit sense amplifier includes a bias circuit (20, 21, 22) for generating an output which mitigates fluctuations in the power source voltage VDD; and a detection result output section (10, 15) which outputs a memory cell current detection result obtained for the purpose of obtaining the value of memory cell data and which has a Pch (P-channel transistor), to the gate of which the output of the bias circuit (20, 21, 22) is connected, whereby fluctuations in the source/gate voltage of the Pch 10 are mitigated so as to restrain the dependence of the memory cell current detection level on the power source voltage.

Abstract: A simple CMOS voltage reference circuit develops a reference voltage from the sum of the threshold voltages of a pair of complementary devices. In a p-type substrate a p-channel device is formed in an isolated n-type well, with the well tied to the source at the reference node. The drain is coupled to the drain of a complementary n-channel device. An additional p-channel device functions as a current source. The voltage reference circuit may be advantageously cascaded to improve stability and insensitivity to the power supply voltage.

Abstract: An automatic SCSI termination circuit has means detecting the occupied or vacant status of one or more SCSI interconnection ports and enables or disables termination, which is applied to the ports without need for manual intervention.