Abstract: One apparatus includes a notch filter that has a state observer unit and a parameter adaptation unit. The state observer unit is configured to receive a sampled noisy electrical signal and a sampled filtered electrical signal, the state observer unit having an estimated noise signal output, the estimated noise signal output carrying an estimated noise signal to be subtracted from the sampled noisy electrical signal, resulting in the filtered electrical signal. The parameter adaptation unit is configured to receive the estimated noise signal and an error signal from the state observer unit. The parameter adaptation unit is also configured to determine, based on the estimated noise signal and the error signal, an updated estimated noise frequency, thereby causing the state observer unit to generate an updated estimated noise signal to be provided on the estimated noise signal output.

Abstract: An electronic component includes a driver that outputs a signal to a reception apparatus; a storage device storing therein reflection information related to a reflected wave that returns to the driver when the signal is reflected back by the reception apparatus; a reflected wave detector that based on the reflection information, determines a measurement period for measuring the reflected wave and that based on the measurement period, measures an arrival time and a peak amplitude of the reflected wave; and a controller that based on the arrival time and the peak amplitude, extracts reflected-wave cancelling information for inhibiting effects of the reflected wave from the reception apparatus and that sets the extracted reflected-wave cancelling information in the driver.

Abstract: For an input signal with a ringing superposed thereon, a ringing-generating filter generates an analogous ringing waveform from only a peak portion of the signal which precedes the ringing. A subtractor subtracts the analogous ringing waveform from the input signal to eliminate the ringing. The coefficient of the filter is determined by applying a calculation method similar to a polynomial division based on the complete pivoting Gaussian elimination to polynomials using a reference data expressing a peak waveform and a ringing waveform, and by using a least squares method for minimizing the square of the covariance so as to allow the presence of noise in the data. Furthermore, by a repetitive process on a plurality of the same datasets, the calculation accuracy of the coefficient is improved even under the condition that the ringing frequency is high and the number of samples in one cycle is small.

Abstract: The present invention provides a semiconductor structure, including a substrate, a first TSV, an inductor and a capacitor. The first TSV is disposed in the substrate and has a first signal. The inductor is disposed in the substrate. The capacitor is electrically connected to the inductor to form an LC circuit to bypass the noise from the first signal. The present invention further provides a method of reducing the signal noise in a semiconductor structure.

Abstract: A method and system avoid ringing at an external power transistor subsequent to switching OFF the external power transistor. A driver circuit generates a drive signal for switching the external power transistor between OFF-state and ON-state. The driver circuit comprises a drive signal generation unit configured to generate a high drive signal triggering the external power transistor to switch to ON-state, wherein an output resistance of the driver circuit is adjustable, an oscillation detection unit to detect a degree of oscillation on the drive signal, and a resistance control unit to adjust the output resistance of the driver circuit based on the degree of oscillation on the drive signal.

Abstract: A touch recognition apparatus and method in a capacitive touch screen are provided. The touch recognition apparatus includes a touch panel and a controller. The touch panel includes a first sub panel and a second panel intersecting each other. The first sub panel includes a first electrode line and a second electrode line in X axis, and a plurality of resistors connected between the first electrode line and the second electrode line in X axis. The controller outputs scan signals to the first electrode line in X axis and the first electrode line in Y axis, receives scan sensing signals through the second electrode line in X axis and the second electrode line in Y axis, and measures delay times between the scan signals and the scan sensing signals to touched positions in X axis and Y axis, respectively.

Abstract: A method and apparatus for an adjustable filter system comprises a first integrated circuit generating a reference value that represents a corner frequency of a filter within the first integrated circuit; sending the reference value that represents the corner frequency of the filter across an interface to a second integrated circuit; receiving, across the interface from the second integrated circuit, a filter adjustment value; and changing the corner frequency of the filter using the filter adjustment value to adjust a passband and a stopband of the filter. The apparatus and method also comprises a second integrated circuit detecting a filter adjustment event, wherein the filter adjustment event comprises receipt of the reference value; calculating the filter adjustment value to change a corner frequency of the filter within a first integrated circuit; and sending the filter adjustment value across the interface to the first integrated circuit.

Abstract: Systems and methods for measuring transmitter and/or receiver I/Q impairments are disclosed, including iterative methods for measuring transmitter I/Q impairments using shared local oscillators, iterative methods for measuring transmitter I/Q impairments using intentionally-offset local oscillators, and methods for measuring receiver I/Q impairments. Also disclosed are methods for computing I/Q impairments from a sampled complex signal, methods for computing DC properties of a signal path between the transmitter and receiver, and methods for transforming I/Q impairments through a linear system.

Abstract: The present invention relates to a semiconductor circuit including: a delay unit for delaying an input signal by a predetermined time to output the delayed signal; a voltage adjusting unit for charging and discharging voltage according to a level of the input signal; and a combination unit for controlling the charging and discharging operations of the voltage adjusting unit according to signals generated using the level of the input signal and a level of the signal output from the delay unit, and it is possible to effectively remove low level noise and high level noise which are respectively mixed in a high level signal and a low level signal input to the semiconductor circuit.

Abstract: One embodiment of an apparatus for cancelling supply noise includes an input circuit operable to receive an input from a charge pump and a drive circuit connected to an output of the input circuit. The drive circuit is operable to provide an output matching the input to the input circuit when a voltage source powering the input circuit and the drive circuit is stable, and to introduce a contrary voltage change on the buffered output when the voltage source is noisy, with the contrary voltage change being contrary to a voltage change on the voltage source due to noise.

Abstract: Systems and methods are provided for decoding signal vectors in multiple-input multiple-output (MIMO) systems, where the receiver has received one or more signal vectors from the same transmitted vector. The receiver combines the received vectors by vector concatenation The concatenated vector may then be decoded using, for example, maximum-likelihood decoding. In some embodiments, the combined signal vector is equalized before decoding.

Abstract: A circuit and method are provided for a power converter to select one from a plurality of current limit signals as a final current limit signal according to the present duty ratio of a power switch for the pulse width modulation of the next cycle, so that the duty ratio of the power switch in the next cycle is prevented from acute variation to eliminate sub-harmonic which otherwise may happen.

Abstract: A micro electro-mechanical system (MEMS) circuit includes a MEMS differential capacitor, a read-out circuit, a control circuit, and a compensation circuit. The MEMS differential capacitor includes a first capacitor and a second capacitor. The read-out circuit is coupled to the MEMS differential capacitor for reading a difference between the first capacitor and the second capacitor in a zero-G condition, and generating an output signal according to the difference. The control circuit is coupled to the read-out circuit for receiving the output signal and generating a control signal. The compensation circuit is coupled to the control circuit for compensating the MEMS differential capacitor according to the control signal.

Abstract: In order to output an accurate waveform in which quantization noise has been cancelled out, provided is a signal generating apparatus that outputs an output signal corresponding to a waveform data sequence expressing a waveform, the signal generating apparatus comprising a DA converting section that outputs an analog signal by sequentially performing digital/analog conversion on each piece of data included in the waveform data sequence, at a timing of a sampling clock; and a jitter injecting section that injects jitter decreasing a quantization noise component of the output signal, into the sampling clock supplied to the DA converting section.

Abstract: A semiconductor integrated circuit includes a user circuit and a power supply noise suppression circuit. The user circuit includes a plurality of circuit modules each containing an operation ratio control circuit. The power supply noise suppression circuit judges an amount of current fluctuation occurring in the user circuit by monitoring an operation ratio of each of the plurality of circuit modules, and controls, via each of the operation ratio control circuits, the operation ratio of a corresponding one of the circuit modules in accordance with a result of the judgment of the amount of current fluctuation.

Abstract: According to embodiments, dual path loop filter circuits are described which have, for example, a single charge pump. The current flow in the DPLF circuit is architected to source, during an injection time period, a first current to the loop filter, sink, also during the injection time period, a second current from the loop filter, wherein the first current has a magnitude of ?*I and the second current has a magnitude of ?*I, and sink, during a linearization time period, a third current from the loop filter, wherein the third current has a magnitude of (???)*I.

Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit that transmits data in parallel through a plurality of signal lines and a data receiving circuit that receives the data. The data transmitting circuit includes a plurality of data output circuits that output the data in a data transmission mode or set an output to a high impedance state in a HiZ mode, a plurality of data selection circuits that select one of the data and fixed data and output the selected data to the data output circuits, and a control circuit that controls the data output circuits to output the fixed data during a period between a time when a mode is switched from the HiZ mode to the data transmission mode and a time when the data output circuits start to output the data.

Abstract: An electronic device includes a first electronic component and a second electronic component that is connected to the first electronic component via a signal line in which a signal is transmitted and received. An electronic device includes a plurality of conductive lines that is arranged in parallel with the signal line with the signal line interposed therebetween, between the first electronic component and the second electronic component. An electronic device includes a detecting unit that detects an amount of noise which each of the conductive lines receives from another signal line and a correcting unit that reduces noise which the signal received in the signal line receives from the other signal line using the amount of noise detected by the detecting unit.

Abstract: A solution for compensating intermodulation distortion of a component is provided. A circuit element includes multiple connected components. At least two of the connected components comprise current-voltage characteristics of opposite signs (e.g., sublinear and superlinear current-voltage characteristics) such that the current-voltage characteristics of the circuit element produces a level of intermodulation distortion for the circuit element lower than a level of intermodulation distortion for each of the connected components.

Abstract: A transceiver mitigates signal leakage into a receive path from a transmit path. A subtraction circuit determines a difference between a receive signal and a compensation signal to produce a compensated receive signal prior to demodulation by a demodulator. An equalizer both amplitude adjusts and phase adjusts orthogonal baseband transmit signals based on the difference from the subtraction circuit to produce the compensation signal. A digital tuning circuit determines at least one amplitude adjust coefficient to be used by the equalizer. The equalizer can have a polarity switch or a variable attenuator or a variable delay.

Abstract: An apparatus for propagating local oscillator signals in a circuit, the apparatus comprising two pairs of lines carrying respectively differential in-phase and quadrature signals. The lines are arranged such that in at least one region along their length one of each pair of lines crosses the other of the pair to create a twist. The twist(s) in each respective pair of lines is offset from the twist(s) in the other pair of lines such that the portion of their length over which the in-phase lines magnetically couple to the quadrature lines with a positive coupling coefficient is substantially equal to the portion of their length over which the in-phase lines magnetically couple to the quadrature lines with a negative coupling coefficient.

Abstract: In accordance with an embodiment, a noise reduction circuit includes one or more phase sampling circuits that receive an electromagnetic signal and splits the signal into an illuminated component and an ambient component. The illuminated component is transmitted along an illuminated signal path and converted to a digital signal and the ambient component is transmitted along an ambient signal path and converted to a digital signal. The digitized ambient component is subtracted from the digitized illuminated component to generate a light signal with a reduced noise component.

Abstract: A method of calibrating a filter includes applying an input signal into the filter to generate an output signal, measuring a phase difference between the input signal and the output signal; determining a leading/lagging status of the phase difference; calculating a capacitor code (CAP_CODE) using the leading/lagging status; and calibrating the capacitor using the CAP_CODE.

Abstract: A method for reducing spurious for a clock distribution system, the method including a) providing a system controller, b) providing clock distribution system, c) inputting characteristics of the clock distribution system in advance of operation thereof, d) calculating an expected level of the integer boundary spurious as a function of a fractional offset value, e) selecting an integer boundary solution based on the fractional offset value being within a preferred predetermined region, and f) programming the master clock subsystem and the one or more fractional synthesizers with the integer boundary solution, and g) repeating steps d) through f) as needed.

Abstract: A semiconductor device includes a first terminal for receiving a first signal; a second terminal for receiving a second signal having more restriction than the first signal with respect to a delay upon transmitting to an internal circuit; a first noise reduction circuit; and a second noise reduction circuit. The first noise reduction circuit includes a first Schmitt circuit for receiving the first signal from the first terminal; and an output signal adjusting unit for adjusting an output signal of the first Schmitt circuit when the output signal is maintained for a specific period of time after the output signal is varied. The second noise reduction circuit includes a second Schmitt circuit for receiving the second signal from the second terminal; and an input signal adjusting unit for adjusting the second signal input to the second Schmitt circuit according to a fluctuation of a power source voltage.

Abstract: Digital signals with higher resolution are generated from dual-phase encode signals indicating phase changes of a position or an angle of a target. A signal processing apparatus for processing dual-phase encode signals indicating changes in position of a target, comprises: a first noise reduction unit configured to remove high frequency noise from each of the dual-phase encode signals before interpolation processing; an interpolating unit configured to apply interpolation processing to the dual-phase encode signals output from the first noise reduction unit to generate dual-phase encode signals with higher resolution; and a second noise reduction unit configured to remove noise from the dual-phase encode signals output from the interpolating unit.

Abstract: A slave electronic device is provided, including a capture unit, at least one low-speed unit and an embedded control unit. The capture unit is coupled to a host electronic device through a transmission lane to filter out a high-frequency signal part from a control signal outputted by the host electronic device to generate a low-frequency control signal, wherein the control signal has a plurality of periods and the control signal respectively has a low-frequency signal part and the high-frequency signal part during odd periods and even periods of the periods. The low-speed unit is coupled to the capture unit to operate according to the low-frequency control signal. The embedded control unit is coupled to the transmission lane for communicating with the host electronic device using a predetermined communications protocol via the high-frequency signal part.

Abstract: A method is provided for performing channel equalization on a wireless signal. The method includes: (i) formulating an equalizer associated with sub-carriers of the wireless signal, wherein the equalizer is a function of a quantity relating to signal quality (305); (ii) determining an adjoint of the equalizer over a selected number of the subcarriers (310); (iii) interpolating the adjoint determined in (ii) to obtain an adjoint of the equalizer over remaining ones of the subcarriers of the wireless signal (315); and (iv) generating an equalized signal for each of the subcarriers using the adjoint of the equalizer over the selected number of subcarriers and the interpolated adjoint over the remaining ones of the subcarriers (320).

Abstract: A method of canceling impulsive interference from a communications signal is provided. The method includes identifying an impulse interference contained in the communications signal, generating a model of impulse interference, matching the model in at least one of amplitude, phase and envelope time delay to the identified impulse interference, and cancelling the identified impulse interference by subtracting the matched model from the identified impulse interference.

Abstract: As a digitized representation of an intermediate frequency television signal moves through a demodulator it undergoes a number of processes, including conversion from an analog signal to a digitized data, digital signal processing of the digitized data, and the like. The rate at which the digitized data moves through the digital signal processor of the demodulator for processing is referred to as the data rate of the DSP. The demodulator can vary the data rate based on a selected television channel, thereby reducing the level of interference at the demodulator resulting from noise.

Abstract: The present invention relates to an electrical device for charging accumulator means (5), said electrical device comprising: a motor (6) connected to an external mains (11); an inverter (2) connected to the phases of said motor (6); and switching means (4) integrated into the inverter (2), said switching means (4) being configured to permit said motor (6) to be supplied and to permit the accumulator means (5) to be charged by the inverter (2). According to the invention, said electrical device further includes, for each phase of said motor (6), an RLC low-pass filter (18) connected, on the one hand, to the mid-point (16) of the phase of said motor (6) and, on the other hand, to ground.

Abstract: This invention compensates for the unintentional magnetic coupling between a first and second inductor of two different closely spaced inductors separated by a conversion circuit. A cancellation circuit formed from transistors senses the magnetic coupling in the first inductor and feeds a current opposite to the induced magnetic coupling captured by the second inductor such that the coupled magnetic coupling can be compensated and allows the first and second inductors to behave independently with regards to the coupled magnetic coupling between the first and second inductors. This allows the distance between the first and second inductors to be minimized which saves silicon area. In addition, the performance is improved since the overall capacitance in both circuits can be decreased. This cancellation technique to reduce the magnetic coupling between two closed placed inductively loaded circuits allows the design of a more compact and faster performing circuit.

Abstract: A system and method for improving the efficiency of an electrical circuit includes an electrical circuit including a first capacitor having a first and second terminal, and a second capacitor having a first and second terminal. A first resistor is connected to the first terminal of the first capacitor and a first terminal of the second capacitor. A second resistor is connected to a second terminal of the first capacitor and the second terminal of the second capacitor. A rheostat is connected to the first terminal of the first capacitor. A Zener diode is connected to the rheostat and the second terminal of the second capacitor. In some implementations, a power source is connected across at least one of the first terminal of the first capacitor and the first terminal of the second capacitor and the second terminal of the first capacitor and the second terminal of the second capacitor.

Abstract: A method for receiving a signal having a succession of symbols, transmitted by a digital modulation, each symbol transmitted having a phase and an amplitude belonging to a set of values in finite number, the method includes evaluating a phase error (PHE) on a received symbol (S), resulting from a signal transmission noise, correcting the phase of the received symbol according to the phase error evaluated, demodulating the symbol corrected in phase, and modeling the transmission noise by a Gaussian component not correlated with the signal received and defined by a power and an interference component defined by an amplitude and which phase is substantially uniformly distributed, the phase error of the received symbol evaluated on the basis of the power of Gaussian component and the amplitude of the interference component.

Abstract: There is provided an alternating current supply noise reducer for a 3D chip stack having two or more strata. Each of the strata has a respective one of a plurality of power distribution circuits and a respective one of a plurality of clock distribution circuits arranged thereon. The alternating current supply noise reducer includes a plurality of voltage droop sensors and a plurality of skew adjustors. The plurality of voltage droop sensors is for detecting alternating current supply noise in the plurality of power distribution circuits. One or more voltage droop sensors are respectively arranged on at least some of the strata. The plurality of skew adjusters are for delaying one or more clock signals provided by the plurality of clock distribution circuits responsive to an amount of the alternating current supply noise. Each skew adjuster is respectively arranged on the at least some of the strata.

Abstract: In conventional radio frequency (RF) systems, transmitters will usually convert baseband signals to RF so as to be transmitted. As part of the conversion process, the transmitters will perform digital predistortion (DPD), which uses feedback from a power amplifier. However, there are usually mismatches between the in-phase (I) and quadrature (Q) paths within with feedback loop. Traditional IQ correction filters were ineffective at providing adequate compensation for these mismatches, but here a filter is provided that provides adequate out-of-band compensation by use of frequency selectivity.

Abstract: In described embodiments, a Floating Tap, Feed Forward Equalizer (FT-FFE) achieves performance comparable to a full size, long FFE when equalizing wire line channels in, for example, SerDes receivers. A FT-FFE might be employed as a standalone datapath equalizer, or might be employed in conjunction with other equalization techniques.

Abstract: A PAM-N decision feedback equalizer (DFE) comprises a coefficient computation unit; a feedback unit that mitigates, using computed feedback coefficients, effects of interference from data symbols; an error-and-decision unit for at least computing a least error value respective to one of a plurality of decision levels, wherein the least error value indicates a difference of a pseudo equalized input PAM-N data symbol from an optimal position of the one of the plurality of decision levels, wherein the one of the plurality of decision levels corresponds to a modulation level used to modulate data in the input PAM-N data symbol; and a calibration unit for adaptively setting the plurality of decision levels based, in part, on the least error value, thereby enabling for compensating for gain changes resulted by a cable on which the input PAM-N data symbol is received and further compensating for embedded offsets of the error-and-decision unit.

Abstract: A filter including common mode feedback can provide single-ended to differential-ended conversion with minimum loss of performance.

Abstract: A filter circuit includes two parallel digital filters, a DAC, and an LPF. The DAC includes two parallel decoders, a parallel-to-serial converter, a switch driver, and a switch. A PLL circuit supplies a reference clock to the DAC. A frequency divider provided in the DAC divides the frequency of the reference clock by two, and supplies the half frequency clock to a parallel processing section (the two decoders and the parallel-to-serial converter) of the DAC and the two digital filters. This makes it easy to secure a timing margin, permitting use in high-speed communication on the order of several GHz.

Abstract: A clock network includes a first plurality of shield wires associated with a first plurality of clock lines and a second plurality of shield wires associated with a second plurality of clock lines. The clock network also includes a first plurality of clock activity program circuits associated with the first plurality of clock lines and a second plurality of clock activity program circuits associated with the second plurality of clock lines, wherein the first and second plurality of shield wires and the first and second plurality clock activity program circuits are configured to reduce power spikes.

Abstract: Disclosed is a noise removing circuit including: a voltage booster which boosts an input signal; and a regulator which receives an output signal of the voltage booster and reduces the signal's voltage higher than a specific value to the signal's voltage having the specific value and then outputs the signal.

Abstract: A system and method are disclosed for reducing the kickback disturbance in an electronic circuit. The system is based on the coupling of a programmable noise filter between bias blocks. In one embodiment the programmable noise filter includes capacitors, resisters and switches and forms a C-R-C circuit structure. By selecting the resistance and capacitance values and the status of the switches, the performance of the programmable noise filter is determined. Also disclosed is a system and method to reduce kickback disturbances comprising N+1 bias blocks, N programmable noise filters, and a bias reference generator, wherein N is equal to or greater than one.

Abstract: In order to output an accurate waveform in which quantization noise has been cancelled out, provided is a signal generating apparatus that outputs an output signal corresponding to a waveform data sequence expressing a waveform, the signal generating apparatus comprising a DA converting section that outputs an analog signal by sequentially performing digital/analog conversion on each piece of data included in the waveform data sequence, at a timing of a sampling clock; and a jitter injecting section that injects jitter decreasing a quantization noise component of the output signal, into the sampling clock supplied to the DA converting section.

Abstract: Signal processing method and apparatus having a first filter storage portion in which first filters are correlatively stored; a second filter storage portion in which second filters are correlatively stored; a first filter selection portion for selecting a first filter based on the power spectrum of the input image; a second filter selection portion for selecting a second filter based on the S/N of the input image; a third filter creation portion for creating a third filter by summing up the first and second filters; and a convolutional processing portion for convolving the input image using the created third filter.

Abstract: In described embodiments, a variety of down-sampling techniques are employed to generate a more constrained set of floating-tap positions when compared to floating-tap Decision Feedback Equalization (DFE) architectures that allow unconstrained 1T resolution or separated floating-tap positions. Down-sampling is employed to constrain the floating-tap positions rather than positions occurring with 1T resolution or spacing. Two broad down-sampling techniques, phase pruning and phase amalgamation, are applied to a variety of exemplary DFE implementations. Although the tap positions are more constrained, the architectures select floating-tap positions containing dominant reflection inter-symbol interference (ISI) terms.

Abstract: A method for communication includes receiving a signal, which carries data bits and is distorted by multiple impairments including one or more frequency offsets and one or more In-phase/Quadrature (I/Q) imbalances. A corrected signal is produced by applying to the received signal a sequence of corrections to compensate for the impairments. The sequence includes a first and a third correction of one correction type and a second correction of another correction type intervening between the first and third corrections in the sequence, the correction types consisting of frequency offset corrections and I/Q imbalance corrections. The data bits are extracted from the corrected signal.

Abstract: Receiver circuitry for processing a received Very Low Intermediate Frequency signal wherein the receiver circuitry comprises a main processing path. The main processing path comprises mixing circuitry arranged to mix a received VLIF signal with a frequency down conversion signal to produce a main path signal. The receiver circuitry further comprises a direct current cancellation path comprising mixing circuitry arranged to mix a DC element of the received VLIF signal with the frequency down conversion signal to produce a DC cancellation signal. The receiver circuitry still further comprises signal summing circuitry arranged to add the DC cancellation signal in anti-phase with the main path signal.

Abstract: A data equalizing circuit includes an equalizer configured to control a gain of data according to a value of a control code and output a controller gain; and a detection unit configured to divide n cycles of the data into N periods, count data transition frequencies for n/N periods while changing the value of the control code, calculate dispersion values of data transition frequencies for 1/N periods of the data from the data transition frequencies for the n/N periods, and finally output the value of the control code corresponding to a largest dispersion value, wherein n is equal to or greater than 2 and is set such that boundaries of the respective n/N periods of the data have different positions in the 1 UI data.

Abstract: A wireless communication system includes a) a first device having a transmitter part with a Tx-antenna for transmitting an electrical signal having a signal bandwidth BWsig and b) a second device having a receiver part with an Rx-antenna for receiving the transmitted electromagnetic signal. At least one of the Tx- and Rx- antennas is a narrowband antenna having an antenna bandwidth BWant, wherein the Tx- and/or Rx-antenna bandwidths fulfil the relation BWant=k·BWsig. The system is adapted to provide that k is smaller than 1.25, and the antenna bandwidth BWant is defined as the ?3dB bandwidth of the loaded antenna when it is connected to the communication system, and the signal bandwidth BWsig is defined as the bandwidth within which 99% of the desired signal power is located.