Abstract: A 3-terminal operational filter circuit is presented that can be used to construct various types of active filters. The filter circuit can be configured to provide 2nd order low pass and band-pass frequency responses by coupling three resistors to the three filter terminals. Similarly, the filter circuit can be configured to provide 2nd order band-pass and high pass frequency responses by coupling two resistors and a capacitor to the three filter terminals. Furthermore, a plurality of filter circuits can be cascaded to construct various types of higher order filters. The filter circuit can be manufactured to operate within a selected range of center frequencies by selecting particular values for the internal filter capacitance and resistance. Users can then select a particular center frequency, quality factor, and gain of the filter circuit by selecting particular values for the circuit elements to be coupled to the three terminals.

Abstract: A circuit is designed with a first transconductor circuit (903) with a first input terminal (901) coupled to receive a voltage signal, a second input terminal (1017) coupled to receive a control signal and an output terminal. The first transconductor circuit has a gain responsive to the control signal. A first integrator circuit (905) has an input terminal coupled to the first transconductor circuit output terminal and has an output terminal. A second transconductor circuit (909) has an input terminal coupled to the first integrator circuit output terminal and an output terminal. A second integrator circuit (911) has an input terminal coupled to the second transconductor circuit output terminal and has an output terminal.

Abstract: A filter system includes a low pass filter, a first summer circuit, a second low pass filter and a second summer circuit. The first low pass filter includes an input, an output, a storage means, a switching means and a control means. An input signal is placed on the input. An output signal is generated on the output. The storage means provides storage of a signal sample over time. The switching means, when closed, electrically couples the input to the first end of the storage means. The switching means, when open electrically isolates the input from the first end of the storage means. The control means controls the switching means. The control means generates a switching control signal. The switching control signal has a sampling frequency. A maximum cutoff frequency of the low pass filter is dependent on a value of a capacitance provided by the storage means, the sampling frequency, and a pulse width of the switching control signal.

Abstract: The integrated low-pass filter has a resistor connected, on the one hand, to an input terminal and, on the other hand, to a first capacitor and to the control terminal of a transistor. The output circuit of the transistor is connected, on the one hand, to the first capacitor and to an output terminal of the circuit. Furthermore, the output circuit of the transistor is also connected, via a current source and a second capacitor, to a first reference potential. On the other end, the output circuit of the transistor is connected to a second reference potential.

Abstract: A circuit and method for providing temperature stability in an FM quadrature detector. The circuit includes a feedback branch that feeds a portion of the dc output voltage to a varactor diode that is connected in parallel with a capacitor of an LC circuit in the quadrature detector. When the ambient temperature of the LC circuit of the quadrature detector changes, the resonant frequency shifts from the desired center value and a dc voltage is introduced at the output of the quadrature detector. The dc voltage is input to the varactor diode via the feedback circuit branch, and the capacitance of the varactor diode, which is dependent on the dc voltage applied to it, causes the overall capacitance of the LC circuit to change. The change in overall capacitance of the LC circuit caused by the capacitance of the varactor diode causes the resonant frequency of the quadrature detector to shift to be more closely maintained at the desired center frequency.

Abstract: A low power pulse amplifier with low duty cycle errors. The amplifier provides several differential amplifier stages with a biasing and canceling network. To minimize duty cycle errors for large input signals, cascode transistors are added between the drains of the differential amplifiers and the outputs. The result is an amplifier having a duty cycle error of less than 5% at amplitude input ranges from 5 millivolts to the supply voltage.

Abstract: An area-efficient low-pass, time-invariant, second-order reconstruction filter, particularly for current-driven digital-to-analog converters, including: a first resistor and a first capacitor which are parallel connected; an operational amplifier; a terminal of a second resistor which is connected to the inverting input of the operational amplifier; another terminal of the second resistor which is connected to a common node of the first resistor and the first capacitor; a second capacitor, which is ffeedback-connected between the output of the operational amplifier and the inverting input; and an additional pair of resistors which are arranged so as to provide feedback between the output and the inverting input, a current signal arriving from a digital-to-analog converter arranged upstream of the reconstruction filter being fed to a common node of the additional pair of resistors.

Abstract: A polyphase filter passes a desired frequency and attenuates an image frequency in many communication systems. The invention is an error correction circuit that compensates the polyphase filter for low open loop gain operational amplifiers. When multiple polyphase filters are used in communication circuits on a single integrated circuit (IC), the open loop gain of the operational amplifiers is limited by the IC's ability to dissipate power. The error correction circuit reduces the dependency of the polyphase filter performance on the low open loop gain of its operational amplifiers and hence, on temperature and IC process parameters.

Abstract: A filter having a semiconductor chip and a low pass filter section on the chip. The low pass filter section includes a filter transconductor and a filter capacitor connected to the filter capacitor. The low pass filter section has a cut-off frequency related to the transconductance, gmF, of the filter transconductor and the capacitance of the filter capacitor. A gm control circuit having a control circuit transconductor is provided. The gm control circuit includes a first oscillator for producing a reference frequency. The first oscillator has a portion thereof on the chip and an off-chip capacitor and off-chip resistor. The reference frequency is a function of the capacitance of the off-chip capacitor and the resistance of the off-chip resistor. A second oscillator is on the chip and produces a variable frequency. The second oscillator has an on-chip capacitor.

Abstract: A switched-capacitor cosine filter circuit includes a differential amplifier and a switched-capacitor circuit. A set of control signals cause the switched-capacitor circuit to selectively couple the inputs and output of the differential amplifier thereby producing a switched input signal for the differential amplifier. During alternating states of the control signals, the switched-capacitor cosine filter circuit samples the input signal as a noninverting and inverting integrator circuit.

Abstract: Provided is a circuit arrangement for attaining an all-pass filter characteristics which have been conventionally attained by bipolar transistors, by using MIS transistors. An alternating-current signal is input to an input terminal of an inversion circuit having a two-fold amplification function through a low-pass filter. When output from the inversion circuit is input to a gate of a lower transistor of two MIS transistors cascaded and an inverted signal of the alternating-current signal is input to a gate of an upper transistor of the two MIS transistors cascaded, the alternating-current signal is subtracted from the output from the inversion circuit. In this manner, the all-pass filter is formed.

Abstract: A baseline correction circuit (BCC) that compensates for the offset present on a PWM signal in an optical readback system when associated transients first appear in the PWM signal, and then compensates for the decay in the PWM signal so that significant baseline variations are minimized. The BCC includes a BCC switch coupled to switch the PWM signal responsive to a control unit and a low pass filter coupled through the BCC switch to receive the PWM signal. The low pass filter includes a capacitor coupled between the PWM signal and a ground reference, which stores the voltage of the baseline variation. A difference amplifier is connected to receive the low pass filtered output and also the PWM signal, and to provide a difference signal responsive to the difference between these two signals. The resultant signal is a high-pass filtered version of the PWM signal originally supplied to the BCC.

Abstract: A 90° phase shift circuit receives an input signal to generate a Q-signal and an I-signal having a phase difference of 90° therebetween. The 90° phase shift circuit has a CR-type high-pass filter having a variable capacitor and fixed resistor, a CR-type low-pass filter having a variable capacitor and a fixed resistor, and a level comparator for comparing the amplitudes of both the outputs from the filters to feed-back a control signal for controlling the cut-off frequencies of both the filters.

Abstract: The present invention relates to a circuit including at least one analog processing cell having a time constant determined by a capacitor and a resistor. A calibration circuit comprises a bridge formed of a switched-capacitance resistor and of a resistor adjustable by means of a digital control signal; and a feedback loop to adjust the digital control signal so that the voltage at the midpoint of the bridge is equal to a predetermined fraction of the voltage applied across the bridge. The resistor of the processing cell is also adjustable by the digital control signal.

Abstract: An integrator and a filter having offset compensated switched-opamp are implemented in the present invention. In the present invention, offset voltages caused by amplifiers used in a integrator or a filter can be compensated and such circuits can be operated under a low power voltage.

Abstract: A hybrid loop filter includes an integrator having an input and an output wherein the output forms an output of the hybrid loop filter, a plurality of transconductance amplifiers having an input and an output wherein each output of the plurality of transconductance amplifiers is coupled to the input of the integrator, a switched capacitor low pass chain having an input and a plurality of branches wherein each of the plurality of branches is coupled to the input of a separate one of said plurality of transconductance amplifiers, and a feedthrough branch having an input and an output wherein the input is coupled to the input of the switched capacitor low pass chain to form an input of said hybrid loop filter, and the output is coupled to the input of a separate one of the plurality of transconductance amplifiers.

Abstract: In a load-side filter of an n-phase converter circuit arrangement, the capacitors are arranged in at least two n-phase capacitor groups, one of which is hard-grounded and the other of which is grounded with a high impedance via a grounding resistor.

Abstract: A network line equalizer includes a transconductance-controlled, tunable single zero, single pole filter that eliminates the necessity of feedback loops or operational amplifiers. The equalizer includes a first MOS transistor having a first size (S1) and a gate for receiving input voltage signal and in response outputting a first current signal. A low pass filter composed of MOS transistors outputs a filtered voltage signal, and a second MOS transistor converts the filtered voltage signal to a second current signal. The second MOS transistor has a size (S2) relative to the first size (S1) such that S2=S1 (z-p)/p, where z is the zero and p is the pole of the filter. The circuit can be duplicated for filtering of differential input voltage signals, where the four current signals can be selectively combined based on whether the zero is at a lower frequency than the pole.

Abstract: The fine protection circuit arrangement is to reduce the remaining residual impulses on gas tube charge eliminators. This is to be achieved by means of a cascading of a gas tube charge eliminator or a .lambda./4 shorting stub with a fine protection circuit. The fine protection circuit connected to the gas tube circuit eliminator or .lambda./4 shorting stub reduces the relatively high residual voltage at the output of the gas tube charge eliminator or .lambda./4 shorting stub to a minimal value.

Abstract: A switched capacitor wherein one of the plates of the capacitor to be switched is fed with the input signal via a transistor switch receiving as control signal at the gate thereof a pulse train with predetermined frequency. For compensating the parasitic capacitance of the transistor switch, a compensation component is located between the transistor switch and the capacitor to be switched. This compensation component is formed as an incomplete transistor structure, such as only 1/2 of a transistor, has a drain region in common with transistor switch and has an insulated gate. The parasitic capacitance of the compensation component thus is established mainly by the capacitance between the insulated gate and the drain region and thus corresponds to the parasitic capacitance of the transistor switch, whereby complete compensation with optimized charge transfer is achieved.

Abstract: A double sampling analog low pass filter for converting differential inputs of first and second analog signals into a single-ended output signal. The double sampling analog low pass filter having first and second input terminals and a final output terminal includes a first charging/discharging means including at lest one charge storing means, and for charging and/or discharging the charge storing means in response to at least one control signal on receiving a first analog input signal from the first input terminal and a second charging/discharging means including at least one charge storing means, and for charging and/or discharging the charge storing means in response to at least one control signal on receiving a second analog input signal from the second input terminal. A differential input single-ended output operational amplifier amplifies the difference between outputs from the first and second charging/discharging means.

Abstract: A continuous-time filter is highly linear even when used with reduced 3-volt power supplies. In each stage of a multi-stage ladder network, resistor networks are attached to each input of a differential op amp. Each resistor network uses fixed resistors in series between the inputs and an intermediate node, and a fixed input resistor between the intermediate node and the op-amp input. The fixed input resistor improves linearity compared with a linear transistor. A transistor connects the internal node to ground, acting as a variable resistor to adjust the equivalent resistance of the resistor network. A control voltage applied to the gate of the transistor is generated by an analog control loop. The control voltage is the voltage input to a voltage-controlled oscillator (VCO) in a phase-locked loop (PLL). The analog PLL control loop adjusts the control voltage and the resistance continuously as the filter operates.

Abstract: There is disclosed a low frequency filter. A low frequency cutoff filter includes a filter circuit having a capacitor connected between an input terminal and an output terminal and an active resistor connected to the output terminal, having a very large resistance, and a bias circuit having a negative feedback to set a biasing voltage of the active resistor to a desired value, thereby implementing the cutoff filter within a semiconductor chip as one set with the capacitor having a small capacitance. A low frequency pass filter includes an active resistor having a very large resistance, means for setting a biasing voltage of the active resistor to a desired value, and a capacitor connected between the output terminal and the ground. Therefore, the low pass filter can be integrated-circuited using even small capacitor.

Abstract: A signal shaping circuit for shaping amplitude shift keyed digital pulses of a digital data stream is set forth. The digital data stream is comprised of a plurality of symbols from which the signal shaping circuit generates an output signal having sinusoidally shaped transition regions between logic level transitions of the digital data stream. The signal shaping circuit comprises an input lead receiving each of the digital pulses of the digital data stream. A delay circuit receives each of the digital pulses of the digital data stream at the input lead and, after a predefined time delay, outputs delayed digital pulses corresponding to each of the digital pulses received at the input lead. A ringing filter circuit having a linear response receives each of the digital pulses of the digital data stream provided from the input lead and each of the digital pulses provided at the output of the delay circuit.

Abstract: A low pass filter includes an input, an output, a storage means, a switching means and a control means. The input receives an input signal. An output signal is generated on the output. The storage means is a sample storage element, for example, a capacitance. A first end of the storage means is connected to the output. The switching means is connected between the first end of the storage means and the input. The switching means, when closed, electrically connects the input to the first end of the storage means. When open, the switching means electrically isolates the input from the first end of the storage means. The control means controls the switching means. The control means generates a switching control signal. The switching control signal has a sampling frequency. The capacitance provided by the capacitance means and a pulse width of the switching control signal are selected so that a maximum cutoff frequency of the low pass filter is less than the sampling frequency divided by two.

Abstract: A digitally controlled tuner circuit for continuous-time filters. Active RC integrators include digitally programmable feedback capacitors to allow for digital fine tuning of their time constant. The PLL-based tuner circuit includes a sine-wave oscillator made up of the digitally-controlled active RC integrators.

Abstract: An input circuit is made up of an external signal input portion which inputs an external signal, a voltage level converting circuit which has an input terminal for inputting a signal from the external signal input circuit and which has an output terminal for outputng the signal to the internal circuit after a voltage level was converted, a first power supply terminal which has a first potential for driving the voltage level converting circuit, a second power supply terminal which has a second potential for driving the voltage level converting circuit, and a noise control portion which couples to the input terminal of the voltage level converting circuit, which controls a noise from the first power supply terminal and/or the second power supply terminal, and which has a first capacitor. Accordingly, the input circuit could be applied the stable signal to the internal circuit.

Abstract: A tunable integrator circuit having a main amplifier with an input resistor R and a feedback capacitor C and a tuning amplifier having a variable gain k between the output of the main amplifier and the feedback capacitor. The circuit has an effective capacitance of kC. Thus the integrator can be tuned to compensate for temperature and processing variations of the RC product by adjusting the gain of the tuning amplifier. The tuning amplifier can also be used to multiply the effective capacitance of the filter, kC, by increasing the gain k of the tuning amplifier beyond that needed to compensate for RC variations, thus reducing the area required for on-chip capacitances while maintaining a constant resistance. The circuit can be used independently or in conjunction with a capacitor array.

Abstract: A circuit (11) for tracking rapid changes in peak and trough voltages of a data signal includes a peak detector circuit (13) and a trough detector circuit (14) coupled to the input for detecting peaks and troughs in the data signal and providing a peak and trough detect output signals, respectively. A peak level rate of change detector (17) is coupled to the peak detector circuit (13) for detecting a rate of increase in the voltage level of detected peaks and to the trough detector circuit (14) for controlling the trough detector circuit to detect troughs when the voltage level of detected peaks rises rapidly. Similarly, a trough level rate of change detector (18) is coupled to the trough detector circuit (14) for detecting a rate of decrease in the voltage level of detected troughs and to the peak detector circuit (13) for controlling the peak detector circuit (13) to detect peaks when the voltage level of detected troughs falls rapidly.

Abstract: A level detector detects an input signal level. A rectifier (210) receives the input signal and provides a rectified signal. A prefilter (220) receives the rectified signal and attenuates high frequency components at frequencies near multiples of a decimation sample rate. The prefiltered signal is decimated (230) and low pass filtered by a lowpass filter (240) having a passband below the input frequency of the input signal. The level detector can be provided to control a variable gain stage circuit (935, 1010) which applies a gain to the input signal based on the level to form a dynamic range compressor or expander.

Abstract: A frequency dependent resistor is disclosed, in which a reactive load represented by a coil or a capacitor is connected to the output of a voltage-current converter thereby to constitute a phase rotator for rotating the phase of an input voltage by 90 degrees. Plural phase rotators are connected in cascade, and the output voltage of a phase rotator in an even-numbered stage is converted into a current and applied to the input terminal of the phase rotator in the first stage.

Abstract: A resistive element including a P-channel MOS device (101, 401, 402, 608a-608c) having a first and second current carrying electrodes, and a gate. The first current carrying electrode forms a first impedance terminal and the second current carrying electrode forms a second impedance terminal. A bias circuit (103, 104, 105, 106) coupled to the first current carrying electrode and gate of the P-channel MOS device (101, 401, 402, 608a-608c). The bias circuit (103, 104, 105, 106) generates a voltage less than the threshold voltage of the P-channel MOS device (101, 401, 402, 608a-608c).

Abstract: A switchable active filter circuit is formed which employs a ground based switch to direct a portion of a feedback current away from a virtual ground terminal of an operational amplifier, thereby providing enhanced circuit Q and greater phase control at frequencies approaching an octave from the unity gain crossover frequency of an operational amplifier used to form the filter. The circuit employs a switchable feedback tee which includes a first capacitor, a second capacitor, a third capacitor and a switch. The first capacitor and the second capacitor form a first series circuit which is connected from the output terminal to the input terminal of the operational amplifier. The third capacitor and the first switch are connected as a second series circuit which is coupled from circuit ground potential to a junction of the first capacitor and the second capacitor.

Abstract: An integrated, tuning circuit for tuning a MOSFET-C filter contains a tuning MOSFET and a differential amplifier. A current source is connected to the drain of the tuning MOSFET. The output of the amplifier is coupled to the drain of the tuning MOSFET and to a terminal that connects to the drains of the MOSFETs of the filter, so that the equivalent resistance of the filter is dependant on the current. The current source is coupled to a reference current generator, such that current supplied by the current source to the tuning MOSFET is proportional to the current supplied in the reference current generator, which in turn varies with process and environmental conditions of a capacitance. As a result, changes in process and environmental conditions oppositely affect the capacitance and resistance in the filter, resulting in a fixed RC product and fixed frequency response from the filter.

Abstract: The present invention provides an apparatus and method of tuning the frequency characteristics of a continuous-time filter. First and second test signals are provided to a filter means and the respective first and second responses of the filter means are measured. The first and second responses are compared and based on the comparison a tuning control signal is provided to the filter means to tune the frequency response characteristics of the filter means. During a tuning phase of operation, a first switch connects a test signal generator and disconnects a data signal generator from the transmission input of a continuous-time filter. A signal processor receives a signal from the transmission output from the continuous-time filter and produces a tuning control signal based on that signal. The test signal generator is comprised of means for providing a first test signal, which may be an alternating signal source ("A.C."), and means for providing a second test signal, which may be a direct signal source ("D.C.

Abstract: The present invention provides a higher order filter with low sensitivity to component values and to a method of designing the same. The higher order filter is constructed of second and/or third order filter circuits which have been desensitized with respect to component values and gain by impedance tapering the filter circuits. The filter circuits are impedance tapered by successively scaling the resistors and/or capacitors from left to right to minimize loading on the first filter section and to maximize the quality factor of the passive pole. The impedance of the filter sections is increased from left to right by increasing the resistor values and/or by decreasing the capacitor values from left to right. Once the lower order filter circuits have been designed, they are cascaded to provide a higher order filter with low sensitivity to component values and gain.

Abstract: The present invention provides a second order filter with low sensitivity to component values and a method for designing the filter. The filter is impedance tapered by increasing the impedance of the filter circuit from left to right so as to minimize loading on the first ladder section and to maximize the pole quality factor of the first section. The filter is designed so that the value of the resistor of the second ladder section of the filter is equal to the resistor value of the first section multiplied by a scaling factor r, which is greater than 1. The capacitor of the second ladder section has a value equal to the value of the capacitor of the first ladder section divided by a tapering factor .rho., which is also greater than 1. In accordance with the preferred embodiment, the capacitor and resistor tapering factors are equal, i.e., r=.rho.>1.

Abstract: A circuit configuration for smoothing an input voltage includes two input terminals for receiving the input voltage. A negative-feedback amplifier has two inputs and an output. A capacitor is connected to one of the inputs of the amplifier. An output terminal is connected to the output of the amplifier. A converter element has a first terminal connected to one of the input terminals, a second terminal connected to the one input of the amplifier and to the capacitor, and a third terminal connected to the output of the amplifier.

Abstract: A circuit configuration for offset compensation includes a filter device for ascertaining a direct component in an input signal delivered to it and a linking device for subtractive linking of the input signal and an output signal of the filter device. A tracking and holding device which is connected between the filter device and the linking device is controllable by a control signal. The control signal is furnished by a window comparator device having an input to which the input signal is applied. When the input signal is within a predetermined window, the tracking and holding device is located in a tracking mode, while otherwise it is in a holding mode.

Abstract: A filter device suitable for being integrated into a single IC chip comprises a reference signal generator, a first filter circuit, a second filter circuit, a phase-comparator circuit, and a low-pass filter. The reference signal generator is for generating a reference signal. The first filter circuit is connected between an input terminal and an output terminal of the filter device and has a first variable time constant circuit. The second filter circuit has a second variable time constant circuit similar to the first variable time constant circuit and is provided with the reference signal from the reference signal generator. The phase-comparator circuit is for comparing the phase of the reference signal with the phase of an output signal of the second filter circuit to generate an output signal based on the result of this comparison.

Abstract: An electrical circuit is disclosed that is capable of adjusting the peak-to-peak voltage of a binary signal symmetrically around a reference voltage, without human intervention and without introducing a transient response into the signal. One embodiment of the circuit comprises a current source, five resistors and two diodes, create an intelligent "voltage divider" that adjusts the peak-to-peak voltage of a binary signal symmetrically around a reference voltage.

Abstract: The object of the present invention is to obtain a charge domain signal filter by composing an digital filter circuit with analog/digital mixed circuit and by introducing the analog processing into the process of multiplication and addition consuming the most of the electric power so as to reduce the total power consumption. The present invention is composed of at least one AD converter; at least one reference charge supply unit; a coefficient supply unit for supplying coefficient signals; a plurality of DA converters acting in a charge domain for receiving digital signal outputs supplied from said AD converter and said coefficient signal supply unit, and for performing the multiplication type DA conversion using, as a reference signal, a reference charge packet generated by said reference charge supply unit; and one circuit of analog shift register composed of N stages of charge transfer devices.

Abstract: A low-pass filter circuit including a first sub-filter designed in integrated circuit technology. The first sub-filter includes high-impedance resistor elements and smaller capacitances. A second sub-filter preceding the first sub-filter is constructed with low-impedance resistor elements and higher capacitances.

Abstract: A switch mode voltage regulator with synchronous rectification that produces ripple cancellation with fast load response is described. The switch mode voltage regulator comprises a main step-down regulator with synchronous rectification with an auxiliary step-down regulator that produces an output ripple cancellation current that is equal but opposite to the output ripple of the main regulator during static load conditions. During changing load conditions a feedback control circuit changes the duty cycle of the main regulator while a time-delay circuit prevents a change of the duty cycle in the auxiliary regulator. Thus, the main regulator is allowed to change its average current while preventing a counteracting average current change in the auxiliary regulator. An embodiment is described in which the duty cycle in the auxiliary regulator is changed in phase with the duty cycle of main regulator to further improve the dynamic response to load changes.

Abstract: A method and system for enhancing a digital input signal and producing a modified digital output signal that can either be further digitally processed or that can be converted to an analog signal. A digital input signal passes through a low-pass filter, a high-pass filter and a bandpass filter. A digital signal emitted from a high-pass section of the bandpass filter is delivered to a dynamically-controlled multiplier operating in a digital domain. Digital signals emitted from the low-pass filter, the high-pass filter and the bandpass filter are summed with a signal multiplied by the dynamically-controlled multiplier. A process controller and a contour controller can be used to vary low-frequency boost and high-frequency boost delivered by the modified digital input signal which can then be converted to an analog audio output sample.

Abstract: An amplifier for an MR head comprises a means for switching cut-off frequencies of a plurality of lowpass filters, when a data signal superposed by a disturbance signal (a composite signal) is input from an MR head, a means for extracting the disturbance signal from the composite signal, a means for adding the extracted disturbance signal to the composite signal. Accordingly, it possible to obtain a data signal less influenced and less distorted even if a disturbance signal appears.

Abstract: A filter circuit comprises three stages 260, 270, 280, each having a differential input and a differential output. The output of stage 260 serves as the input of stage 270 and the output of stage 270 serves as the input of stage 280 respectively. Stage 260 comprises two transistor pairs 201, 202 and 203, 204. An input signal is applied to the base electrodes of transistors 201, 204 which causes a current change in their opposite transistor 202, 203. Transistors 202, 203 have their respective base and collector electrodes connected together. The collector electrodes of transistors 202, 203 constitute the output of stage 260. Stages 270 and 280 have essentially the same structure as stage 260. The arrangement offers high frequency capabilities from a low supply voltage. In another embodiment, a cut-off frequency is varied under control of controllable current sources.

Abstract: A signal reproduction circuit used for an MR head has a simple circuit configuration to suppress a disturbance signal caused by the contact between the MR head and a disk, and to remove the ripples completely from the reproduced signal. The signal reproduction circuit used for the MR head includes a first circuit for generating a switching signal in accordance with a disturbance signal extracted from an input data signal, a second circuit including a filter circuit and a switching circuit, the filter having a first and a second cut-off frequency, the switching circuit for switching either the first of second cut-off frequency for outputting an un-suppressed data signal and a suppressed disturbance signal.

Abstract: A low pass filter comprises a complementary signal generator circuit for receiving an input pulse signal to output a first and a second signals having phases inverse to each other, a first CR circuit inputted with the first signal, a second CR circuit inputted with the second signal, a flip-flop circuit, a set circuit, and a reset circuit. In the low pass filter, the set circuit detects an output signal of the first CR circuit by the threshold voltage value thereof to set the flip-flop circuit in accordance with a detection result, and the reset circuit detects an output signal of the second CR circuit by the same threshold voltage value to reset the flip-flop circuit in accordance with a detection result.

Abstract: A switched-capacitor gain-boost network includes a bank of N-substantially identical sampling capacitors connectable to an output node. An integrating capacitor has one node connected to a low potential node and a second node connected to the output node. The integrating capacitor is connected to the bank of sampling capacitors in parallel when the bank of sampling capacitors is connected to the output node. Sampling period switches are actuable during a sampling period to connect the sampling capacitors of the bank in parallel and to connect the bank between an analog signal input node and a low potential node to charge the sampling capacitors. Integrating period switches are actuable during an integrating period to connect the sampling capacitors of the bank in series and to connect the bank between a low potential node and the output node to dump the charge stored by the sampling capacitors onto the integrating capacitor. A method of providing dc gain to an analog input signal is also provided.