Abstract: An active filter circuit has differential transistors having first conductivity type bipolar transistors and load transistors having second conductivity type bipolar transistors. A connecting node between the differential transistors and the load transistors is driven by a middle electric potential. Voltage dependent characteristics of earth capacitance including parasitic capacitances parasitic to the differential transistors and the load transistors can be kept constant by offsetting the voltage dependent characteristics of the parasitic capacitances. It is thereby possible to make the active filter circuit small in size and the consumed electric power reduced.

Abstract: A DRAM includes an N-type well formed on a main surface of a P-type semiconductor substrate, an N-type impurity region formed on the main surface of the P-type semiconductor substrate, a P-type impurity region formed in the N-type well to be a storage node of a memory capacitor, and a polycrystalline silicon layer for connecting the P-type impurity region and the N-type impurity region. The N-type impurity layer, the P-type impurity layer, and the polycrystalline silicon layer constitute the storage node of the memory capacitor, and electrons of minority carriers flowing from the substrate to the N-type impurity layer are recombined with holes flowing from the N-type well to the P-type impurity layer.

Abstract: A gain cell circuit includes a logarithmic transformation circuit. The logarithmic transformation circuit includes a pair of first and second transistors, each of which has first and second current carrying electrodes and a control electrode. The control electrodes of the first and second transistors are coupled to input terminals of the logarithmic transformation circuit. The logarithmic transformation circuit further includes third and fourth transistors coupled to the first and second transistors. The third and fourth transistors have control electrodes serving as output terminals of the logarithmic transformation circuit, first current carrying electrodes connected at first and second circuit nodes to the second current carrying electrodes of the first and second transistors, and second current carrying electrodes coupled to a power supply voltage.

Abstract: An interstage circuit functions to combine a first differential voltage and a second differential voltage, the first and second differential voltages being either positive or negative, to produce a current at a single ended output. A first pair of PNP transistors generates a first current corresponding to the first differential voltage, if positive, summed with a first bias current. A first pair of NPN transistors generates a second current corresponding to the second differential voltage, if positive, summed with a second bias current. A second pair of PNP transistors generates a third current corresponding to the first differential voltage, if negative, summed with the second current. A second pair of NPN transistors generates a fourth current corresponding to the second differential voltage, if negative, summed with the first current. The third current is subtracted from the fourth current to produce the current at the single ended output.

Abstract: A master-slave differential comparator having a threshold value. The master section controls the threshold value of the slave section. The slave section is controlled by bias currents therein to matching same in the master section. The bias currents are substantially determined by fixed biases applied to the master section, the difference in biases being substantially equal to the threshold value of the comparator.

Abstract: A multiplier circuit includes first and second squaring circuits each having a differential input terminal pair. A first input terminal of the differential input terminal pair of the first squaring circuit is applied with a first input voltage and the second input terminal thereof is applied with a second input voltage opposite in phase to the first input voltage. A first input terminal of the differential input terminal pair of the second squaring circuit is supplied with the second input voltage and the second input terminal thereof is applied with the first input voltage. The first and second squaring circuits each includes two sets of unbalanced differential transistor pairs which are arranged so that their inputs are opposite in phase and their outputs are connected in common. The transistors of each unbalanced differential transistor pair have different emitter sizes.

Abstract: There is disclosed on optoelectronic integrated circuit comprising, a plurality of channels each including an optical receiving device for converting a received optical signal to an electric signal, and an amplifier for amplifying an output signal of the optical receiving device, the channels being integrated on the same semiconductor substrate, electric power source nodes of at least two of the amplifiers of the respective channels being connected to a common electric power source node, and the common electric power source node being connected through a resistor element to an electric source power supply terminal for supplying an electric source power to the channels.

Abstract: A cascode amplifier circuit including an input mirroring transistor (401) that generates a first output current (403) in response to the input signal. A diode connected transistor (404) generates a control bias proportional to the first output current. A cascode connected transistor output stage (405) includes a common source transistor (406) coupled to the input signal and the input mirroring transistor (401) for establishing an output current (407) in the cascode connected transistor output stage. A common gate transistor (408) is coupled to the diode connected transistor (404) and the common source transistor (406) for isolating the common source transistor (406) from any change in an output voltage present at an output terminal (409) of the common gate transistor (408) while operating to control the output currently(407) in response to the control bias.