Abstract: A driver circuit for outputting an output signal corresponding to an input signal given to the driver circuit, includes a voltage generating unit for outputting a basic output voltage corresponding to the input signal, a first buffer circuit for outputting an output voltage corresponding to the basic output voltage outputted by the voltage generating unit, a second buffer circuit, of which power consumption is larger than the first buffer circuit, for generating and outputting a voltage corresponding to the output voltage as the output signal, a simulating circuit including a simulating buffer circuit for generating a simulated voltage corresponding to the basic output voltage outputted by the voltage generating unit, the simulating buffer circuit having substantially the same characteristic as that of the first buffer circuit, and a controlling unit for controlling the basic output voltage outputted by the voltage generating unit based on the simulated voltage.

Abstract: A small-sized, light-weight display device having an audio output circuit is provided. A display device of the present invention has a flat speaker and an audio signal processing device is constructed from thin film semiconductor elements, typically, thin film transistors, on the display device. The speaker is driven by BTL driving, thereby reducing the power supply voltage and preventing degradation of the thin film transistors. A display device with a built-in audio signal processing circuit is thus reduced in size and weight.

Abstract: A duty cycle and phase placement sampling circuit that can be used for high accuracy sampling and correcting the duty cycle and placement of differential clock signals is provided. The duty cycle and phase placement sampling circuit includes dual differential input stages and re-timed precharge signals that allow for high accuracy sampling of common mode logic clock phases.

Abstract: An integrated circuit comprises a gain stage circuit coupled to a compensation circuit. Both the gain stage circuit and the compensation circuit respectively comprise a first current source and a second current source that are subject to the same process variations. A negative feedback circuit is used to generate a corrective current in relation to the second current source, indicative of a current that needs to flow through a load in addition to a current flowing through the second current source in order for a variable voltage to be substantially equal to a reference voltage used to drive the first and second current sources. A compensating current corresponding to the corrective current generated for the second current source is applied to the first current source to compensate for process variation in the gain stage circuit in respect to the first current source.

Abstract: A system for driving an electromagnetic field generator. In one aspect, the system may include a plurality of transistors arranged in an H-bridge configuration, the H-bridge having first and second output terminals, first and second switching inputs, and a power input. The system may further include a control transistor coupling the power input to a power supply, and a diode having a cathode coupled to the power input and an anode coupled to ground. The first and second output terminals may be coupled to the electromagnetic field generator and the first and second switching inputs may receive switching signals based on an output of the electromagnetic field generator.

Abstract: An output buffer circuit includes an input stage of which one end receives an input voltage and the other end receives an output voltage; a class AB output stage that increases a current flowing in the output stage when the difference between the input and output voltages is larger than 0; a floating current source that biases the class AB output stage; a summing circuit that is connected to the input stage, the floating current source, and the class AB output stage so as to sum up the current supplied from the input stage and the internal current supplied from the floating current source; and an offset compensating circuit that is connected to the input stage and is composed of a plurality of switching elements and resistors so as to detect an offset voltage to compensate.

Abstract: A transconductor tuning device tuning a transconductance using a current. The transconductor tuning device includes a tuning section that applies a tuning current and a reference voltage to a transconductor converting an input voltage signal into a current signal and thereby tunes a level of transconductance. The tuning section includes a tuning current generator that converts a bias signal supplied from a bias current source into a certain level of tuning current and outputs the tuning current to the transconductor. The transconductor includes a control voltage generator that generates a certain level of control voltage using the tuning current. Accordingly, the transconductance of the plurality of transconductors are tuned at the same level.

Abstract: A versatile, programmable, low-cost transmit line driver is provided. The line driver includes a digital-to-analog converter that receives a digital input and provides an analog output. The line driver is reconfigurable between the voltage mode of operation.

Abstract: A voltage conversion device having non-linear gain and changeable gain polarity includes a switch module, a gain decision module, a first voltage selection module, a second voltage selection module, a first switch unit, a second switch unit and a voltage output module. The switch module is used for outputting analog voltage provided by the analog voltage source or voltage corresponding to the system ground end. The gain decision module is used for determining a gain. The first voltage selection module is used for outputting a first DC voltage. The second voltage selection module is used for outputting a second DC voltage. The first switch unit is used for outputting the first DC voltage. The second switch unit is used for outputting the second DC voltage. The voltage output module is used for outputting an amplified result of a DC voltage according to the gain.

Abstract: An output circuit includes a differential section configured to amplify an inputted differential signal; a current source section configured to supply a current to the differential section; a load resistance section connected with the differential section; and a control unit configured to set a value of the current from the current source section and a resistance value of the load resistance section based on a signal supplied to the control unit. The output circuit converts the differential signal into an output signal of a different interface level from that of the differential signal and balance-transmits the output signal.

Abstract: Methods and apparatus are provided for improving phase switching and linearity in an analog phase interpolator. A phase interpolator in accordance with the present invention comprises (i) a plurality of tail current sources that are activated for substantially all times when the phase interpolator is operational; (ii) at least two pairs of input transistor devices, wherein one pair of the input transistor devices is associated with a minimum phase of the phase interpolator and another pair of the input transistor devices is associated with a maximum phase of the phase interpolator; and (iii) a plurality of current steering switches that provide currents generated by the plurality of tail current sources to one or more of the at least two pairs of input transistor devices, based on an applied interpolation control signal.

Abstract: Systems and methods are disclosed for providing automatic gain control of a multi-stage system. A method can include defining at least one parameter that is adapted to at least one of maximize hardware capacity of each of a plurality of gain stages and mitigate part-to-part variations of the multi-stage system. An order is selected for training the plurality of stages based on relative noise dominance for the plurality of stage. For a given stage of the plurality of stages, which is selected according to the selected order, output signals of the multi-stage system are measured over a plurality of gain settings for the given stage. A gain setting of the given stage of the multi-stage system also is configured based on the measured output signals relative to the at least one parameter defined for the given stage. The plurality of gain stages can include an analog equalizer as well programmable gain amplifiers connected in series.

Abstract: An operational amplifier includes: a differential amplifier for differentially amplifying first and second differential input signals to generate first and second output signals through first and second nodes; a driver for driving an output node in response to the second output signal; and a drive current adjuster for adjusting a driving current of the driver in response to the first output signal.

Abstract: A power amplifier circuit comprising first and second modules, a current source and a push-pull module. The push-pull module comprises two intermediate transistors and two output transistors. The circuit also comprises third and fourth modules, operating in current mirror mode. Inputs of the third module are respectively connected to one main electrode of one of the intermediate transistors and to a node internal to the first module. Outputs of the fourth module are respectively connected to a main electrode of the other intermediate transistor and to a node internal to the second module. The circuit is designed to form a power output stage of an operational amplifier.

Abstract: A predistorer configured for use with an RF power amplifier having an input loop configured to be coupled to the input of the RF power amplifier and peak control circuit. Such an input loop includes a look-up table containing predistortion values to be applied to an input signal, in response to the power in the input signal, for forming a predistorted input signal. The predistorter may further include an output loop, such an output loop configured to measure an intermodulation distortion product of the RF power amplifier output resulting from the predistorted input signal, and operable to update the predistortion values in the look-up table. Such a peak control circuit configured to select a power supply voltage for the RF power amplifier in response to the power in the input signal.

Abstract: Variable gain amplifiers offering high frequency response with improved linearity and reduced power dissipation are provided. An amplifier is disclosed that is constructed from a one-stage topology with multiple signal paths and compensation networks for improved linearity and stable operation. In this amplifier, improved performance is obtained by replacing single transistor components with enhanced active devices which incorporate local negative feedback. One embodiment of the invention is a transconductance enhancement circuit that improves transconductance and input impedance relative to the prior art. A further development is an enhanced active cascode circuit that provides improved linearity. A high frequency bipolar transistor switch is also disclosed that incorporates lateral PNP transistors as high frequency switches with improved OFF-state to ON-state impedance ratio to realize a variable gain function.

Abstract: A negative current generator for an amplifier circuit including a shunt transistor, first and second mirror transistors, a current bias device, and an amplifier. The amplifier circuit includes a current source transistor having current terminals coupled between a supply terminal and an input node and a control terminal receiving a bias voltage. The shunt transistor is coupled in a shunt configuration with the current source transistor. Each mirror transistor has a control terminal, a first current terminal coupled to the supply terminal and a second terminal coupled to a voltage node. The control terminal of the first mirror transistor receives another bias voltage. The current bias device draws a constant current from the voltage node. The amplifier has a first input receiving a reference voltage, a second input coupled to the voltage node, and an output coupled to the control terminals of the shunt and second mirror transistors.

Abstract: The two output currents (INP, IN) which are produced by a current source digital/analog converter (DAC) are supplied to the two halves of a symmetrical transimpedance amplifier. The input current (INP, IN) is supplied to a first stage, which is formed by a first transistor (N2), and a potential at the output of the first stage is supplied to a second stage, which is formed by a second transistor (N3), and the output voltage (VOUT, VOUTP) is formed by a potential at the output of the second stage. The output of the second stage is coupled to the output of the first stage through a Miller capacitor (Cm). The output of the transimpedance amplifier is coupled to its input by means of a connecting line which contains a feedback resistor (Rf).

Abstract: A switched operation amplifier including a biased circuit, an amplifier circuit, and a buffer circuit is provided. The biased circuit is to provide a first, a second, and a third biased signals by means of an input signal and a reference current source. The amplifier circuit is driven by the biased signals through current mirrors, a sample-and-hold switch, a complementary sample-and-hold switch and a differential pair. The buffer circuit includes a capacitor and two transistors in series. An output signal is generated from a node in between the two transistors, and fed back to a negative terminal of the differential pair of the amplifier circuit. The amplifier circuit charges the capacitor and controls one of the transistors of the buffer circuit until the voltages of a positive and the negative terminal of the differential pair are equal. By means of the operation of the switched op amplifier, the output voltage can be kept being stable.

Abstract: The present invention provides an amplifier for amplifying a high-frequency signal and outputting an amplified signal. The amplifier includes: an amplification element which is a bipolar transistor or a field-effect transistor; and an inductor connected between a base and a collector or between a gate and a drain of the amplification element. The inductance of the inductor is chosen so that, within a predetermined frequency range, a parallel resonance occurs with a parasitic capacitor of the amplification element and an intrinsic capacitor of the amplification element, the intrinsic capacitor being a base-collector capacitance or a gate-drain capacitance.

Abstract: An operational amplifier has a bias circuit, a differential amplifier, an output stage, and a feed forward circuit. The bias circuit provides a reference. The differential amplifier is coupled to a pair of input terminals and provides a differential output based on the first and second inputs. The output stage responds to the reference and to the differential output so as to supply a current to an output terminal. The feed forward circuit responds to the differential output in order to increase and decrease current to the output terminal. As a result, the feed forward circuit extends the dynamic range of the operational amplifier.

Abstract: An operational amplifier input stage provides a symmetrical rail-to-rail input common-mode voltage without turning off either pair of complementary differential input transistors. Secondary, or surrogate, transistor pairs assume the function of the complementary differential transistors. The circuit also maintains essentially constant transconductance, constant slew rate, and constant signal-path supply current as it provides rail-to-rail operation.

Abstract: A driving circuit for driving a capacitive load promptly to a target voltage is to have a broad dynamic range and achieve a high accuracy output and saving in the surface area with low power dissipation. A first period and a second period are provided in one data driving period. During the first period, a transistor amplifier for driving the load for charging, with a setting drive voltage (V1), and a transistor amplifier for driving the load for discharging, with a setting drive voltage (V2), with V1<V2, are both enabled for actuation and, during the second period, the transistor amplifier performing either the driving for charging or the driving for discharging, and a constant current source, performing the reverse of the operation of the transistor amplifier, are actuated, for driving the load to the target voltage.

Abstract: Among the embodiments of the present invention is an apparatus that includes a transistor, a servo device, and a current source. The servo device is operable to provide a common base mode of operation of the transistor by maintaining an approximately constant voltage level at the transistor base. The current source is operable to provide a bias current to the transistor. A first device provides an input signal to an electrical node positioned between the emitter of the transistor and the current source. A second device receives an output signal from the collector of the transistor.

Abstract: A system is provided for substantially reducing variation in AM to PM distortion of a power amplifier caused by variations in RF drive power and temperature. The system includes power control circuitry and power amplifier circuitry. The power amplifier circuitry includes an input amplifier stage and at least one additional amplifier stage coupled in series with the input amplifier stage. The power control circuitry provides a first supply voltage to the input amplifier stage based on a control signal such that the first supply voltage has a predetermined DC offset with respect to the control signal. The first supply voltage is provided such that the predetermined DC offset substantially reduces variations in the AM to PM distortion of the power amplifier due to variations in radio frequency (RF) drive power.

Abstract: A multistage analog circuit for independently controlling a bias current in each stage of the multistage analog circuit having an input stage, an intermediate stage, and an output stage, includes a first current source which controls the input stage of the circuit, a second current source which controls the intermediate stage of the circuit, and a third current source which controls the output stage of the circuit. The bias current in each stage of the circuit is set by the first, second, and third current sources. An output voltage of the circuit is capable of remaining the same when the first current source is changed to affect an input transconductance of the circuit.

Abstract: Variable gain amplifiers offering high frequency response with improved linearity and reduced power dissipation are provided. An amplifier is disclosed that is constructed from a one-stage topology with multiple signal paths and compensation networks for improved linearity and stable operation. In this amplifier, improved performance is obtained by replacing single transistor components with enhanced active devices which incorporate local negative feedback. One embodiment of the invention is a transconductance enhancement circuit that improves transconductance and input impedance relative to the prior art. A further development is an enhanced active cascode circuit that provides improved linearity. A high frequency bipolar transistor switch is also disclosed that incorporates lateral PNP transistors as high frequency switches with improved OFF-state to ON-state impedance ratio to realize a variable gain function.

Abstract: There is provided a current source circuit in which a outflow current of an output terminal is equal to an inflow current thereof. The current source circuit includes a first transistor group converting a reference current from a reference current source into a voltage and a first transistor having a current mirror relationship with the first transistor group, and allowing an output current to flow therethrough. An error amplifier compares a voltage generated in the first transistor group and supplied to one input terminal with a voltage supplied to the other input terminal. A second transistor is driven with an output voltage of the error amplifier. A third transistor is driven with the output voltage of the error amplifier, and allows an output current to flow therethrough in a direction opposite to the output current of the first transistor with respect to an output terminal.

Abstract: An apparatus and method that compensates for pre-distortion of a power amplifier includes a digital pre-distorter controller which generates a power/phase compensation coefficient, a temperature compensation coefficient and a frequency compensation coefficient, a look-up table which stores the coefficients, a pre-distorter kernel which pre-compensates an input signal based on the temperature compensation coefficient from the look-up table, and a correction filter which compensates an output signal of the kernel based on the frequency compensation coefficient from the look-up table. If desired, an input signal may be pre-distorted based on only one of the temperature and frequency compensation coefficients along with the power/phase compensation coefficient. Nonlinear characteristics of the power amplifier are accurately checked and distortion due to the nonlinear characteristics are compensated for.

Abstract: Pre-emphasis is given to differential output signals emanating from a pair of output nodes by initially (after an input data signal transition) connecting at least two current circuits to only one of the nodes. After a time delay, one of the current circuits is switched to connect only to the node to which the current circuits were not previously connected if there has been no further transition in the input data signal during the time delay. If only single-ended (i.e., non-differential) output is desired, only one of the output nodes is used as an output signal source. More than two current circuits may be used, and their switching from one node to the other may be performed progressively to provide pre-emphasis having any of many different characteristics.

Abstract: The invention provides robust and non-invasive calibration of an adaptive signal conditioning system having a signal conditioning block in the signal path to a signal conversion system, and a feedback path with a number of feedback components for enabling adaptation, by means of a parameter adaptation block, of the parameters used in the signal conditioning. In order to calibrate the feedback path, a well-defined reference signal is inserted into the feedback path, and an appropriate calibration coefficient is then determined by a coefficient calibrator in response to the received reference signal. The calibration coefficient is provided to a compensator, which effectively compensates for changes in the transfer characteristics of the feedback path due to factors such as variations in ambient temperature and component aging.

Abstract: An integrated circuit comprises a biasing circuit for maintaining the transconductance of a Gm cell constant. The integrated circuit comprises an on-chip constant voltage source and an on-chip constant current source. The on-chip constant current source has a connection for an external resistance, the value of the external resistance determining the current generated by the constant current source. The biasing circuit comprises means for providing a first fraction (?) of the current generated by the on-chip current source to bias the output of the Gm cell, and means for providing a second fraction (?) of the voltage generated by the on-chip voltage source to bias the input of the Gm cell. The transconductance of the Gm cell is controlled to be equal to the ratio of said fraction of the current generated by the on-chip current source to said fraction of the voltage generated by the on-chip voltage source.

Abstract: A signal processing integrated circuit has having a chopper stabilized, multistage, feedforward amplifier and a delta sigma analog to digital converter. Filtering of the output of the output from the analog to digital converter comprises a sinc5 filter and a sinc3 filter. The sinc3 filter may be bypassed. A rough buffer permits quick charging of a sample and hold capacitor during part of the charge cycle and slower but more accurate charging during the remainder of the charge cycle.

Abstract: A fully integrated charge amplifier with DC stabilization includes a first amplifier having an input terminal and an output terminal, a first capacitor coupled between the input terminal and the output terminal of the first amplifier, a transimpedance amplifier having an input terminal coupled to the output terminal of the first amplifier and an output terminal, and an impedance device coupled between the input terminal of the first amplifier and the output terminal of the second amplifier. The impedance device has a resistance of at least 1 M?.

Abstract: A transmission channel for a subscriber line interface circuit comprises a front end, tip/ring current-sensing transimpedance stage, containing relatively low valued tip and ring sense resistors coupled in circuit with tip and ring paths of a telecommunication wireline pair. The front end transimpedance stage transforms differential tip and ring input currents sensed by the tip and ring sense resistors into a single ended voltage, which is coupled to a transconductance amplifier filter/gain stage. The filter/gain stage is configured to provide a programmable output impedance, and converts the voltage from the current-sensing transimpedance stage into an output transmission voltage for application to a selected one of a current-sense, voltage-feed, or voltage-sense, voltage-feed telecommunication circuit.

Abstract: An apparatus and method for a sensing circuit for cancelling an offset voltage. Specifically, in one embodiment, a CMOS inverter amplifier amplifies an input signal present at an input node. A resistive feedback circuit is coupled to the CMOS inverter amplifier for cancelling an offset voltage that is associated with the CMOS inverter amplifier. This is accomplished by biasing the CMOS inverter amplifier to its threshold voltage. A bias circuit is coupled to the resistive feedback circuit for biasing MOSFET transistors in the resistive feedback circuit at a subthreshold conduction region. As such, the resistive feedback circuit presents a high impedance to the input node. A clamping circuit, coupled to the resistive feedback circuit, maintains operation of the transistors in the resistive feedback circuit in the subthreshold conduction region.

Abstract: A multi-stage integrator achieves a relatively high small-signal gain, broad bandwidth, and very clean transient pulse response. Only simple amplifying stages (typically including an inverting amplifier(s)) are used. A high gain amplifier is coupled between an integrator input node and amplifier output node. A broadband single stage amplifier (which may comprise or act as a transconductor), may act as a current source for the output transistor and load, coupled between the integrator input node and output node. Preferably, a capacitance is coupled from the integrator input to the amplifier output. A frequency-selective element or network steers signal components to the single stage amplifier or the integrator appropriately to produce a combined output that has the desired characteristics.

Abstract: A transmission of a signal through an isolation interface with a capacitive barrier is performed so that in an input circuit of the interface by integrating with an appropriate time constant the slope rates of the edges of signal replicas U1o± of the transmitted input signal Ui are adjusted and that the said signal replicas are differentiated either in an appropriate differentiating unit, whereat the time constants of these differentiating units are shorter than the rising and falling-off times of the signal replicas and are advantageously in the order of magnitude of 1 nanosecond or below. Therefore, in a circuit on the output side of the capacitive barrier no amplifier in front of voltage comparators is needed, which makes it possible that the pulse width is maintained extremely precisely. The data transmission is immune from the fast variation in the order of magnitude of 10 kV/&mgr;s of the potential difference between the voltage supplying sources for the input and the output circuits.

Abstract: An apparatus and method for a sensing circuit for cancelling an offset voltage. Specifically, in one embodiment, a CMOS inverter amplifier amplifies an input signal present at an input node. A resistive feedback circuit is coupled to the CMOS inverter amplifier for cancelling an offset voltage that is associated with the CMOS inverter amplifier. This is accomplished by biasing the CMOS inverter amplifier to its threshold voltage. A bias circuit is coupled to the resistive feedback circuit for biasing MOSFET transistors in the resistive feedback circuit at a subthreshold conduction region. As such, the resistive feedback circuit presents a high impedance to the input node. A clamping circuit, coupled to the resistive feedback circuit, maintains operation of the transistors in the resistive feedback circuit in the subthreshold conduction region.

Abstract: The present invention relates generally to electrical cascade circuits using normally-off junction field effect transistors (JFETs) which have low on-resistance for low voltage and high current density applications. Proper configuration of the normally-off JFETs allows for low voltage drop, low-on resistance, high current density and high frequency operations. More particularly, these cascade circuits are configured to provide amplification of an input signal and signal switching capabilities. In general two or more normally-off JFETs are coupled together on a substrate to create a desired characteristic. For a three terminal gate-controlled cascade amplification circuit, an input signal at the first JFET can realize a signal gain of 80 dB to 120 dB at the second JFET. A four terminal gate-controlled cascade switching circuit, comprised of two JFETs, switches on or off to regulate current flow through the second JFET.

Abstract: A method for affecting speed of transition of a closed loop circuit from an initial state to a steady state during a transition period; the closed loop circuit including a switching unit effecting the transition in response to a gating signal applied to a gate locus at a value greater than a predetermined threshold potential; includes the steps of: (a) at least one of: (1) clamping the gate locus at a minimum potential greater than ground potential and less than the predetermined threshold potential; and (2) increasing potential at the gate locus at a plurality of various rates during a plurality of segments of the transition period.

Abstract: A high slew rate operational amplifier circuit of which the through current of its push-pull transistors is substantially zero is disclosed. The operational amplifier circuit preferably comprises an amplifier portion and a push-pull output amplifier including NPN and PNP output transistors. The output of the amplifier portion is transferred to the NPN output transistors base through a PNP driving transistor and to the PNP output transistors base through an NPN driving transistor. The emitters of the driving transistors are connected to respective power supply conductors through respective current sources. The through current reduction is achieved by resistors inserted between the current sources and the corresponding power supply conductors, an NPN transistor so connected with the NPN output transistor as to constitute a current mirror and a PNP transistor so connected with the PNP output transistor as to constitute another current mirror.

Abstract: A radio frequency amplifier including a long tail pair of transistors provided with a tail current source. The bases of the transistors are driven by emitter follower transistor provided with collector load resistors. Feedback capacitors ensure stability and feedback resistors bias the amplifier without degrading noise performance. The amplifier may be driven unbalanced while retaining good second harmonic distortion performance.

Abstract: An amplifier utilizes feedback compensation to extend bandwidth. A feedback network is coupled between an output stage and an intermediate stage. One or more resistors in the feedback network can be arranged to compensate for Early voltage effects in one or more transistors in the intermediate stage. One or more capacitors in the feedback network can be arranged to cancel the junction capacitance of one or more transistors in the intermediate stage.

Abstract: Among the embodiments of the present invention is an apparatus that includes a transistor, a servo device, and a current source. The servo device is operable to provide a common base mode of operation of the transistor by maintaining an approximately constant voltage level at the transistor base. The current source is operable to provide a bias current to the transistor. A first device provides an input signal to an electrical node positioned between the emitter of the transistor and the current source. A second device receives an output signal from the collector of the transistor.

Abstract: A gain stage is disclosed. The gain stage comprises a first stage that provides two voltages of equal and opposites polarities and a plurality of devices cross coupled to the first stage. The plurality of devices minimize the Miller Effect capacitance in the differential stage by providing an out-of-phase signal to the first stage. Accordingly, a system and method in accordance with the present invention utilizes an at least one extra device on the same die as the first stage to provide an impedance match. In so doing, a broadband cancellation of the Miller Effect is achieved. Moreover, the matching is valid over an extended temperature range.

Abstract: It is intended to provide a DC offset cancel circuit capable of canceling DC offset regardless TDMA system and non-TDMA system, with simple circuit structure, and applicable to dual-mode-structured receivers. Out of output signals having at least two or more phases (OUT1, OUT2, . . . ), at least any one of the signals (OUT1, . . . ) is inputted to a phase converter unit. A signal outputted from the phase converter unit and any one of other signals not inputted to the phase converter unit (OUT 2, . . . ) are inputted to a comparator unit. A comparison result obtained at the comparator unit is fedback to a signal processing section and DC offset components are cancelled. Through the phase converter unit, phase of a signal is converted so as to make phases of signals to be compared same. Thereby, signal components of different phases are cancelled out each other and DC offset components as DC components can be compared.

Abstract: A system is provided for activating gain stages in an amplification module. The system includes an amplification module including a first group of amplifiers. Inverting output ports of each of the first group of amplifiers are coupled to a module inverting output terminal, and non-inverting output ports are coupled to a module non-inverting output terminal. A divider network is provided and is coupled to the input ports of the first group of amplifiers. A second group of amplifiers is also provided. Each amplifier of the second group corresponds to one of the amplifiers in the first group, has an inverting input port coupled to the second module inverting input terminal and to output ports of the divider network, and a non-inverting input port coupled to the second non-inverting input terminal.

Abstract: A limiter-amplifier device usable for burst mode communications. In one variation, the device includes a resistor bypassable via a switch, a capacitor, and a limiter-amplifier in series. In operation, in a first phase, the capacitor is discharged to ground via switches. In a second phase, the resistor is bypassed and the capacitor is charged while between the received signal and ground, via switching. In a third phase, in a fast tracking mode, the resistor is bypassed, and the capacitor is placed in series with the limiter-amplifier via switching, and in a slow tracking mode, the resistor is not bypassed, such that the resistor and capacitor are in series with the limiter-amplifier. In additional variations, the resistor is so placed such that less switching functions are needed to bypass the resistor, and additional resistors are optionally used in series with the switches to avoid exceeding current limitations for the switches.

Abstract: The present invention provides a CMOS transconductor circuit that features high frequency with high linearity, and the circuit includes an transistor. The source electrode of this output transistor is for receiving a current source. The gate electrode of this output transistor is for receiving another current source, and the drain electrode of this output transistor is for outputting current. Also included within the present invention is resistance that's coupled to the source electrode of the output transistor. A local negative feedback loop used as a negative feedback to connect the gate electrode of the output transistor to the source electrode itself, which makes the transconductance of this CMOS transconductor circuit to become the reciprocal of the resistance.