Abstract: A semiconductor device includes a bipolar transistor whose emitter-collector voltage is set to satisfy a condition IBE<ICB according to a voltage applied across a base and emitter where IBE is the base current flowing through a base-emitter path in a forward direction, and ICB is the base current flowing through a collector-base path in a reverse direction.

Abstract: The invention concerns a temperature level detection circuit including means (B1, B2, B3, 11, 12, 21, 31, 32) for generating diode voltages (VBE1 to VBE5) and calculating means including capacitive elements (51, 52, 53) and switching means (SW1 to SW4) arranged to connect selectively and sequentially, during first and second phases, the capacitive elements (51, 52, 53) to the means generating said diode voltages (VBE1 to VBE5). During the second phase, the calculating means generating a temperature signal representative of the temperature level being greater than or less than a determined temperature threshold (Tlimit) defined as the temperature value for which the equation &agr;1(VBE2−VBE1)+&agr;2(VBE3+&agr;3 (VBE5−VBE4)) becomes zero, where &agr;1, &agr;2, and &agr;3 are first, second and third proportionality coefficients determined by the values of the capacitive elements.

Abstract: The accumulation of a small positive charge on the source of a MOS switch which occurs after the switch has been turned off due to the parasitic capacitance that exists between the gate and the source of the transistor, known as clock feedthrough, is reduced by utilizing a split-gate MOS transistor, and by continuously biasing one of the gates of the split-gate transistor.

Abstract: A plurality of heterojunction bipolar transistors (HBTs), each including one or more HBT cells, are combined so as to drive all of the cells equally and involves coupling the input drive signal via a pair of microstrip transmission lines to the two farthest transistors having a first common circuit node therebetween. A third microstrip transmission line is located between the other two microstrip transmission lines and is connected from the first circuit node to a second circuit node which is common to the two nearer transistors in order to couple the drive signal in an opposite direction to the nearer transistors. In such an arrangement, a negative mutual inductance exists between the center transmission line and the two outer transmission lines. The microstrip transmission lines are designed with physical dimensions and mutual separation distances so that the total inductance of the transmission lines which exists between the circuit nodes equals the mutual inductance be therebetween.

Abstract: The present invention sets forth a new device comprising a PTC, and a transistor in direct physical contact with the PTC. The PTC has a first surface and a second surface wherein at least one of the surfaces is substantially flat. Preferably, the transistor comprises a MOSFET coupled to and located on a flat surface of one of the first and second surfaces of the PTC. The device further includes insulating material coupled to the PTC, a conductive pad coupled to the insulating material, and a conductor coupled between the conductive pad and a gate junction of the transistor. A similar conductive pad and conductor arrangement is provided for a source junction of the transistor. The MOSFET is coupled at a drain junction thereof to one of the first and second surfaces of the PTC, and the device includes a non-conductive encapsulating material around at least a portion of the transistor and the PTC. The combined PTC/MOSFET device provides switching and overload protection features.

Abstract: This invention relates to a process for controlling at least one IGBT type transistor enabling its operation under irradiation, in which the value of the threshold value Vge.sub.s of the gate-emitter voltage of a first IGBT transistor (30) under irradiation is measured, and the voltage applied between the gate and the emitter of at least one second IGBT transistor under irradiation is varied during operation, so as to slave the threshold voltage Vge.sub.s of this (these) IGBT transistor(s) to a set value despite the drift caused by irradiation.

Abstract: A rectifying device comprising of a SRMOS, an inductor, and a control circuit is disclosed. The SRMOS has a gate, a drain, and a source. The gate of the SRMOS is connected to the output of the control circuit. The inductor is connected to the drain of the SRMOS. The control circuit uses two sense traces for determining the voltage (or current) passing between the inductor (that is connected to the drain) and the source of the SRMOS. Upon sensing a forward characteristic (voltage or current), the SRMOS forward biases to allow current to flow through the SRMOS. Upon sensing a reverse characteristic (voltage or current), the SRMOS reverse biases to cut off any current flow. Hysteresis is used in setting the forward biasing threshold voltage and the reverse biasing threshold voltage for the SRMOS. In reverse biasing and forward biasing the SRMOS, V.sub.gs is stepped (or curved) controlled to avoid false turn ON/OFF of the SRMOS.

Abstract: A method of designing improved CMOS input circuits by understanding and selecting appropriate drive strength for a CMOS output from a previous stage. The method involves modeling the net using HSPICE and including a transit time term to accurately model charge storage, then size drivers as needed to keep the V.sub.ss clamps out of forward conduction. Excessive ringing can cause data errors in the input stage if unterminated, falling edge transitions in such a net can turn on a receiver's V.sub.ss clamp diode (stored charge in the V.sub.ss clamp diode combined with the line's inductance and the receiver's capacitance form an energized resonant circuit which can release energy at a time to cause a data glitch). Currently, XNS simulation miscalculates the ring amplitude by a factor of three. Driver scaling and termination can eliminate the problem by keeping the receiver's V.sub.ss clamp out of forward conduction. Driver sizing can control the problem.

Abstract: A integrated circuit, high impedance, current source/sink for wireless communications systems comprising one or more inverted bipolar junction transistors, and a method of ensuring high output impedance at RF frequencies. Mixers, differential amplifiers and transconductance amplifiers are disclosed as is the physical structure of bipolar transistors including heterojunction transistors.

Abstract: A power transistor (11) having a control electrode (16), a first electrode (17), a second electrode (181), and a kelvin electrode (19) is provided. The power transistor (11) comprises a plurality of transistors (12-15) coupled in parallel. Each transistor having a control electrode, a first electrode, and a second electrode coupled respectively to the control electrode (16) , first electrode (17) , and second electrode (18) of the power transistor (11). A plurality of first resistors (26-29) reduce oscillation and ringing, each first resistor is coupled between the kelvin electrode (19) and a second electrode of a transistor of the plurality of transistors (12-15). A plurality of second resistors (21-24) also reduces oscillation and ringing, each second resistor is coupled between the control electrode (16) and a control electrode of a transistor of the plurality of transistors (12-15).