Abstract: A fast, accurate, low offset comparator may be configured with multiple gain stages. A low gain, low input impedance, and fully differential common-gate amplifier may be configured as a first stage in the multi-stage comparator, providing a wide bandwidth for small power consumption. The inputs of the comparator may comprise a pair of differential inputs at respective source terminals of gate-coupled metal oxide semiconductor (MOS) devices configured in the input stage of the common-gate amplifier. A pair of differential outputs of the first stage may be coupled to a pair of differential inputs of a second stage, which may be a differential input current-mirror amplifier that may perform differential to single-ended conversion.

Abstract: A system to evaluate a voltage in a charge pump may include a transistor, and a transistor drain carried by the transistor with the transistor drain receiving a reference current. The system may also include a transistor gate carried by the transistor and connected to the transistor drain. The system may further include an additional transistor and an additional transistor gate carried by the additional transistor and connected to the transistor gate. The system may additionally include an additional transistor drain to receive the reference current mirrored from the additional transistor.

Abstract: The LVDS receiver circuit comprises a differential-input transistor pair, a control transistor pair, a current-mirror-load circuit, a first feedback inverter and a second feedback inverter. The first feedback inverter, the second feedback inverter and the control transistor pair constitute a feedback loop. The voltage change of the input voltage of the first feedback inverter is suppressed, and the input voltage is controlled around the threshold voltage of the first feedback inverter.

Abstract: Method and apparatus are provided for fast rail-to-rail voltage comparison. A rail-to-rail voltage comparator for indicating one of two states with an output signal in response to an input signal is provided comprising an input stage having an input configured to receive the input signal and having an output, and an amplification circuit having an input coupled to the output of the input stage. The input stage comprises a first differential amplifier having a first input-voltage range and configured to produce a first current based on the input signal, a second differential amplifier having a second input-voltage range and configured to produce a second current based on the input signal, and a summing circuit having a first input coupled to the first differential amplifier and having a second input coupled to the second differential amplifier. The first input-voltage range overlaps the second input-voltage range.

Abstract: A voltage comparator where the difference of currents from transistors is converted into voltage, which is amplified and conducted to a gate terminal of a switching transistor. A source of a limiting transistor is connected to the gate terminal. The voltage at the gate terminal when the switching transistor is quiescent is equal to a value between eight and nine tenths of the switching voltage at the gate of the transistor, at which voltage the transistor triggers a switching in the output stage. A response to an input voltage change at one direction of the sign reversal of the difference of the input voltages is fast. The voltage comparator is robust and reliable with regard to temperature variations.

Abstract: Methods and apparatus for properly biasing differential comparators are provided. Using a feedback relationship, a bias for a main stage that receives a first differential input of the comparator is produced. Separately, a feedback relationship produces a bias for a main stage that receives a second differential input. These biases, produced as a result of the feedback relationship between bias stages and stages that replicate the main stages, are applied to the main stages. The outputs of the differential comparator are differential outputs with improved common-mode rejection as a result of the feedback and replica biasing.

Abstract: A current control circuit is coupled in parallel with the current paths of a differential comparator circuit to ensure that a substantially constant current is drawn from a current source during all operating phases of a comparator. The current control circuit is biased by a reference voltage, which is also used to bias a V? input terminal of the differential comparator circuit. The reference voltage is stored by a sample capacitor, which is charged by applying the reference voltage to a V+ input terminal of the differential comparator circuit while coupling an output terminal of the differential comparator circuit to the sample capacitor in a unity feedback configuration.

Abstract: An input circuit comprising a level-determining unit and an output unit is provided. In a first period controlled by a first enable signal, the level-determining unit receives an input signal at an input terminal of the input circuit and determines a voltage level of the input signal. The output unit is coupled to the input terminal. In the first period, the output unit outputs the input signal with the determined voltage level at an output terminal of the input circuit to serve as an output signal. In a second period following the first period, the output unit latches the determined voltage level of the input signal according to a second enable signal and outputs the input signal with the determined voltage level at the output terminal to serve as the output signal.

Abstract: A current mirror includes at least a first and a second mirror transistors inserted between a first and a second voltage reference and connected to an input terminal and to an output terminal of the current mirror, respectively. The current mirror further includes a base current compensation block inserted between the input terminal and common control terminals of the first and second mirror transistors and connected to a voltage reference. The base current compensation block at least includes a bias current generator of a bias current and a first compensation transistor inserted, in series to each other, between the voltage reference and the input terminal, and a second compensation transistor inserted between the voltage reference and the common control terminals of the mirror transistors and having a control terminal connected to a control terminal of the first compensation transistor.

Abstract: Embodiments of the invention relate to a signal receiver inserted between a first and a second voltage reference and having a first and a second input terminal effective to receive differential signals and an output terminal effective to provide a converted signal. Advantageously, the signal receiver according to embodiments of the invention comprises a conversion stage inserted between the first and second voltage references and connected between the first and second input terminals of the signal receiver and an input terminal of an hysteresis comparator, connected in turn to the output terminal of the signal receiver. In particular, the conversion stage performs a conversion from any input signal received on respective input terminals to an intermediate signal provided on an output terminal and suitable for reception by the hysteresis comparator.

Abstract: A comparator includes a differential pair of transistors providing a first amplification stage and receiving inverting and non-inverting input signals. An output transistor is coupled to the differential pair of transistors providing a second amplification stage and transitioning the output signal state when the non-inverting input signal is larger than the inverting input signal. The output node of one of the differential pair of transistors is connected to an input node of a current-tail transistor. The output node of the other differential transistor is connected to an input node of the output transistor. The other nodes of the differential pair of transistors are connected to each other and are coupled to an output node of the current-tail transistor. The output nodes of the differential pair of transistors and an output node of the output transistor are each coupled to a separate current generator that may include a complex impedance element.

Abstract: A comparator, comprising at least one current stage for providing a first current proportional to a difference between first and second comparator inputs, the first current being provided to an amplifier input; an amplifier for amplifying a current provided to the amplifier input and providing a comparator output; apparatus for introducing hysteresis, comprising at least one of a current source and a current sink, the current source being arranged to selectively source a source current to the amplifier input such that the comparator output changes from a first state to a second state when a difference between the first and second inputs rises above a first value, and the current sink being arranged to selectively sink a sink current from the amplifier input such that the comparator output changes from the second state to the first state when the difference between the first and second inputs falls below a second value; and apparatus for controlling at least one of the source current and the sink current to be

Abstract: There is provided a differential signal comparator which maintains the duty ratio of complementary input signals. The differential signal comparator includes differential amplifier circuits 1 and 2 receiving complementary input signals, a plurality of current amplifier circuits 3 to 6 for amplifying current output from the differential amplifier circuits and a current arithmetic operation circuit 7 for an arithmetic operation of an output from the plurality of current amplifier circuits 3 to 6 at the time of converting the differential signal between the complementary input signals into a voltage of CMOS level, wherein a capacitive load of an output of the differential amplifier circuit is constant independent of a level of the input signals. A voltage signal which is current-voltage converted to a complementary CMOS level signal is input into a differential comparator to obtain a single end CMOS level signal.

Abstract: A self-biasing slicer includes a self-biased differential transistor pair. As a result of the self-biasing, the slicer may receive input signals without the use of AC coupling. That is, a differential input signal may be fed directly to the inputs of the differential transistor pair. The differential pair circuit may incorporate a self-biased load and a self-biased current source. The slicer also may include a matched output stage with inverters that provide a rail-to-rail output. Here, the inverters may incorporate components that are matched with components of the differential pair.

Abstract: A current mirror circuit includes a pair of first and second transistors having bases connected together and emitters connected to a power line, a resistor connected between the bases of the first and second transistors and the power line, a third transistor for providing base currents of the first and second transistors and a resistor current flowing through the resistor, and a current compensation circuit that adds a compensation current to an input current to the first transistor. The amount of the compensation current is approximately equal to that of the resistor current divided by a current gain of the third transistor. Thus, the compensation current compensates the difference between a collector current of the first transistor and the input current.

Abstract: Methods and systems are provided for comparing currents. The method includes driving a first current through a first X leg of a first current conveyor circuit and a second current through a second X leg of a second current conveyor circuit. The method further includes draining a third current from a first X terminal of the first current conveyor circuit to produce a first positive transistor current and a first negative transistor current, and draining a fourth current from a second X terminal of the second current conveyor circuit to produce a second positive transistor current and a second negative transistor current. The method further includes summing the first positive transistor current and the second negative transistor current to produce a first current output, the first negative transistor current and the second positive transistor current to produce a second current output, and the first current output and the second current output to produce a summed current output.

Abstract: A voltage comparator contains low voltage devices (e.g., bipolar or MOS transistors) and high voltage devices (e.g., DMOS transistors). The low voltage devices, which cannot sustain a voltage greater than a relatively small range of variation that is substantially less than the range of potential variation of the input voltage, are connected in a differential amplifier configuration to perform precision differential measurements on the input voltage. The high voltage devices are interconnected with the low voltage devices in a manner that enables operating levels of the low voltage devices to move up/down, or ‘slide’, with variations in the input voltage, so that the low voltage devices are effectively immune to high levels of the input voltage.

Abstract: Differential peak detection for outputting a signal indicative of a peak value of an input signal. The input signal is differentially amplified using common mode feedback and a common mode output is thereby output, wherein common mode level of the common mode output is substantially the same as a common mode voltage. The common mode output of such differential amplification is coupled to an input of a first common source input pair, and the common mode voltage and a feedback from the output signal across a sampling capacitor is coupled to an input of a second common source input pair. A summation of respective outputs of the first and second common source input pairs is coupled to an input of a transconductance stage, wherein an output of the transconductance stage controls charging of the sampling capacitor. In this manner, a more accurate output signal is provided.

Abstract: A current mirror circuit includes p-type MOS (PMOS) transistors, whereby the current flowing when the input voltage is “H” is interrupted when an output node of the current mirror circuit goes from “L” to “H,” so that a cascode-connected PMOS transistor within the current mirror circuit is automatically turned OFF. The gates of PMOS transistors within the current mirror circuit are connected by a signal line directly to the output node. The rise time of the output voltage of the current mirror circuit and the consumption current can thus be reduced.

Abstract: A voltage comparator circuit is composed of a differential amplifier circuit receiving a pair of input signals to develop an output signal on an output terminal, and a waveform shaping circuit connected to the output terminal.

Abstract: A fast, accurate, low offset comparator may be configured with multiple gain stages. A low gain, low input impedance, and fully differential common-gate amplifier may be configured as a first stage in the multi-stage comparator, providing a wide bandwidth for small power consumption. The inputs of the comparator may comprise a pair of differential inputs at respective source terminals of gate-coupled metal oxide semiconductor (MOS) devices configured in the input stage of the common-gate amplifier. A pair of differential outputs of the first stage may be coupled to a pair of differential inputs of a second stage, which may be a differential input current-mirror amplifier that may perform differential to single-ended conversion.

Abstract: A VCO buffer circuit comprising a first loading means receiving a first signal for loading the VCO at a first input node; a second loading means receiving a second signal for loading the VCO at a second input node; a third loading means coupled to said first loading means for loading the VCO at third input node to thereby balance a load distribution on three nodes of VCO. At least three current controlling means are coupled to each other to form a symmetrical configuration and receive input signals from said first and second loading means for minimizing variations in the oscillation frequency of the VCO. A buffering means is connected to the output of the controlling means for buffering the output of the current controlling means.

Abstract: A comparator (12A,12B) includes a first differential input stage (10) including first (MN2) and second (MN3) input transistors and a load (MP9,MP10), the first input transistor (MN2) having a gate, source, and drain coupled to a first input voltage (Vin?), a first tail current source, and the load, respectively. The second input transistor has a gate and source coupled to a second input voltage (Vin+) and a first tail current source. A second differential input stage (11) includes a third (MN4) and fourth (MN5) input transistors, the third input transistor having a gate and source coupled to a first reference voltage (Vref+) and the second tail current source, respectively. The fourth input transistor (MN5) has a gate and a source coupled to a second reference voltage (Vref?) and the second tail current source, respectively. Drains of the third and fourth input transistors are coupled to the load.

Abstract: A regulated mirror current source circuit has an output transistor, a regulator for controlling the output circuit, and a current mirror having two or more current paths. The first path of the mirror is coupled in series with a current path of the output circuit, and the second path is coupled to the regulator, to provide feedback. The feedback can provide better precision, or reduced component area. The circuit can include cascode transistors, and the regulator can have integral control. The output transistor gate-source voltage is overdriven to reduce “on” resistance of the output transistor. When the output transistor is a high voltage transistor, its area can be reduced without sacrificing compliance.

Abstract: A current mirror circuit includes a pair of first and second transistors having bases connected together and emitters connected to a power line, a resistor connected between the bases of the first and second transistors and the power line, a third transistor for providing base currents of the first and second transistors and a resistor current flowing through the resistor, and a current compensation circuit that adds a compensation current to an input current to the first transistor. The amount of the compensation current is approximately equal to that of the resistor current divided by a current gain of the third transistor. Thus, the compensation current compensates the difference between a collector current of the first transistor and the input current.

Abstract: A comparator circuit includes a differential amplifier circuit, a latch circuit, and a control signal generating circuit. The latch circuit includes a pair of cross-coupled inverting amplifiers that pull the output signals of the differential amplifier to the high and low logic levels, a control transistor that activates the latch circuit in synchronization with a clock signal, and an equalizing transistor that equalizes the output signals when the latch circuit is inactive. The equalizing transistor is switched on and off by a control signal generated from the clock signal by the control signal generating circuit. The high-level potential of the control signal is lower than the high-level potential of the clock signal. Switching noise at the control electrode of the equalizing transistor is therefore reduced, permitting high-speed operation.

Abstract: The invention relates to a sense amplifier comprising the following element: a first current mirror unit coupled to a high voltage source, outputting a first current and a second current according to a first reference current, wherein the second current is twice the first current; a second current mirror unit coupled to a high voltage source, outputting a third current according to a second reference current; a first impedor coupled to the second current and a low voltage source; a second impedor coupled to the third current and a low voltage source; a third current mirror coupled to the first, second and third currents, and the first current is regarded as the reference current of the third current mirror unit, thus, the current which flows through the first impedor is the first current, and the current which flows through the second impedor is a fourth current.

Abstract: Methods and apparatus for properly biasing differential comparators are provided. Using a feedback relationship, a bias for a main stage that receives a first differential input of the comparator is produced. Separately, a feedback relationship produces a bias for a main stage that receives a second differential input. These biases, produced as a result of the feedback relationship between bias stages and stages that replicate the main stages, are applied to the main stages. The outputs of the differential comparator are differential outputs with improved common-mode rejection as a result of the feedback and replica biasing.

Abstract: A current source apparatus includes a first MOS transistor having a drain serving as current input terminals with the gate connected to the drain, a first switch connected to the source of the first MOS transistor, a second MOS transistor having a drain serving as a current output terminal, a second switch connected to the source of the second MOS transistor, a third switch having one end connected to the gate of the first MOS transistor, and the other end connected to the gate of the second MOS transistor, and a drive circuit which controls the second switch and the third switch.

Abstract: An electric circuit for providing a selection signal being used to select a control value of a control variable which oscillates, at steady state, about a reference value about a first control value and a second control value with a first period duration comprises a first differential circuit which provides a first current being dependent on a difference between the first control value and the reference value. The electric circuit further comprises a second differential circuit which provides a second current being dependent on a difference between the reference value and the second value and a first node at which a differential current between the first current and the second current is formed. The differential current forms the selection signal indicating if the first control value or the second value is to be selected in order to minimize a difference between the reference signal and control variable.

Abstract: An integrated CMOS circuit with a differential open drain output driver comprises a plurality of differential output stages each having differential inputs and differential outputs, the differential outputs of the differential output stages being interconnected to provide a pair of differential open drain driver outputs, and the differential inputs of the differential output stages being driven by a pair of inverter chains each of which has an input receiving one of a pair of differential input signals and cascaded inverter stages each with an output connected to an input of one of the differential output stages.

Abstract: A comparator has first and second current paths, each passing from an input through a transistor, through a current source to ground, the second current path also having a reference voltage drop element coupled in series with the second input. The gates of the transistors are coupled to form a current mirror. The reference voltage drop element enables higher voltages to be input and compared to higher thresholds above an internal supply voltage level without the need for dividing resistors to reduce the input voltage. Avoiding such resistors means the power dissipation and the silicon area used can be kept lower. ESD vulnerability is reduced since the inputs are not coupled to gates of MOS transistors. Overvoltage protection across the source and gate of the second transistor can be added.

Abstract: A comparator circuit with reduced current consumption, and other circuits utilizing the same, are provided. The comparator circuit may achieve reduced current consumption by preventing current flow via a switching transistors responsive to the voltage level of the input signal.

Abstract: A circuit and a method are provided to produce a novel comparator with Schmitt trigger hysteresis character. The circuit includes a current source which controls the magnitude of current flow through this comparator circuit. It has a first logic device which is turned ON by a reference voltage, and a second logic device is turned ON by a comparator input voltage. A first feedback device is turned ON by a negative comparator output. A first parallel resistor is connected in parallel to the first feedback device. A second feedback device is turned ON by a positive comparator output. A second parallel resistor is connected in parallel to the second feedback device. The first and second parallel resistors are used to provide the differential comparator with switching voltage offsets which result in the Schmitt trigger hysteresis character.

Abstract: A semiconductor integrated circuit has: a differential amplifier circuit including a first MOS transistor connected between a first node and a common node and a second MOS transistor connected between a second node and the common node; a first current supply circuit configured to supply current to the first node; and a second current supply circuit configured to supply current to the second node. A current supply ability of the first current supply circuit is variable.

Abstract: An integrated circuit comparator comprises a differential amplifier, a source follower circuit coupled to a gate terminal of a first transistor in the differential amplifier, and an output circuit. One or more source follower circuits may be utilized in connection with the differential amplifier, and one or more source follower circuits may be utilized in connection with the output circuit.

Abstract: A method for dynamically adapting the biasing current for a fast switching CMOS comparator is achieved. The difference of the two input signals of said comparator controls the comparator's biasing current, where the biasing current is high only when the difference is low and the comparator's switching is likely to happen and where the biasing current is kept low at other times. In a current mirroring circuit, the voltage difference at the comparator inputs controls the mirroring ratio. The biasing current reaches its maximum when the input voltage difference approaches zero. Once the input voltage difference crosses zero and continues to change in the same direction as before, that is after the polarity of the voltage difference changed, the control mechanism alternates the connection of the comparator input signals to the current controlling elements, in order to now reduce the current with a further increase of the voltage difference.

Abstract: A transconductance stage is provided. The transconductance stage includes a tail current source, a differential pair, and two current mirrors. The input to each of the current mirrors is connected to the drain of a separate one of the transistors in the differential pair. The two current mirrors each have two outputs so that one of the outputs can be used to determine whether the output current exceeds a threshold (e.g. nine-tenths of the tail current). If the source current exceeds the threshold, extra source current is switched in to the output so that output source current is increased. Similarly, if the sink current exceeds the threshold, extra sink current is switched in to the output so that the output sink current is increased. This way, the transconductance stage can supply large output currents in response to a large signal input but maintains low quiescent current for small input signals.

Abstract: A comparator circuit having improved operational characteristics. A predetermined voltage drop device is provided, such as an exemplary embodiment Schottky diode, having an anode connected to circuit power supply voltage and an output stage of the comparator and a cathode connected to an input stage of the comparator. The predetermined voltage drop device effects a lowering of the power supply voltage for the output stage bias between said power supply voltage and said common voltage. This reduces the required swing of the output stage drivers during a comparator input signal transition and reduces propagation delay of said comparator.

Abstract: An operational amplifier has a bias circuit, a differential amplifier, an output stage, and a feed forward circuit. The bias circuit provides a reference. The differential amplifier is coupled to a pair of input terminals and provides a differential output based on the first and second inputs. The output stage responds to the reference and to the differential output so as to supply a current to an output terminal. The feed forward circuit responds to the differential output in order to increase and decrease current to the output terminal. As a result, the feed forward circuit extends the dynamic range of the operational amplifier.

Abstract: A differential amplifier is configured to receive an input signal whose magnitude is referenced between a reference voltage and a first power supply magnitude. A differential current conducted by the differential amplifier induces current to be conducted by a first current mirror, which in turn induces current to be conducted by a second current mirror. The current conducted by the second current mirror produces an output signal that is referenced between the reference voltage and a second power supply magnitude.

Abstract: Comparator systems are provided that include cross-coupled transistors which respond to a differential network that receives an input signal. The systems further include a control transistor connected across the cross-coupled transistors and a bias network configured to apply a bias voltage to the control transistor that is substantially the voltage across two transistors which are each biased into saturation. It has been found that this bias during the systems' acquire phase substantially stabilizes the systems' gain over variations in their total environment and that this stabilization enhances the systems' performance.

Abstract: Circuit for providing drive signal waveforms. The circuit includes a current mode logic (CML) driver that includes a common mode voltage (VCM), an output node and a complementary output node. The circuit also has a level shifting mechanism that is coupled to the CML driver. The level shifting mechanism adjusts the common mode voltage (VCM) by either drawing a level shifting current from the output node and the complementary output node or injecting a level shifting current into the output node and the complementary output node.

Abstract: A voltage monitor circuit for biasing a well region of a CMOS circuit includes a self-biased comparator which compares first (INP) and second (INN) input signals. The comparator includes first (MN1) and second (MN2) N-channel transistors with grounded sources, a drain of the first N-channel transistor and a gate of the second N-channel transistor being coupled to a first output (OUTN), and a drain of the second N-channel transistor and a gate of the first N-channel transistor being coupled to a second output (OUTP). First (MP1) and second (MP2) P-channel transistors are operated to couple the second or first input signal to the second or first output, respectively, by controlling the gate-to-source voltage of the first or second P-channel transistor according to the polarity of a voltage difference between the first and second input signals.

Abstract: The present invention provides a current mirror circuit of which consistency (ratio) of the input current and output current is more improved. This current mirror circuit comprises input side and output side bi-polar transistors of which bases are commonly connected, an input side MOS transistor of which source is connected to a collector of the input side bi-polar transistor and of which drain and gate are connected to the input terminal, output side MOS transistors of which source is connected to the collectors of the output side bi-polar transistors, of which drain is connected to the output terminals, and of which gate is connected to the gate of the input side MOS transistor, and an MOS transistor for supplying base current of which source is connected to the bases of the input side and output side bi-polar transistors, and of which gate is connected to the gate of the input side MOS transistor.

Abstract: A high gain, highly linear mixer includes an input section, mixing section, at least one tuning component, and at least one stand by current source. The input section is operably coupled to receive an input voltage signal and perform a linear transconductance thereon to produce an input current signal. The mixing section is operably coupled to mix a local oscillation with the input current to produce a mixed current signal. The tuning component is operably coupled to the mixing section and to convert the mixed current signal into a mixed voltage signal that function as the output of the mixer. The standby current source is operably coupled to the mixing section and provides a standby current to the mixing section.

Abstract: According to one embodiment, an integrated fault detector circuit is used to detect one or more of the open circuit and short circuit of a load connected to an integrated circuit power MOSFET driver by directly detecting the level of current flowing in a floating current source.

Abstract: A driver circuit that allows high-speed switching when the reference current (I) is small. The driver circuit includes a drive current generation circuit (220) for supplying to a first node (232) a drive current based on a binary data signal (DATA); a current mirror circuit (240) for conducting through a second node (234) a current (mI) having a magnitude of the current flowing through the first node (232), multiplied by a predetermined current mirror ratio (m); and a pre-bias circuit (260) for supplying a first pre-bias current (Ib1) to the first node (232) and supplying a second pre-bias current (Ib2) having a magnitude of the first pre-bias current (Ib1), multiplied by said current mirror ratio (m), to the second node (234).

Abstract: A comparator includes a circuit which provides a plurality of common-mode difference signals in response to differential input signals. The circuit provides a common-mode feedback signal in response to the plurality of common-mode difference signals. The common-mode feedback signal is used to drive the common-mode level of an amplifier to a desired value.

Abstract: A dynamic current generator 30 is disclosed in which a common-mode input range is provided which is asymmetric toward the bottom rail VEE. An embodiment of the invention is also disclosed used in an asymmetrical dynamically biased amplifier system 34.