Abstract: A precision bias is provided for a differential transconductor. The precision bias includes a bias circuit, a differential amplifier and a current mirror. The current mirror includes at least two mirror transistors, one of which is connected to the bias circuit, and th other of which is connected to the differential amplifier. The bias circuit provides a bias current, which the current mirror accurately reflects to the differential amplifier as a tail current. By providing identical operating conditions to the bias circuit and first mirror transistor as are seen at the differential amplifier and second mirror transistor, the precision bias can more accurately reflect the bias current into the tail current. This can reduce the DC output currents of the differential amplifier to substantially zero, which improves its performance. A second bias circuit provides the gate-source voltage of the two transistors forming the load of the differential transconductor.

Abstract: A cross coupled output stage for a transmitter. It is desirable to have high impedance for a differential cascode output stage of an externally terminated transmitter in order to improve return loss. However, at high frequencies, parasitic capacitances cause shunts at the output nodes due to drain to bulk capacitances and negative feedback loops due to gate-to-drain capacitance. In order to counteract this, cross coupled capacitors are connected to the circuit to cause a positive feedback loop. This counteracts the reduction in impedance causing the impedance to remain high over all frequencies and to improve the return loss.

Abstract: A differential output circuit is composed of a constant-current circuit section having a reference voltage circuit, an amplification circuit, a resistance, an N-channel MOS transistor and a P-channel MOS transistor; a mirror circuit section having three P-channel MOS transistors; a data transmission switch circuit section having a data input terminal, an inverter circuit, positive and negative output terminals, and two N-channel MOS transistors; and an offset level adjusting circuit section having a resistance.

Abstract: A device for comparing two input signals includes a first comparator with differential outputs to whose inputs the signals are applied. The first comparator is followed by a second comparator delivering an output logic signal of the device. Each comparator includes at least one input differential stage, and each stage has two arms biased by a bias current generator. The comparison device may also include at least one additional current supply circuit associated with an arm of the input differential stage of the first comparator to copy the current of the arm and add it, with a multiplier factor, to the bias current of the input differential stage of the second comparator. This facilitates a corresponding switch-over.

Abstract: A power on reset (POR) circuit in a semiconductor device which is process independent and resistant to noise present in a power supply voltage when the power supply voltage has not yet obtained a predetermined operational voltage level. The POR circuit includes a differential amplifier, a non-inverting input control circuit and an inverting input control circuit. The differential amplifier senses and amplifies a difference in voltage between the non-inverting input terminal and the inverting input terminal. The non-inverting input control circuit controls a voltage of the non-inverting input terminal of the differential amplifier. The inverting input control circuit controls a voltage of the inverting input terminal of the differential amplifier.

Abstract: A class AB buffer (or amplifier) is disclosed for driving a large capacitive load. The disclosed CMOS class AB buffer can drive capacitive loads, for example, in excess of 100 pF, while operating from a voltage supply as low as 1.5 volts. The disclosed class AB buffer includes a pair of driving transistors that are cross-coupled through an amplifier and level shifting circuitry, such as transistor circuitry, and a pair of current source transistors each having a gate terminal connected to an output of the corresponding amplifier and a gate terminal of an output transistor, and a drain terminal connected to a source terminal of the driving transistors. The driving transistors are prevented from entering a linear region by connecting a drain terminal of each of the driving transistors to a positive power supply voltage. The threshold voltage of only one transistor must be overcome before the transistors conduct current, since the gate-sources of the driving and current source transistors are not in series.

Abstract: Integrated circuit memory devices according to the present invention include a current sense amplifier having first and second cross-coupled sensing transistors. First and second data lines are electrically coupled to the source of the first sensing transistor and the source of the second sensing transistor, respectively. The current sense amplifier includes a first load transistor that has a source electrically connected to a drain of the first sensing transistor and a gate of the second sensing transistor and a second load transistor is included that has a source electrically connected to a drain of the second sensing transistor and a gate of the first sensing transistor. A switching transistor is responsive to an enable signal and has a source electrically coupled to a drain of the first load transistor and a drain of said second load transistor. A first load circuit provides a variable impedance across the source and the drain of the first load transistor in response to at least a first sense signal.

Abstract: A control circuit for a power MOSFET includes a voltage divider for dividing an input voltage, a fixed voltage generator for generating a fixed voltage, a comparator having a differential pair including first and second depletion transistors each receiving the divided voltage or the fixed voltage and a current mirror including first and second enhancement transistors connected in series with the first and second depletion transistors, respectively, an inverter for receiving the output from the comparator, and a power MOSFET controlled for the ON/OFF control thereof by the inverter.

Abstract: A resistorless offset comparator is provided. The comparator includes a differential stage having a first input and a second input, an output stage in which the output is zero when the two inputs have therebetween a specific voltage difference, and a biasing stage providing a first biasing voltage and a second biasing voltage for respectively creating a second input voltage and a first input voltage respectively in the second and first inputs such that the two input voltages have therebetween the specific voltage difference. A method for forming the same includes steps of a) providing the differential stage, b) providing the output stage and c) providing the biasing stage which has a characteristic dependent on a manufacturing parameter such that the specific voltage difference is independent of the manufacturing parameter.

Abstract: A comparing detector circuit capable of operating regardless of input voltages thereto includes a first pair of transistors to which first and second input signal voltages are input for functioning as a buffer; a second pair of transistors constructing a current mirror circuit in which an input side and an output side are connected to the first pair of transistors via first and second resistors, respectively; and an output transistor to which potential at the output side of the current mirror circuit is applied as an input.

Abstract: A rectifier circuit is described, which comprises an arrangement of a first, a second and a third transistor, emitters of said transistors being coupled together at a first junction point and to a terminal of a first constant current source and in which arrangement collectors of the first and the second transistor are coupled together at a second junction point, a current mirror arrangement having a predetermined mirror ratio, an input of said current mirror being coupled to the second junction point and an output of said current mirror being coupled to a collector of the third transistor at a third junction point, wherein an input voltage, by which the collector-emitter currents of the first and/or the second transistor are controllable, can be supplied to the rectifier circuit bia bases of the first and/or the second transistor, while an output voltage can be taken from the base of the third transistor of the rectifier circuit and the output voltage at least substantially corresponds to the rectified input

Abstract: There is disclosed a level shift circuit which has a differential input, for receiving input signals, and a differential output, for supplying output signals derived from the input signals. The level shift circuit further includes a control level setting input, and a feedback circuit for setting a common mode level of the output signals to a level set on the control level setting input. This allows the output common mode to be set accurately, independently of the input common mode.

Abstract: A differential input circuit which can positively operate over a wide input range is provided. The differential input circuit includes a first constant current source of a current mirror type which generates a positive current and a second constant current source of a current mirror type which generates a negative current. The first and second constant current sources constitute a differential amplifier circuit. A current switch which is connected to a positive input and a negative input is also connected to said first and second constant current sources so that an operating point of the differential amplifier circuit can be changed.

Abstract: A sense-amplifier circuit for a multivalued information storing memory is featured by a reduced current consumption realized without any elongation of delay time, which circuit comprises plural current-mirror sub-sense-amplifiers corresponding to plural reference potentials VREF, wherein those having higher reference potentials among the sub-sense-amplifiers are provided each with a current-limiting switching element QNX.

Abstract: A line receiver circuit for receiving differential digital signals from a symmetrical transmission line comprises a first differential input stage (1) adapted to receive and process differential signals having a common mode voltage within a first common mode voltage range, and a second differential input stage (2) adapted to receive and process differential signals having a common mode voltage within a second common mode voltage range. Means (N5, N6) detect an operating condition of said first input stage (1) which operating condition depends on a common mode input voltage at said inputs of said first input stage. Means (P1, N7, N8) are provided for enabling said second input stage depending on said detected operating condition of said first input stage.

Abstract: A circuit for evaluating the asymmetric antenna effect of a transistor pair is provided, which can be implemented by using bipolar or complementary metal oxide semiconductor (CMOS) transistors to implement a differential amplifier, with which a pair of transistors Q1 and Q2 having similar characteristics are connected. The transistors Q1 and Q2 have a structure of, for example, one polysilicon layer and three metal layers, in which a second metal layer M2 and a third metal layer M3 are used for signal input, and metal layer M1 close to the gate oxide layer of both the transistors Q1 and Q2 are used to obtain a differential antenna ratio. The differential amplifier comprises transistors Q3 and Q4 serving as an active load, and transistor Q5, which is used for adjusting the voltage gain.

Abstract: A comparator circuit includes a differential input stage, a second differential stage having a differential output, and an output stage transforming an output signal from the differential output of the second differential stage into an output signal having a logic level. The comparator further includes a common mode measuring stage. The common mode measuring stage includes a differential pair of input transistors and a differential pair of complementary transistors biased by respective current generators, and a current mirror summing the differential output currents of the two complementary transistors pairs into a single output current signal. A switching stage is controlled by the differential output nodes of the second differential stage. A common source node of the switch stage is coupled to the output of the common mode measuring stage and to the differential output nodes of the differential input stage.

Abstract: A redundant resistor matching detector is provided with constant percentage threshold. The redundant resistor matching detector includes a voltage reference and a first operational amplifier, a second operational amplifier, a first potentiometer and a reference potentiometer. The first operational amplifier has a first input connected to a first potentiometer. The second operational amplifier has a first input connected to the reference potentiometer. The first operational amplifier and the second operational amplifier have a reference input coupled to the voltage reference. An input current mirror is coupled to the first potentiometer providing a first current. A first reference current mirror is coupled to the reference potentiometer providing a reference current. A second reference current mirror has an input coupled to a first output of the first reference current mirror and has a first output coupled to an output of the input current mirror.

Abstract: Comparator systems and methods are provided that isolate their input and output processes from each other. Comparator signals are converted to a differential current in an input process and are carried via the differential current to an output process which converts the differential current to a comparator output signal. Supply rails that are coupled to the input process are isolated from the output process and supply rails that are coupled to the output process are isolated from the input process. The differential-current transmission and supply rail isolation effectively reduce feedback and, in addition, the differential current enhances common-mode signal rejection.

Abstract: CMOS comparators are provided that have substantially improved operating frequency ranges. They include first and second differential pairs of transistors and first, second, third and fourth current mirrors. The first and second differential pairs both respond to an analog input signal but only the first differential pair is coupled to define an output port. The first and second current mirrors are cross coupled to the transistors of the first differential pair but each of the third and fourth current mirrors are cross coupled between a respective transistor of the second differential pair and a respective transistor of the first differential pair. The third and fourth current mirrors provide high-speed discharge paths for parasitic circuit capacitances. The comparator structure can be adjusted to control comparator slew rates and hysteresis.

Abstract: A sense amplifier comprising first and second CMOS inverters, an pMOS current mirror, a nMOS current mirror, a source pMOSFET to source current, and a sink nMOSFET to sink current. The gate voltage of the first CMOS inverter is the input voltage and the gate voltage of the second CMOS inverter is at the reference voltage. The output voltage is at the drains of the first CMOS inverter. The pMOS and nMOS current mirrors provide active loads to the first and second CMOS inverters. The sense amplifier is self-biasing by connecting the gate of the source pMOSFET to the gates of the pMOS current mirror and by connecting the gate of the sink nMOSFET to the gates of the nMOS current mirror.

Abstract: A phase locked loop has a charge pump circuit connected through a loop filter to a voltage controlled oscillator, and the charge pump circuit is controlled by a frequency/phase comparator, wherein the charge pump circuit includes a first current mirror circuit responsive to a first control signal for regulating a discharging current from the loop filter to a first target amount proportional to a constant current, a second current mirror circuit for regulating a reference current to a second target amount proportional to the constant current and a third current mirror circuit responsive to a second control signal for regulating a charging current to the loop filter to a third target amount proportional to the reference current, a first switching circuit for charging a first parasitic capacitor coupled to the first current mirror circuit from the constant current source and a second switching circuit for charging a second parasitic capacitor coupled to the third current mirror circuit through the second current

Abstract: A high voltage detector circuit (FIG. 2) maintains a voltage (V.sub.2) on a reference line driven by a charge pump by turning the charge pump on with a signal (PUMPON) when the reference line voltage (V.sub.2) drops below a reference voltage (V.sub.1) plus a CMOS transistor threshold voltage. The high voltage detector is further configured to use transistors which have a maximum gate to drain, or gate to source voltage which exceeds the pin supply voltage to the chip. The high voltage detector includes comparators made up of a series of current mirrors driven by weak current sources enabling the circuit to use a minimum amount of power.

Abstract: A three input comparator facilitates the comparison of a signal to the greater of two different reference voltages in a manner which mitigates propagation delay. A first differential pair of transistors facilitates comparison of the two reference voltages to one another, while second and third differential pairs of transistors facilitate comparison of the signal to the higher of the two reference voltages.

Abstract: The a timer circuit and oscillator are disclosed. The timer circuit is similar in functionality to a '555 timer circuit but uses few transistors. The timer circuit has two differential pairs of transistors, three current mirrors, two selectable current sources, and one inverter. The two differential pairs of transistors, three current mirrors, two selectable current sources, and one inverter are arranged to receive an IN+ voltage, an IN voltage, and a IN- voltage. From these inputs a Q and a Q(bar) output is generated. This timing circuit can be used to generate an oscillator by connecting a capacitor, a current source, and current drain to the IN voltage.

Abstract: A differential threshold comparator is provided which includes an input stage and a threshold stage, both supplied with current by a common current mirror. Both stages are differential comparators, with the input stage having terminals for receiving an input signals and the threshold stage having terminals for receiving a threshold voltage. The threshold comparator produces a signal which indicates whether the difference between input signal voltages exceeds the threshold voltage.

Abstract: A circuit configuration for a comparator provides that first and second transistors on an input side are connected jointly by their two control terminals to a first input terminal, and that the first and second transistors have different cutoff voltages. Such a circuit configuration has the advantage that at a zero-volt input voltage, no current is consumed. The circuit configuration can be connected directly to a high-voltage supply without the aid of regulating voltages or high-precision reference voltages.

Abstract: A P-type MOSFET transistor as a current source and an N-type MOSFET transistor are connected in series between a power supply and one end of a bit line that is also connected to a memory cell with the other end thereof. The gate electrode of the P-type MOSFET transistor and that of the N-type MOSFET transistor are then biased by a current capability setting circuit in such a manner that a current capability of the P-type MOSFET transistor is smaller than a current capability of a memory cell and a current capability of the N-type MOSFET transistor is larger than the current capability of the P-type MOSFET transistor.

Abstract: The present invention provides a differential amplifier. The differential amplifier includes first and second inputs and an output. The differential amplifier further includes a lateral bipolar transistor. The lateral bipolar transistor includes a well region that has a base region, an emitter region and first and second collector regions. The first and second collector regions are spaced apart from the emitter. The lateral bipolar transistor also includes a first gate, coupled to the first input, to overlay a space between the emitter region and the first collector region. Furthermore, the lateral bipolar transistor includes a second gate, coupled to the second input, to overlay a space between the emitter region and the second collector region. The differential amplifier further includes first and second load devices coupled to the first and second collector regions.

Abstract: A control circuit is provided which includes a single programmable terminal for controlling a plurality of modes, functions or parameters in a programmable circuit with a minimum of program elements connected to the single programmable terminal. The program elements may illustratively be resistors, capacitors, inductors or other circuit components. In a first mode, for example, two program elements control a signal generating function in the programmable circuit. In a second mode in this example, a voltage provided internally forces a condition at the programmable terminal to control another signal generating function. In both first and second modes, the values of the program elements, selectable by the user, also determine the particular frequencies of the respective generated signals. In a third mode, the signals generated in the first and second modes are compared to provide yet another a control function.

Abstract: A comparator circuit with low current consumption for driving a sawtooth generator includes two differential amplifiers connected back to back, which control the bias current of an operational amplifier through a current measuring device and a means for impressing bias current. During normal operation, that is to say outside a switch-over point of the operational amplifier, the means for impressing bias current is supplied by a comparatively small standby current. Near the switch-over point of a sawtooth signal, the bias current of the operational amplifier is increased. Since the bias current source supplies a current pulse only at the switch-over point of the sawtooth signal, but remains switched off for the remainder of the time, the comparator circuit current consumption is minimized.

Abstract: A circuit for controlling the bias current in a differential amplifier is disclosed. A differential amplifier comprising complementary differential input transistor pairs includes variable bias current sources to provide bias currents to the differential input pairs. The variable bias current sources are coupled to an input current control unit that includes one or more programmable switches to vary the amount of bias current supplied to the differential input pairs. The slew rate, differential gain, and common mode input range of the differential amplifier may be varied by adjusting the bias currents to the differential input pairs. A cascode circuit is coupled between the differential input pairs and their respective load circuits to extend the common mode input range to the supply voltage rail values.

Abstract: A differential receiver cell circuit is provided for a CMOS chip for use in chip to chip interfaces. The differential receiver cell is testable to enable the testing of the functioning of other circuits on the CMOS chip. The receiver cell is provided (between a voltage source VDD! and ground GND!) with a bias switch circuit comprising a PFET T115 having its drain connected to the receiver cell's voltage source. This source has a node VDD! connected to a self biasing network composed of PFET T106 and NFET T107 whose input node NB and output are connected to control a current controlling device NFET T118 whose drain is connected to a common node NA and whose source is coupled to ground.

Abstract: A transient signal detector for monitoring a signal line and generating a control signal which indicates when the magnitude of a differential signal on the line exceeds either a positive or negative threshold value. The threshold value is defined by a single current, thereby allowing for a single, simple adjustment of such threshold in both the positive and negative directions.

Abstract: A current switching type switch circuit is constructed with a constant current source, a switch group consisted of a pair of P-type MOS transistors and a current mirror circuit consisted of first, second, third and fourth npn bipolar transistors. The sources of the P-type MOS transistors are connected in common and to a first power source via the constant current source. Complementary clock signals are input to the gates of the P-type MOS transistors. Collectors and bases of first and second npn bipolar transistors are respectively connected to drains of the P-type MOS transistors, and to bases of third and fourth npn bipolar transistors. Collectors of the third and fourth npn bipolar transistors are respectively connected to first and second load circuits. Also, emitters of all of npn bipolar transistors are connected to a second power source.

Abstract: A CMOS output circuit including a differential error amplifier (3) is operated to provide a stable quiescent bias current in an output MOSFET by causing a first current equal to a threshold voltage of a P-channel reference MOSFET (M1) divided by the resistance of a reference resistor (R1) to flow through an N-channel current mirror control MOSFET (M4). A first N-channel current mirror output MOSFET (M6) having a gate coupled to the gate of the N-channel current mirror control MOSFET (M4) and a drain coupled to a drain of the P-channel reference MOSFET (M1) causes a second current proportional to the first current to flow through the P-channel reference MOSFET (M1). The first current is controlled in response to feedback from the P-channel reference MOSFET (M1). A bias current in an error amplifier (3) is controlled in response to the N-channel current mirror control MOSFET (M4).

Abstract: An improved current mode driver circuit uses N-type transistors in current mirrors to achieve higher speed operation at lower cost. A pair of matched low frequency P-type transistors provide a small amount of current to each side of the differential amplifier which comprise of only N-type transistors in a current mirror connection to amplify the current supplied thereto.

Abstract: A level comparator has a first and a second input terminal, an output terminal and a first and a second power terminal. In the comparator, the gate of a first MOS transistor is connected to the first input terminal. The gate of a second MOS transistor is connected to the second input terminal and the source of the second MOS transistor is connected to the source of the first MOS transistor. A current source is connected between the source of the first MOS transistor and the first power terminal. The drain and gate of a third MOS transistor are connected to the drain of the first input terminal and the source of the third MOS transistor is connected to the second power terminal. The drain of a fourth MOS transistor is connected to the drain of the second MOS transistor. The gate of the fourth MOS transistor is connected to the gate of the third MOS transistor. And the source of the fourth MOS transistor is connected to the second power terminal.

Abstract: A differential comparator having a low-offset comparator and two processing paths, each of which receives one of the two primary inputs to the differential comparator and generates one of the two inputs to the low-offset comparator. The output of the low-offset comparator is the output of the differential comparator. Each processing path is capable of (1) generating an offset voltage and (2) turning on and off the generation of that offset voltage. In a preferred embodiment, each processing path has a passive resistor that generates the offset voltage and a pair of shunt transistors that selectively shorts out the passive resistor. The output of the low-offset comparator is connected (either directly or indirectly through an inverter) to the gates of the shunt transistors. The shunt transistors are therefore controlled by the output of the low-offset comparator. In each of two modes of operation, a different one of the passive resistors is "on" while the other passive resistor is "off.

Abstract: In a differential circuit including first and second transistors, a constant current circuit causes a constant current to flow through the first transistor. A variable current circuit causes a variable current to flow through the second transistor. A differential input voltage is given to drive the first and the second transistors and to produce an output signal in the form of an output current which may be either a differential output current across two output electrodes or a variable output current flowing through an output electrode. Each of the first and the second transistors may be bipolar transistors or MOSFET's. A relationship between the differential input voltage and the output signal is specified by a peculiar characteristic dependent on the bipolar transistors or the MOSFET's. Therefore, the differential circuit may be incorporated in an LSI circuit.

Abstract: A CMOS output circuit including a differential error amplifier (3) is operated to provide a stable quiescent bias current in an output MOSFET by causing a first current equal to a threshold voltage of a P-channel reference MOSFET (M1) divided by the resistance of a reference resistor (R1) to flow through an N-channel current mirror control MOSFET (M4). A first N-channel current mirror output MOSFET (M6) having a gate coupled to the gate of the N-channel current mirror control MOSFET (M4) and a drain coupled to a drain of the P-channel reference MOSFET (M1) causes a second current proportional to the first current to flow through the P-channel reference MOSFET (M1). The first current is controlled in response to feedback from the P-channel reference MOSFET (M1). A bias current in an error amplifier (3) is controlled in response to the N-channel current mirror control MOSFET (M4).

Abstract: In a differential circuit including first and second transistors, a constant current circuit causes a constant current to flow through the first transistor. A variable current circuit causes a variable current to flow through the second transistor. A differential input voltage is given to drive the first and the second transistors and to produce an output signal in the form of an output current which may be either a differential output current across two output electrodes or a variable output current flowing through an output electrode. Each of the first and the second transistors may be bipolar transistors or MOSFET's. A relationship between the differential input voltage and the output signal is specified by a peculiar characteristic dependent on the bipolar transistors or the MOSFET's. Therefore, the differential circuit may be incorporated in an LSI circuit.

Abstract: A differential amplifier circuit whose noise is reduced when used in a CMOS operational amplifier without increasing its cost includes a differential input stage circuit in which gate lengths of load transistors and gate lengths of differential input transistors are set to an optimal ratio to minimize internal transistor noise components.

Abstract: A circuit for interfacing between the output voltage terminals of a focal plane array (FPA) detector and subsequent digital processing circuitry and employing a differential circuit including respective resistors to create first and second input currents and a control circuit to adjust the first and second input currents to eliminate the common mode current component. The control circuit includes a current source and a current mirror amplifier on each side of the differential circuit with each current mirror amplifier supplying a current sample signal to a current sense amplifier which, in turn, supplies a control signal to each of the current sources. The interface circuit accommodates input voltages of different polarities and magnitudes, while operating from reduced supply voltage levels and providing output currents limited within a defined range.

Abstract: A comparator with a built-in hysteresis is disclosed. The comparator has a differential input stage, an output stage, and a bias circuit with a hysteresis circuit. The hysteresis circuit selectively applies a bias voltage to the differential input stage to achieve the hysteresis.

Abstract: A recording apparatus including a magnetic write head and a write amplifier with capacitive current compensation. The write amplifier is made up of four current mirrors which are turned on two at a time by two switchable floating current sources connected between the input terminals of the current mirrors in order to produce a write current of alternating polarity through the write head. The parasitic capacitances across the write head and/or the parasitic capacitances of the write amplifier at the write terminals are neutralized by means of neutralizing capacitors. The high impedance at the terminals of the write head enables the common-mode voltage across the write head to be fixed at any desired voltage value by means of a common-mode circuit.

Abstract: The comparator circuit comprises a first comparator circuit having a differential input stage composed of P-channel FETs; a second comparator circuit having a differential input stage composed of N-channel FETs; pull-up and pull-down resistances connected to the output terminals of the two comparator circuits, respectively; at least one skew adjusting circuit having a delay circuit and a selector; and a logical gate for obtaining the two output signals of the two comparator circuits. Since the two differential input signals can be received by the two comparator circuits and according to the potentials of the two differential input signals, even if the supply potential is low, the comparator circuit can compare the two differential input signals in a wide potential range from the ground potential and the supply potential, so that it is possible to provide a high speed interface circuit which can satisfy the LVDS standard at a low supply potential.

Abstract: In a differential circuit including first and second transistors, a constant current circuit causes a constant current to flow through the first transistor. A variable current circuit causes a variable current to flow through the second transistor. A differential input voltage is given to drive the first and the second transistors and to produce an output signal in the form of an output current which may be either a differential output current across two output electrodes or a variable output current flowing through an output electrode. Each of the first and the second transistors may be bipolar transistors or MOSFET's. A relationship between the differential input voltage and the output signal is specified by a peculiar characteristic dependent on the bipolar transistors or the MOSFET's. Therefore, the differential circuit may be incorporated in an LSI circuit.

Abstract: A control circuit, in particular for a direct current control in positioning systems, comprising a differential circuit (1), a control logic (2) and a full bridge (3) connected between a supply voltage V.sub.S and a reference potential GND. The differential circuit (1) has a first hysteresis comparator (HC1) and a second hysteresis comparator (HC2). The two comparator inputs (HC1-, HC1+, HC2-, HC2+) of the two hysteresis comparators (HC1, HC2) are connected each to one of two input terminals (IN1, IN2) of the control circuit and crosswise to a comparator input of the respective other comparator (HC1, HC2). The inverting input of each comparator (HC1, HC2) is connected to the non-inverting input of the respective other comparator. (FIG.

Abstract: A low voltage differential signal detector capable of detecting low-voltage differential signals over a large common-mode voltage range. The signal detector uses two differential pairs of opposite conductivity type, coupled to each other in a self-biasing manner to detect low voltage swings in a signal over a large common-mode voltage range. Depending upon the common-mode voltage level of the signal, the low-voltage level swings will be detected by one of the differential pairs, the other of the differential pairs or both.