Abstract: At the input sides of matched first and second differential amplifiers 11 and 12, first and second input buffers 21 and 22, and third and fourth input buffers 23 and 24 are respectively connected. In input transistors Q5 and Q8 in the first and second input buffers 21 and 22, emitter currents corresponding to the collector currents of differential transistors Q3 and Q4 of the second differential amplifier 12 flow by using current mirror circuits. Changes of base-emitter voltage of the PNP transistors Q5 and Q8, and changes of base-emitter voltage of NPN transistors Q1 and Q2 cancel each other, and an output voltage improved in linearity is obtained between a negative phase output terminal 33 and a positive phase output terminal 34.

Abstract: A low-voltage transconductor circuit in which the common mode gain of a first transconductor stage is compensated by a second transconductor stage (connected in parallel with the first transconductor stage) which has no differential mode transconductance, and which is connected so that its common mode transconductance offsets the common mode transconductance of the stage. This greatly reduces the common mode current signal at the output, while avoiding the necessity for a current sink at the source of the input transistors.

Abstract: An apparatus for recording on a magnetic record carrier includes a write amplifier comprising four current mirrors which are turned on two at a time by two switchable floating current sources connected between the input terminals of the current mirrors in order to produce a write current of alternating polarity through a write head. The high impedance at the terminals of the write head enables the common-mode voltage across the write head to be fixed at any desired voltage value by means of a common-mode circuit. The symmetrical structure further enables the parasitic capacitances at the write terminals to be neutralized by means of neutralizing capacitors.

Abstract: A strobed comparator for a large common mode range is described, which includes a mixture of natural and enhancement transistors, and a high-swing folded-cascode architecture, to achieve an improved dynamic range suitable for audio applications.

Abstract: A negative input voltage comparator that compares a negative input voltage signal against a positive voltage signal in a circuit, such as an integrated circuit. The negative input voltage signal is effectively isolated from the circuit by means of a series resistor in the base-emitter circuit of a transistor which is connected in the output leg of a current comparator.

Abstract: A current mirror circuit including at least one current bank transistor coupled to a cascade transistor. The cascade transistor further coupled to a current mirror input. A current-controlled current source operable for both receiving a differential current from said current mirror input and for producing a charging current for charging a gate of the at least one current bank transistor in order to null the differential current.

Abstract: A comparator circuit includes a differential amplifier circuit (5, 6, and 7) which receives a first input voltage and a second input voltage, and outputs a comparison result signal by comparing the first and second input voltages, a current circuit (8) which supplies a driving current to activate the differential amplifier circuit, and a current control circuit (2) which is connected to the differential amplifier circuit and the current circuit. The current control circuit is deactivated when the first input voltage is lower than the second input voltage, and is activated when the first input voltage is higher than the second input voltage to reduce the driving current supplied.

Abstract: Method and apparatus for logic signal level translation to a semiconductor switch. The logic signal input is converted by a first circuit referenced to a first power supply level to a current source or sink gated on and off by the logic signal. The resulting current is coupled to the input of a second circuit referenced to a second power supply level to control complementary devices providing a switching signal for coupling to the semiconductor switch. The second circuit preferably includes circuitry for assuring that both complementary devices cannot be on at the same time.

Abstract: A control circuit, in particular for a direct current control in positioning systems, comprising a differential circuit (1), a control logic (2) and a full bridge (3) connected between a supply voltage V.sub.S and a reference potential GND. The differential circuit (1) has a first hysteresis comparator (HC1) and a second hysteresis comparator (HC2). The two comparator inputs (HC1-, HC1+, HC2-, HC2+) of the two hysteresis comparators (HC1, HC2) are connected each to one of two input terminals (IN1, IN2) of the control circuit and crosswise to a comparator input of the respective other comparator (HC1, HC2). The inverting input of each comparator (HC1, HC2) is connected to the non-inverting input of the respective other comparator.

Abstract: There is provided a potential comparing circuit of which output potential is almost equal to specific determining potential levels used in a next-stage logic circuit. The potential comparing circuit has a current-mirror circuit, a first transistor, a second transistor and an offset correcting circuit. The current-mirror circuit is connected to a first power source. The first transistor has a gate to which a first input signal is supplied. The second transistor has a gate to which a second input signal is supplied, a channel type of the second transistor being the same as a channel type of the first transistor. The offset correcting circuit is provided between a drain of the first transistor and an input point of the current-mirror circuit, for correcting a potential level obtained at a drain of the first transistor to correspond to specific potential levels related to the specific determination potential levels.

Abstract: A data transmitter (12) on a data bus (16) keeps its drive transistor (36) at a minimum bias according to the minimum voltage level on the data bus. The current flowing through the drive transistor in response to a data signal, or a proportional current, is mirrored (52, 54) and compared to a current source (60). Any mismatched between the mirrored current and the current source enables a transistor (58) to bias the drive transistor so that it maintains a minimum conduction state. The base of the drive transistor is held one V.sub.be above the minimum voltage on the data bus. The minimum bias on the base of the drive transistor keeps it conducting so that the transition to full conduction is smooth and prevents any sharp transitions that may cause undesired radiated emissions.

Abstract: An off-line controller circuit having a line voltage detector and a switched current bootstrap circuit. The controller receives current from the line and provides a drive signal for controlling the switch(es) of an off-line converter. The line voltage detector establishes a voltage proportional to the line voltage in response to a portion of the received line current. The proportional voltage is compared to a reference voltage to provide a control signal for inhibiting the drive signal when the proportional voltage is less than the reference voltage, indicating that the line voltage is less than a predetermined level. The switched current bootstrap circuit limits a bootstrap current provided to the controller supply voltage from the converter output in accordance with current shunted to ground by a supply voltage clamp.

Abstract: A comparator circuit comprising a transconductance stage that senses a first and a second input voltage and a transresistance stage that senses the current output of the transconductance stage while limiting a voltage swing at the output of the transconductance stage. The transresistance stage generates an output voltage at an output node that indicates whether the first or the second input voltage has a greater magnitude.

Abstract: A tristateable sense amplifier, for driving a bus directly with minimal size devices, includes a control transistor coupled to a reference voltage terminal and having a control electrode receiving a first control signal. A first series circuit includes a first transistor of a first channel type and a second transistor of opposite channel type coupled between the control transistor and a supply voltage terminal. A control electrode of the second transistor receives a first input signal and the second transistor generates a first output signal. A second series circuit includes a third transistor of the first channel type and a found transistor of the opposite channel type coupled between the control transistor and the supply terminal. A second input signal is coupled to the control electrode of the fourth transistor.

Abstract: A first field effect transistor has a drain electrode connected to a first current input terminal of a first current mirror circuit and a gate electrode connected to a first voltage input terminal which is supplied with a first voltage input terminal. A second field effect transistor has a drain electrode connected to a first current output terminal of the first current mirror circuit and a gate electrode connected to a second voltage input terminal which is supplied with a second input voltage. A second current mirror circuit has a second current input terminal connected to the first current output terminal and a second current output terminal connected to a power terminal through a resistor and to a voltage output terminal which is supplied with an output voltage. A comparator may include third and fourth current mirror circuits instead of the first and the second field effect transistors.

Abstract: The present invention is a closed-loop peak detection circuit comprising switching means, comparing means, control means, two current sources, and a holding capacitor. The switching means selectively provides one of a plurality of input signals to the comparing means. The control means is coupled to the comparing means. The control means receives first and second control signals for selecting one of three modes: reset, peak detect, and hold. First and second current sources are coupled to the control means. A capacitor is coupled to the first and second current sources for generating an output signal. The output signal is feedback coupled to the comparing means. The comparing means determines when one of the plurality of input signals exceeds the output signal. The control means enables and disables the current sources in response to the comparing means and to the first and second control signals.

Abstract: A semiconductor memory includes a memory cell for storing data; a bit-line pair to be charged to an electric potential corresponding to the data stored in the memory cell; a data-line pair to be electrically connected to the bit-line pair; and a main amplifier for amplifying an electric potential difference of the data-line pair and outputting a signal corresponding to the data. The main amplifier restrains itself from outputting the signal corresponding to the data until the electric potential difference of the data-line pair becomes higher than a predetermined value.

Abstract: An I/O bus interface cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference voltage provided to the driver. The I/O cell also includes a receiver circuit having an input terminal coupled to said output terminal of said driver with the receiver disposed to latch an unresolved, unamplified received signal prior to resolving the state of the signal. The I/O cell further includes a termination circuit having a terminal connected to the output of said driver, and having a selectable impedance characteristic at said terminal, with said selectable impedance being in accordance with a reference voltage provided to an input of said termination circuit. Preferably, the I/O cell a the driver, receiver and termination circuits are fabricated on a common semiconductor substrate.

Abstract: A drive circuit for triggering a symmetrical bipolar transistor, the drive circuit having a balanced circuit connected to two operating electrodes of the symmetrical bipolar transistor. The balanced circuit includes two parts connected by their bases. Collectors of the two parts of the balanced circuit act on inverse balanced circuits which control a switching device which in turn controls the triggering of the symmetrical bipolar transistor.

Abstract: Current output terminals of first and second current mirror circuits are connected. An input terminal of a third current mirror circuit is connected to a node of the current output terminals of the first and second current mirror circuits. A load circuit is connected between a current output terminal of the third current mirror circuit and a first voltage. An output terminal is connected to the load circuit. First and second currents to be compared with each other are supplied to current input terminal of the first and second current mirror circuits.

Abstract: An improved comparator circuit is provided for comparing two input signals and producing a resulting digital output. The comparator circuit uses a single cascode devices and current mirror circuit parallel coupled to two differential amplifier stages. One differential amplifier stage receives differential input signals and the other differential amplifier stage receives a variable reference voltage and a feedback voltage from the output of the comparator. The reference voltage is varied according to user requirements. The reference voltage can be varied to any voltage within the range of the input signals placed on the differential amplifier stage. Hysteresis differential voltage on the input differential amplifier stage can be accurately controlled by varying the biasing current and reference voltage placed on the hysteresis differential amplifier stage.

Abstract: A cut-off frequency setting circuit of a filter circuit comprises a filter circuit possessing an analog signal input terminal for adjustment of the cut-off frequency, a memory capable of rewriting data, and a D/A converter for producing an analog current according to the output data from the memory and for supplying the analog current into the analog input terminal for adjustment of the cut-off frequency of the filter circuit.

Abstract: In a tone control circuit of luminance signals, an adjusting current is used to add to or subtract from input signals with a gain control. Output signals are thus controlled to have a predetermined gradient based on an arbitrary output setting voltage against the input signals, and an input-output characteristic represented by an arbitrary line graph is obtained by plural gradient adjusting circuits.