Abstract: A light emitting element driving circuit for supplying driving current I2 to a light emitting element 10 connected to one line 2 of a current mirror circuit 12 is equipped with a pulse generating circuit 20 connected to the other line 1 so that pulse current flows therethrough, and superposing means 30 for superposing a first auxiliary pulse current on the pulse current in synchronization with the rise-up time of the pulse current. The rise-up time is shortened by the superposition. In the driving circuit, a source follower circuit is connected to the current mirror circuit, and current flowing through the source follower circuit is set to be substantially proportional to current flowing through the other line of the current mirror circuit.

Abstract: The present invention discloses a skew detection device which can detect a skew of a transistor changed due to a driving voltage, a size and a process variable. The skew detection device includes a first potential level generator for outputting a first voltage, a second potential level generator for outputting a second voltage, a first level shifter for receiving the first voltage and outputting a first shift voltage, a second level shifter for receiving the second voltage and outputting a second shift voltage, and a comparator for comparing the first shift voltage with the second shift voltage. The first voltage is determined according to a drain-source current of a first MOS transistor operated in a linear region, and the second voltage is determined according to a drain-source current of a second MOS transistor operated in a saturation region.

Abstract: Circuitry is provided for converting differential digital data to single-ended digital data. Differential data signals have complementary pairs of signals that are referenced to each other. Single-ended signals are referenced to ground. The circuitry can be used on an integrated circuit to convert incoming differential data from a high-speed communications link to single-ended data for processing by internal logic on the integrated circuit. The operation of the circuitry can be stabilized using load circuitry that reduces temperature effects and jitter in the single-ended data.

Abstract: An output stage circuit for a current mode device provides open loop reduction or cancellation of DC offset in differential output signals. Differential input signals are received and sourcing current mirrors provide mirrors of the differential input signals to output nodes. Sinking current mirrors also provide mirrors of opposite polarity of the differential input signals to the output nodes corresponding to the opposing sourcing current mirrors. The summing of the mirror currents at the output nodes substantially reduces or eliminates the DC offset components present in the input signals.

Abstract: A computer system includes at least one high-voltage device and at least one low-voltage device. The low-voltage device has at least one differential input receiver, which reduces the risk of gate oxide stress by ensuring the voltage level on the low-voltage device gate(s) is at or below a predetermined value. The high-voltage device may be a memory controller and the low-voltage device may be a memory.

Abstract: The present invention concerns an apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a reference output voltage in response to a plurality of reference voltages. The second circuit may be configured to generate an output voltage in response to the reference output voltage and an unknown voltage. The output voltage may comprise accurately controlled hysteresis.

Abstract: A drive device for a light-emitting component including a reference source, which generates a current specification signal specifying a desired current through the light-emitting component, a current mirror circuit, which generates a current equal to a fraction of the actual current through the light-emitting component, and a regulating device having a first input and a second input, the first input being connected to the current mirror circuit and the second input being connected to the reference source. In this case, the regulating device generates a regulation signal that regulates the current through the light-emitting component in such a way that the deviation between the desired current and the actual current becomes minimal.

Abstract: A semiconductor integrated circuit device is comprised of an amplifier circuit having first and second PMOS and NMOS transistors. The first PMOS transistor has a gate electrode and a drain electrode connected together. The second PMOS transistor has a gate electrode connected to the gate electrode of the first PMOS transistor and a course electrode connected to a course electrode of the first PMOS transistor. The first NMOS transistor has a drain electrode connected to the drain electrode of the first PMOS transistor and a gate electrode sat as a first input terminal. The second NMOS transistor has a drain electrode connected to a drain electrode of the second PMOS transistor, a source electrode connected to a sourse electrode of the first NMOS transistor, and a gate electrode sat as a second input terminal. At least one of the first NMOS transistor and the second NMOS transistor is comprised of a buried channel transistor.

Abstract: A plurality of LEDs is driven in parallel, in at least two modes. In a first mode, the LEDs are driven with a first voltage. In subsequent modes, the LEDs are driven with successively higher voltages. The forward voltage drop for each LED is monitored, and the driver switches from the first mode to successive modes based on the largest of the LED forward voltage drops. The current through each LED is controlled by directing a reference current through a first digitally controlled variable resistance circuit, and directing the LED current through a second digitally controlled variable resistance circuit having substantially a known ratio to the first variable resistance circuit and connected in series with the LED. A digital count is altered based on a comparison of the first and second currents, and the first and second variable resistance circuits are simultaneously altered based on the digital count.

Abstract: A pre-buffer voltage level shifting circuit includes a multi-supply voltage level shifting circuit having single gate oxide devices coupled to produce a pre-buffer output signal to an output buffer. The pre-buffer output signal has a level within normal gate voltage operating levels of the single gate oxide devices for each of the least a plurality of supply voltages. In one embodiment, the multi-supply voltage level shifting circuit includes a current mirror coupled to at least one of the first or second power supply voltage and also uses a non-linear device, such as a transistor configured as a diode, which is coupled to the output of current mirror. The non-linear device is coupled to receive a digital input signal from a signal source, such as from a section of core logic. A switching circuit coupled to the non-linear device selectively activates the non-linear device based on a level of the digital input signal.

Abstract: A plurality of LEDs is driven in parallel, in at least two modes. In a first mode, the LEDs are driven with a first voltage. In subsequent modes, the LEDs are driven with successively higher voltages. The forward voltage drop for each LED is monitored, and the driver switches from the first mode to successive modes based on the largest of the LED forward voltage drops. The current through each LED is controlled by directing a reference current through a first digitally controlled variable resistance circuit, and directing the LED current through a second digitally controlled variable resistance circuit having substantially a known ratio to the first variable resistance circuit and connected in series with the LED. A digital count is altered based on a comparison of the first and second currents, and the first and second variable resistance circuits are simultaneously altered based on the digital count.

Abstract: A comparator compares a first voltage applied to a first input to a second voltage applied to a second input. The comparator delivers an output signal having a first value when the second voltage is higher than the first voltage, and having a second value when the second voltage is lower than the first voltage. The comparator includes first and second PMOS transistors arranged as current mirrors. The first PMOS transistor has its source connected to the first input of the comparator for receiving the first voltage. The second PMOS transistor has its source connected to the second input of the comparator for receiving the second voltage. The output of the comparator is connected to the drain of one of the transistors.

Abstract: A low read current, low power consumption sense amplifier well suited for low frequency RFID systems is disclosed. An MOS transistor receives the read current from a memory cell, typically an EEPROM, and a current mirror is formed by a parallel MOS transistor. The mirror current is integrated on a capacitor after the charge on the capacitor is cleared via a reset pulse. A time period is defined during which the voltage on the capacitor is compared to a second voltage. The second voltage is formed from a reference voltage or from dummy cells, in either case the reference voltage is at about the logic boundary between a one and zero stored in a memory cell. A comparator, with or without input hysteresis, receives the voltage on the capacitor and a second voltage and within the time period, the output state of the comparator indicates the binary contents of the memory cell.

Abstract: A comparator according to the present invention can generate an output signal of low or high level by comparing a first and second input voltages that have a common voltage. An input stage circuit of a comparator according to the present invention receives a common voltage detection signal. The common voltage is supplied with a first offset voltage when the common voltage detection signal is on low level, and the common voltage is supplied with a second offset voltage when the common voltage detection signal is on high level. Then, the input stage circuit performs amplification to output a voltage difference between the first input voltage and the second input voltage to the comparator. Accordingly, the comparator with offset voltage according to the present invention can sufficiently amplify the input signal difference of low common voltage by selectively applying different offset voltages to a common voltage in accordance with the common voltage level of the input signal.

Abstract: In a differential output signal circuit suitable for restraining voltage overshooting/undershooting at differential output terminals due to lags in input signals and realizing stable and fast switching of differential input signals, a first differential pair of PMOS transistors connected to a first current source and a second differential pair of NMOS transistors connected to a second current source are mutually connected at the differential output terminals, and a capacitor is connected between the connection nodes of the respective differential pairs and current sources. A transitional current path of the capacitor restrains voltage variations during differential input signal switching.

Abstract: A differential voltage transmission circuit. The reference bias circuit outputs a first reference voltage, a second reference voltage and a reference current corresponding to a reference current adjusting signal. The differential comparator compares the difference between the first reference voltage and the second reference voltage with the difference between a first output voltage and a second output voltage, and outputs a result signal corresponding to the compared result. The decision circuit outputs the reference current adjusting signal corresponding to the result signal. The output circuit outputs the first output voltage and the second output voltage generated at both terminals of a termination resistor when the reference current flows through the termination resistor.

Abstract: A differential amplifying apparatus includes first and second differential pair circuits having opposite conductivity, first and second current sources, first and second current mirror circuits, and a first voltage amplifying circuit. The first current source is connected between the first differential pair circuit and a first power source terminal, biasing the first differential pair circuit. The second current source is connected between the second differential pair circuit and a second power source terminal, biasing the second differential pair circuit. The first current mirror circuit is connected between a corresponding output terminal of the second differential pair circuit and the first power source terminal. The second current mirror circuit is connected between a corresponding output terminal of the second differential pair circuit and the first power source terminal. The first voltage amplifying circuit amplifies voltages from the first differential pair circuit and outputs amplified voltages.

Abstract: Voltage comparator circuit capable of precisely comparing voltages to ground and power supply potentials, without level converter or plurality of power supplies. First and second MOS transistors, with gates commonly connected and drains are connected to a first power supply potential with the same gate width and length. Third MOS transistor with opposite conductive type than first and second, with drain connected to second power supply potential connected to source of first. A fourth MOS transistor with opposite conductive type to the first and second, with a drain connected to the second power supply potential, with same gate width and length as the third. The drain and gate of the first are connected, and a comparative reference potential applies to the gate of the third. Input signal is given to gate of the fourth, and output signal is derived from the drain of the second.

Abstract: A comparator includes an adjustable offset and particularly dimensioned and configured components. The particular configuration and dimensioning of the comparator ensure that the offset voltage can be set precisely and permanently to a value, which can vary within a large range. The setting of an offset voltage does not lead to the degradation of other properties of the comparator, in particular to a slower reaction to changes in the input voltages.

Abstract: A peak hold circuit which improves the precision of a hold voltage. The peak hold circuit includes a first input transistor which receives an input voltage and a second input transistor which receives the hold voltage. The peak hold circuit further includes a hold capacitor, a hold-voltage setting transistor and a bypass circuit. The hold capacitor supplies the hold voltage to the second input transistor. The hold-voltage setting transistor receives base current from the collector of the first input transistor and makes the hold voltage coincide with the input voltage in accordance with the base current. The bypass circuit bypasses bias current to be supplied to the second input transistor when the hold-voltage setting transistor is turned off.

Abstract: A mirroring circuit operating at high frequencies is provided. The mirroring circuit includes a first branch having a first transistor in series with a first resistor, a second branch having a second transistor in series with a second resistor, and a servo circuit for controlling current flowing in the first branch and the second branch. The servo circuit includes a third transistor configured as a diode, a source of the third transistor coupled to a source of the first transistor, a fourth transistor configured as a shift lever, a source of the fourth transistor coupled to ground via a third resistor, a fifth transistor configured as a diode, a source of the fifth transistor coupled to a source of the second transistor, and a sixth transistor configured as a shift lever, a source of the sixth transistor coupled to ground via the third resistor.

Abstract: A method and a circuit detect the presence of a high-speed signal, such as a high-speed differential signal, based on a software-programmable signal amplitude threshold. In one embodiment, when the amplitude threshold is exceeded, a current is generated to charge a capacitor. The voltage on the capacitor is compared to a second pre-set voltage in a low-speed comparator, which provides an output voltage indicating detection of the high-speed signal.

Abstract: The comparator input stage uses low voltage transistors 20 and 21 as the input pair. They have a small threshold voltage, and hence support a low common mode. The circuit includes a current sink 22 coupled to the input pair 20 and 21; a first resistor 33 coupled between a first branch of the input pair and a voltage node V24; a second resistor 36 coupled between a second branch of the input pair and the voltage node V24; a first transistor 23 coupled to the voltage node V24; a second transistor 24 having a gate coupled to a gate of the third transistor 23; a third resistor 32 coupled to a first end of the second transistor 24; and a current source 29 coupled to a second end of the second transistor 24 for controlling a voltage across the third resistor 32 wherein the voltage across the third resistor 32 sets a voltage at the voltage node V24. This voltage at the voltage node V24 serves as an open loop regulation for protection of the input pair transistors 20 and 21.

Abstract: A method for dynamically adapting the biasing current for a fast switching voltage comparator is achieved. The difference of the two input signals of said comparator controls the comparator's biasing current, where the biasing current is high only when the difference is low and the comparator's switching is likely to happen and where the biasing current is kept low at other times. In a current mirroring circuit, the voltage difference at the comparator inputs controls the mirroring ratio. The biasing current reaches its maximum when the input voltage difference approaches zero. Once the input voltage difference crosses zero and continues to change in the same direction as before, that is after the polarity of the voltage difference changed, the control mechanism alternates the connection of the input signals to the current controlling elements, in order to now reduce the current with a further increase of the voltage difference.

Abstract: A computer system includes at least one high-voltage device and at least one low-voltage device. The low-voltage device has at least one differential input receiver, which reduces the risk of gate oxide stress by ensuring the voltage level on the low-voltage device gate(s) is at or below a predetermined value. The low-voltage device may be a memory controller and the high-voltage device may be a memory.

Abstract: Electronic devices are typically coupled together to operate as systems that require the communication of data between two or more devices. Many of these devices includes a communications circuit, such as receiver, transmitter, or transceiver for this purpose. A typical component in these communication circuits is the phase-lock loop, a circuit that in receiver circuits determines the timing of pulses in a received data signal and in transmitter circuits clocks the data out at a predetermined rate. One problem with phase-lock loops and thus the receiver and transmitter circuits that incorporate them is that they are generally tuned, or tailored, to operate at a certain frequency. This means that one cannot generally use a receiver or transmitter circuit having phase-lock loops tuned for one frequency to communicate at another frequency. The inability to communicate at other frequencies limits the usefulness of not only the receiver and transmitter circuits but also their electronic devices.

Abstract: A system and method are provided for reducing the threshold bias offset voltage in a comparator, by canceling and bypassing the bias offset current errors. The comparator system comprises amplification stages with bias cancellation circuitry and a threshold setting circuit. The bias offset current cancellation circuit is used to cancel the base current of differential amplifier input emitter follower. The bias offset current cancellation circuit also cancels the loading effect of amplifier input emitter-follower driving stage. The threshold offset voltage is further reduced by the threshold setting circuit. The threshold-setting circuit includes two integrators and a unit gain operation amplifier. The integrators have the input accept a single-ended input signal, an output connected to the negative input of the comparator, and an output connected to the unit gain operational amplifier, whose output is connected to the negative input of the comparator.

Abstract: A load independent single ended sense amplifier is provided. The sense amplifier includes a first current mirror having a first load transistor and a first reflected current transistor, and a second current mirror having a second load transistor and a second reflected current transistor. The first load transistor is capable of communicating a load current to the second load transistor. In addition, a reflected current flowing through the first reflected current transistor and the second reflected current transistor generates an amplified load current.

Abstract: A method and structure for comparing an input signal to a reference signal using a comparator comprises a circuit for setting a trip point of a rising edge of an input signal according to a value of an external voltage reference; and at least two transistors, in the circuit, for setting a trip point of a falling edge of an input signal, according to a width-to-length ratio of the at least two transistors. Moreover, the at least two transistors comprises a first transistor of length (Lx) and a width of (Wx); and a second transistor of length (Ly) and a width of (Wy), wherein the width-to-length ratio equals (WxLy)/(WyLx). The trip point of a falling edge of an input signal increases (decreases) by increasing (decreasing) the width-to-length ratio.

Abstract: An operational amplifier comprises multiple stages. A differential input stage that includes an adaptive high voltage differential pair generates up and down output currents in response to up and down input voltages. The differential input stage includes adaptive common input high voltage (HV) bias. An intermediate stage converts the up and down output currents into a first output voltage signal. The intermediate stage includes a folded cascode arrangement. The intermediate stage is biased by fixed voltage bias signals. The intermediate stage also includes unaffected slew rate stability compensation and a combined split stability compensation. An output stage includes a class AB source follower driver that generates a second output voltage signal in response to the first output voltage signal. The output stage is biased with an adaptive push-pull source follower output HV bias. The output stage includes feed-forward slew rate enhancement.

Abstract: In an embodiment consistent with the present invention, a semiconductor device having a oscillating circuit comprises: a first transistor having a control electrode and having one end and the other end of a current path thereof; a second transistor having a control electrode and having one end and the other end of a current path thereof, the control electrode is coupled to one end of the current path of the first transistor and one end of the current path thereof is coupled to the control electrode of the first transistor; a current mirror circuit that supplies a current to one end of the current path of the first transistor and one end of the current path of the second transistor; an inductor coupled to one end of the current path of the first transistor and one end of the current path of the second transistor; a first capacitor coupled to one end of the current path of the first transistor and one end of the current path of the second transistor; and a second capacitor and a switch element coupled with, are

Abstract: A multistage analog circuit for independently controlling a bias current in each stage of the multistage analog circuit having an input stage, an intermediate stage, and an output stage, includes a first current source which controls the input stage of the circuit, a second current source which controls the intermediate stage of the circuit, and a third current source which controls the output stage of the circuit. The bias current in each stage of the circuit is set by the first, second, and third current sources. An output voltage of the circuit is capable of remaining the same when the first current source is changed to affect an input transconductance of the circuit.

Abstract: An integrated circuit comparator comprises a differential amplifier, a source follower circuit coupled to a gate terminal of a first transistor in the differential amplifier, and an output circuit. One or more source follower circuits may be utilized in connection with the differential amplifier, and one or more source follower circuits may be utilized in connection with the output circuit.

Abstract: A data receiver circuit uses two parallel differential circuits to process incoming data signals. The parallel differential circuits each compare the data signal to a different clock signal. In one embodiment, the clock signals are complementary signals. Further, the parallel differential circuits are coupled to control a current mirror circuit such that an output of the data receiver is controlled in response to a differential transition between the data signal and one of the complementary clock signals. In one embodiment, a first differential circuit includes a transistor controlled by a CLK signal and a transistor controlled by the Data signal. The second differential circuit includes a transistor controlled by a /CLK signal (complement of CLK) and a transistor controlled by the Data signal.

Abstract: A programmable logic device is equipped for low voltage differential signaling (“LVDS”) by providing an LVDS input buffer and/or an LVDS output buffer on the device. I/O pins on the device that are used together in pairs for LVDS can alternatively be used individually for other types of signaling. The LVDS buffers are constructed to give good performance and to meet LVDS specifications despite variations due to temperature, manufacturing process inconsistency, and power supply changes.

Abstract: A high speed input buffer of the type having a first connection in electrical communication with a positive voltage source and a second connection in electrical communication with a negative voltage source. A first native transistor is functionally disposed between the positive voltage source and the first connection. A first contact of the first native transistor is electrically connected to the positive voltage source and a second contact of the first native transistor is electrically connected to the first connection. A second native transistor is functionally disposed between the negative voltage source and the second connection. A first contact of the second native transistor is electrically connected to the negative voltage source and a second contact of the second native transistor is electrically connected to the second connection.

Abstract: Transimpedance amplifiers are provided that generate low-distortion output voltage signals with simple, inexpensive structures that are compatible with integrated-circuit fabrication processes. The amplifiers include a current processor and a complementary output stage. The processor provides in-phase upper and lower current signals in response to a differential input current signal and differentially alters respective first and second amplitudes of these signals in response to a common-mode input current signal. The complementary output stage has upper and lower transistors that provide the output voltage signal in respective response to the upper and lower current signals and with distortion that is reduced by the altered first and second amplitudes.

Abstract: A differential amplifying circuit according to the present invention, comprising: a first differential pair having first and second transistors of the same conduction type, which outputs differential output signals in accordance with differential input signals supplied to gate terminals of said first and second transistors from differential output terminals; a second differential pair having third and fourth transistors having the same conduction type as that of said first and second transistors with threshold voltages different from each other, which outputs differential output signals in accordance with said differential input signals supplied to gate terminals of said third and fourth transistors from said differential output terminals; a bias supply part which supplies bias current to said first and second differential parts; and a differential pair control part which controls whether or not to operate said second differential pair.

Abstract: An integrated circuit comparator includes a differential amplifier, a source follower circuit coupled to a gate terminal of a first transistor in the differential amplifier, and an output circuit. One or more source follower circuits may be utilized in connection with the differential amplifier, and one or more source follower circuits may be utilized in connection with the output circuit.

Abstract: A current sense amplifier including a transconductance amplifier to measure a current passing through a sense resistor and generate a reference current indicative of the measured current. A current mirror circuit is connected to the transconductance amplifier and receives the reference current for amplification to generate an amplified output current. A cascode circuit is connected serially to the current mirror circuit to boost an output impedance for the amplifier at the output of the generated amplified output current. The current mirror circuit and cascode circuit of the current sense amplifier are each formed from a pair of transistors sharing a common control node, with the transistors realized using with bipolar or MOS technology.

Abstract: A bipolar comparator with an asymmetric differential amplifier stage is described. The comparator has two transistors, and the control electrodes of which are short circuited to one another. The two transistors have load paths that are connected in series in each case with one current source between one input terminal and a supply terminal. An output terminal is connected to the second current source and to a load electrode of the second transistor, at which output terminal an output signal can be picked up. A third transistor is provided with a load path disposed in parallel with the load path of the first transistor. The first current source generates a first operating current being a multiple of the second operating current generated by the second current source and the multiple corresponds to an effective area ratio of the first and third transistor with respect to the second transistor.

Abstract: A bipolar comparator with an asymmetric differential amplifier stage is described. The comparator has two transistors, and the control electrodes of which are short circuited to one another. The two transistors have load paths that are connected in series in each case with one current source between one input terminal and a supply terminal. An output terminal is connected to the second current source and to a load electrode of the second transistor, at which output terminal an output signal can be picked up. A third transistor is provided with a load path disposed in parallel with the load path of the first transistor. The first current source generates a first operating current being a multiple of the second operating current generated by the second current source and the multiple corresponds to an effective area ratio of the first and third transistor with respect to the second transistor.

Abstract: A comparator circuit for comparing a differential input signal to a reference signal. A differential MOS transistor pair is provided having respective gates for receiving the positive and negative components of the differential input signal. A tail current source is coupled to the common sources of the transistor pair, with the current magnitude being related to the reference signal magnitude. The first and second transistors are made differently, typically by making the sizes different, so that the gate-source voltages differ when the transistor currents are equal. A comparator stage provides a digital output which changes state when the transistor currents are equal, with the difference in gate-source voltage representing the comparator trip voltage, a trip voltage related to the magnitude of the reference signal.

Abstract: A comparator according to the present invention can generate an output signal of low or high level by comparing a first and second input voltages that have a common voltage. An input stage circuit of a comparator according to the present invention receives a common voltage detection signal. The common voltage is supplied with a first offset voltage when the common voltage detection signal is on low level, and the common voltage is supplied with a second offset voltage when the common voltage detection signal is on high level. Then, the input stage circuit performs amplification to output a voltage difference between the first input voltage and the second input voltage to the comparator. Accordingly, the comparator with offset voltage according to the present invention can sufficiently amplify the input signal difference of low common voltage by selectively applying different offset voltages to a common voltage in accordance with the common voltage level of the input signal.

Abstract: The comparator includes a differential stage having a first input and a second input, an output stage in which the output is zero when the two inputs have therebetween a specific voltage difference, and a biasing stage providing a first biasing voltage and a second biasing voltage for respectively creating a second input voltage and a first input voltage respectively in the second and first inputs such that the two input voltages have therebetween the specific voltage difference. A method for forming the same includes steps of a) providing the differential stage, b) providing the output stage and c) providing the biasing stage which has a characteristic dependent on a manufacturing parameter such that the specific voltage difference is independent of the manufacturing parameter.

Abstract: A high-impedance current source 100 having an enhanced compliance voltage. The current source 100 preferably has a means for generating a biasing current 105 and a first current mirror stage having a first transistor M6 coupled to a second transistor M1. A second current mirror stage having a third transistor M2 coupled to a fourth transistor M5 acts as a feedback circuit. A stabilization circuit having a fifth transistor M3 coupled to a sixth transistor M4 are also included. The stabilization circuit is coupled between the first and second current mirror stages and an output circuit having a seventh transistor M7 is connected to the stabilization circuit between the first and second current mirror stages. The current mirror circuit has a low compliance voltage, enhanced operating characteristics and enhanced dynamics which eliminate the need for OTAs.

Abstract: A pre-buffer voltage level shifting circuit includes a multi-supply voltage level shifting circuit having single gate oxide devices coupled to produce a pre-buffer output signal to an output buffer. The pre-buffer output signal has a level within normal gate voltage operating levels of the single gate oxide devices for each of the least a plurality of supply voltages. In one embodiment, the multi-supply voltage level shifting circuit includes a current mirror coupled to at least one of the first or second power supply voltage and also uses a non-linear device, such as a transistor configured as a diode, which is coupled to the output of current mirror. The non-linear device is coupled to receive a digital input signal from a signal source, such as from a section of core logic. A switching circuit coupled to the non-linear device selectively activates the non-linear device based on a level of the digital input signal.

Abstract: A voltage-to-current circuit utilizes an NMOS-input voltage-to-current (V-I) converter and a PMOS-input V-I converter, with both driving a common gate output stage. Each of the V-I converters includes a transconductance amplifier and a current mirror. The common gate output stage includes two series connected complementary pairs of transistors. One complementary pair drives the output, and the other complementary pair biases the first. The V-I circuit can be utilized as part of a phase detector, which is in turn can be utilized as part of a phase lock loop or a delay lock loop.

Abstract: Automatic slice level control in response to differential input signals is enabled. Analog signals are transferred differentially to remove in-phase noise. Thus, its effects on S/N are alleviated. Ideal desired DSV (e.g., DSV=0) is accomplished. Also, the circuit scale is reduced, and the processing speed is enhanced. Analog differential input signals vinp and Vinn which are obtained by reading a recording medium and are inverted with respect to each other are supplied to input terminals in1 and in2 of a comparator (1) via resistors R1 and R2. A data stream is recorded on the recording medium while giving DSV=0. A charge pump (2) is driven by the digital signal from the comparator (1). A transconductance amplifier produces output currents Itrc1 and Itrc2 that are mutually differential signals and in proportion to the voltage difference between the output voltage Vcp from the charge pump (2) and a reference voltage Vref.

Abstract: The differential amplifier of a comparator circuit includes first and second n-type MOSFETs for receiving an input signal, first and second p-type MOSFETs of a current mirror circuit, and a third n-type MOSFET of a current source circuit. The output stage includes a third p-type MOSFET for transmitting a signal, and a fourth n-type MOSFET of the current source circuit. The differential amplifier further includes fifth and sixth n-type MOSFETs respectively series-connected to the first and second n-type MOSFETs. The output stage further includes a seventh n-type MOSFET series-connected to the fourth n-type MOSFET. The gates of the fifth, sixth, and seventh n-type MOSFETs are connected to voltage bias circuits. The fifth, sixth, and seventh n-type MOSFETs suppress variations in voltage at an output node caused by poor saturation characteristics of the first, second, and fourth main n-type MOSFETs.