Having Current Mirror Amplifier Patents (Class 330/257)
  • Patent number: 8134407
    Abstract: In an embodiment of the invention, a differential input signal is coupled to a plurality of transconductance blocks. In some embodiments, each of the transconductance blocks divide an input transconductance among a plurality of signal paths to a plurality of outputs in each transconductance block. In an embodiment, the input transconductance may be divided based a ratio of transistor areas in the plurality of signal paths, though other embodiments may divide the transconductance differently. In some embodiments, transconductance block outputs of a plurality of transconductance blocks may be cross-coupled to provide a gain path for a differential signal than is greater than that of a common mode signal.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: March 13, 2012
    Assignee: Analog Devices, Inc.
    Inventors: Scott A. Wurcer, Robert F. Day
  • Patent number: 8130036
    Abstract: A circuit provides a first current corresponding to the differential input Inn and Inp, and a second current corresponding to the common mode input Vcm. The circuit then mirrors the differential current and the common mode current to a third current and a fourth current. Based on the difference between the mirrored differential current and the mirrored common mode current, the circuit pulls up or pulls down these currents to balance the corresponding difference between the differential input and the common mode input. In effect, the circuit adjusts the input common mode voltage to a desired level, without providing an opportunity for it to rise to an unwanted level.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: March 6, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wei Lin, Yung-Chow Peng
  • Publication number: 20120044021
    Abstract: A differential amplifier circuit includes: P-type and N-type differential input units outputting respectively first and second outputs in response to first and second input voltages; a P-type current mirror circuit driven by the second output; an N-type current mirror circuit driven by the first output; an output unit outputting an output voltage in response to control outputs from the P-type and N-type current mirror circuits; a first sub-current source including first and second P-type transistors connected in series; and a second sub-current source including first and second N-type transistors connected in series. Control ends of the second P-type and second N-type transistors receive the control outputs from the P-type and N-type current mirror circuits, respectively. Control ends of the first P-type and first N-type transistors are coupled to a common node between the first and second P-type transistors, and a common node between the first and second N-type transistors, respectively.
    Type: Application
    Filed: December 22, 2010
    Publication date: February 23, 2012
    Applicant: ILI Technology Corporation
    Inventors: Sung-Yau Yeh, Kuo-Jen Hsu
  • Publication number: 20120025912
    Abstract: A differential amplifier circuit can reduce consumption current and the circuit size while improving a power supply rejection ratio. The differential amplifier circuit includes a power supply line and an input part that includes an input circuit and an active load. The input circuit includes two differential input elements, and the active load includes two transistors connected to the two differential input elements. The input part generates a differential signal in response to an input signal given to the two differential input elements. The differential amplifier circuit also includes an amplifying part for generating an output voltage generating signal by amplifying the differential signal. The differential amplifier circuit also includes an output part for generating an output voltage based on the output voltage generating signal and a power supply voltage.
    Type: Application
    Filed: July 26, 2011
    Publication date: February 2, 2012
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventor: Tetsuo OOMORI
  • Publication number: 20120025911
    Abstract: An LNA circuit for providing a wide range of gain while maintaining the output headroom. In a radio frequency (RF) receiver, the signal received by the receiver may be extremely small. For a transmitter in a short distance, the received signal may be relatively strong. A low power amplifier usually is used to amplify the input signal. The LNA has to be designed to accommodate a wide range of gain. A convention LNA circuit supporting a wide range of gain often suffers from reduced output headroom due to increased current through the load resistor. The present invention discloses the use of current bleeding branch to allow a portion of current to flow through the current bleeding branch and consequently reduces the current that would have flown through the load resistor. Consequently, the voltage across the load resistor may be maintained low to allow adequate output headroom.
    Type: Application
    Filed: September 30, 2010
    Publication date: February 2, 2012
    Applicant: QUINTIC HOLDINGS
    Inventors: Zhongwu Zhao, Xiaodong Jin
  • Patent number: 8102210
    Abstract: The amplifier circuit (1) includes a differential pair of PMOS transistors at input (P3, P4), whose source receives a current from a current source (3). The gate of the first transistor (P3) of the pair defines a non-inverting input (XOUT) and the gate of the second transistor (P4) of the pair defines an inverting input (XIN). A drain of the first transistor (P3) of the differential pair is connected to a diode connected NMOS transistor (N2) of a first current mirror (N1, N2), and a drain of the second transistor (P4) of the differential pair is connected to a diode connected NMOS transistor (N3) of a second current mirror (N3, N4).
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: January 24, 2012
    Assignee: The Swatch Group Research and Development Ltd
    Inventor: Carlos Velasquez
  • Patent number: 8085092
    Abstract: An amplifier arrangement comprises a first transistor (18), a first bias transistor (13) and a first field-effect transistor (51). A first input signal (VN) is supplied for amplification to a control terminal of the first transistor (18). The first bias transistor (13) is coupled to the first transistor (18) via a first node (12). The first field-effect transistor (51) is coupled for clamping of a first node voltage (V1) provided at the first node (12).
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: December 27, 2011
    Assignee: austriamicrosystems AG
    Inventor: Pramod Singnurkar
  • Patent number: 8081030
    Abstract: An amplifier capable of operating in multiple modes may include (a) first and second voltage inputs and (b) first and second current outputs that have substantially the same amplitude and polarity. Preferably, the inputs and outputs of the amplifier will have high impedances. The amplifier may operate in a first mode—and function as an operational amplifier—when the first and second current outputs are coupled together. The amplifier may operate in a second mode—and function as a type-2 current conveyor—when the second current output is coupled to the second voltage input. The amplifier may additionally include a third current output that has an amplitude that is substantially the same as the amplitudes of the first and second outputs and a polarity that is substantially opposite to the polarities of the first and second outputs. In this configuration the amplifier may function as a four-terminal floating nullor.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: December 20, 2011
    Assignee: Honeywell International Inc.
    Inventor: Paul M. Werking
  • Patent number: 8081150
    Abstract: Provided is an output buffer for a source driver of an LCD with a high slew rate, and a method of controlling the output buffer. The output buffer, which outputs a source line driving signal for driving a source line of the LCD, includes: an amplifier section amplifying an analog image signal; an output section outputting the source line driving signal in response to a signal amplified by the amplifier section; and a slew rate controller section, setting a capacitance of a capacitor section to a first capacitance, during a first charge sharing period in which the source line is precharged to a first precharge voltage, setting the capacitance of the capacitor section to a second capacitance smaller than the first capacitance during a second charge sharing period in which the source line driving signal is supplied to the source line, and setting the capacitance of the capacitor section to the first capacitance while the source line driving signal is maintained after the second charge sharing period.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: December 20, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chang-Ho An
  • Publication number: 20110291760
    Abstract: A folded cascode differential amplifier includes a high-voltage input stage and a low-voltage output stage. The input stage is formed from high-voltage MOS transistors, two of which constitute a differential pair. The output stage is formed from low-voltage MOS transistors, some of which constitute a current mirror circuit connected to the differential pair. The output stage also includes at least one transistor that amplifies a voltage produced in the current mirror circuit to generate an output voltage signal. The high-voltage MOS transistors have higher breakdown voltages than the low-voltage MOS transistors. Incorporation of both types of transistors into a single amplifier reduces the necessary number of transistors and the necessary number of bias voltages.
    Type: Application
    Filed: April 27, 2011
    Publication date: December 1, 2011
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventor: Tetsuji Maruyama
  • Patent number: 8067983
    Abstract: An error amplifier expected to exhibit rail-to-rail operation, high bandwidth, and high slew rate, is described, the error amplifier comprising a first stage to receive an input differential voltage and to provide transconductance gain, an intermediate stage to provide current gain, and an output stage to drive a load.
    Type: Grant
    Filed: February 19, 2010
    Date of Patent: November 29, 2011
    Assignee: Monolithic Power Systems, Inc.
    Inventor: Farhood Moraveji
  • Patent number: 8067982
    Abstract: The invention relates to a transconductance amplifier, intended to supply current variations di when it receives voltage variations dv, with a desired conversion coefficient Gm called transconductance: Gm=di/dv. The amplifier comprises a PMOS transistor (MP1) and an NMOS transistor (MP2) connected by their drains, their gates both being connected to the voltage input receiving dv; the source of the first transistor is connected to a constant current source (IB1) and to a resistor (R) and to the drain of a third MOS transistor (MN3) of the same type as the first; the sources of the second (MN2) and third (MN3) transistors are commoned, the gate of the third transistor being connected to the drains of the first and second; the output is connected to a circuit (MN4) which mirrors the current of the third transistor. The resulting amplifier has good linearity and can be used in a sample and hold device used to sample charges.
    Type: Grant
    Filed: January 15, 2008
    Date of Patent: November 29, 2011
    Assignee: Commissariat a l'Energie Atomique
    Inventor: James Wei
  • Publication number: 20110279182
    Abstract: A circuit for power amplification of an input signal includes an input stage and an output stage, the said input stage including: a drive means incorporating a so-called main drive transistor, and a first so-called main input transistor able to receive the input signal, and mounted as a current mirror with the main drive transistor. The first main input transistor is coupled to the output stage via a second so-called main input transistor incorporated into the input stage and controlled by the drive means, the first and second main input transistors being coupled together and with the earth according to a structure of Darlington type by way of a resonant circuit.
    Type: Application
    Filed: November 9, 2010
    Publication date: November 17, 2011
    Applicant: THALES
    Inventors: VINVENT FRÉDÉRIC FRANÇOIS PETIT, BRUNO LOUIS, RÉMI LUC PIERRE CORBIERE
  • Publication number: 20110279718
    Abstract: An amplifier is provided. The amplifier includes a differential amplifier including a tail, a current mirror connected between output terminals of the differential amplifier and a power line receiving a supply voltage, and a first switching circuit for connecting and disconnecting one of the output terminals of the differential amplifier to and from the tail in response to a first switching signal.
    Type: Application
    Filed: March 29, 2011
    Publication date: November 17, 2011
    Inventors: Kwi Sung Yoo, Seog Heon Ham, Dong Hun Lee, Min Ho Kwon, Wun-Ki Jung
  • Patent number: 8058909
    Abstract: The present invention is intended to achieve a transconductance amplifier and a voltage/current converting method which can provide a sufficient amplitude and a high degree of design freedom. The method comprises the steps of converting a first voltage signal to a first current signal; converting a second voltage signal to a second current signal; obtaining the common-mode components of the first and second current signals; and subtracting the common-mode components from the first and second current signals to obtain third and fourth signals, and further, subtracting the fourth current signal from the third current signal to generate a first output, while subtracting the third current signal from the fourth current signal to generate a second output.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: November 15, 2011
    Assignee: NEC Corporation
    Inventor: Hiroyuki Okada
  • Publication number: 20110273232
    Abstract: Provided is a differential amplifier circuit in which an offset voltage is independent from input voltages. A first correction current generation circuit and a second correction current generation circuit are provided and configured to cause the same current as a current flowing through a folded cascode amplifying stage to flow into an output stage. Accordingly, transistors included in the folded cascode amplifying stage and transistors included in the output stage have the same bias condition.
    Type: Application
    Filed: April 22, 2011
    Publication date: November 10, 2011
    Inventors: Atsushi Igarashi, Masahiro Mitani
  • Publication number: 20110273231
    Abstract: A semiconductor integrated circuit receives an input current, and supplies, to a different circuit, an output current that corresponds to the input current. A first terminal of a first variable resistor is connected to an input terminal. A first transistor and a second transistor are sequentially arranged in series between a power supply terminal and a second terminal of the first variable resistor. A third transistor and a fourth transistor are sequentially arranged in series between the power supply terminal and an output terminal. The gates of the first transistor and the third transistor are each connected to the second terminal of the first variable resistor. The gates of the second transistor and the fourth transistor are each connected to the input terminal. The first variable resistor is configured to be capable of switching the resistance value thereof according to the input current.
    Type: Application
    Filed: January 21, 2011
    Publication date: November 10, 2011
    Applicant: ROHM CO., LTD.
    Inventor: Kei NAKAMURA
  • Publication number: 20110242145
    Abstract: A display device is provided with a plurality of differential amplifiers associated with a plurality of data lines within a display panel. Each of the plurality of differential amplifiers includes: an output stage circuit including a first transistor having a source connected to the positive power supply and a second transistor having a source connected to the negative power supply, an output terminal connected to drains of the first and second transistors; and a bias control circuit provided between the adder circuit and the output stage circuit to achieve bias control of gates of the first and second transistors. During the switching period, the output stage circuit provides short-circuiting between the gate and source of each of the first and second transistors, and the bias control circuit cuts off a current path between the gates of the first and second transistors during the switching period.
    Type: Application
    Filed: March 29, 2011
    Publication date: October 6, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Kouichi NISHIMURA, Masamitsu NAKAOKA
  • Patent number: 8031888
    Abstract: Two control voltages are generated, one increasing and another decreasing, in response to the rise of the voltage of a condenser of a common time-constant circuit. Based on the two control voltages, a first and a second currents are formed, from which four different combinations of currents are established. By feeding one of four combinations to each of multiple differential output amplifier circuits each having a feedback resistor, the multiple output amplifier circuits can be individually started up or shut down without generating popcorn noise, using only one single time constant circuit.
    Type: Grant
    Filed: January 29, 2007
    Date of Patent: October 4, 2011
    Assignee: Rohm Co., Ltd.
    Inventors: Takenori Kato, Akio Ogura
  • Publication number: 20110234319
    Abstract: Provided is a differential amplifier circuit with a small circuit size. When a differential voltage (Vinp?Vinn) is higher than a predetermined voltage, a PMOS transistor (4) is turned ON. At this time, a current source (12) is connected in parallel to a current source (11), and the current source (12) supplies a drive current to a differential amplifier circuit (10). In other words, the current sources (11 and 12), rather than only the current source (11), supply a total current (I11+I12) to the differential amplifier circuit (10) as the drive current. Accordingly, a slew rate of an output voltage (Vout) is increased. Two PMOS transistors and the current source (12) are simply required for controlling the slew rate of the output voltage (Vout), and hence the differential amplifier circuit (10) is small in circuit size.
    Type: Application
    Filed: March 23, 2011
    Publication date: September 29, 2011
    Inventor: Toshiyuki Tsuzaki
  • Publication number: 20110216258
    Abstract: A differential amplifying circuit includes first and second differential transistor pairs, first and second constant current sources, first and second current mirror circuits and first and second output transistors. The differential amplifying circuit also includes a feedback circuit configured to perform feed-back operations to the first and second current mirror circuits to restrain reduction of gate voltages of the output transistors. The constant current sources are configured to increase bias currents in response to reduction of the gate voltages of the output transistors.
    Type: Application
    Filed: March 1, 2011
    Publication date: September 8, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Fumihiko KATO
  • Patent number: 8008972
    Abstract: A differential signal generator circuit includes: a first amplifier for comparing an input signal with a threshold voltage and outputting differential signals; and a second amplifier for adjusting the threshold voltage in response to the differential signals. The second amplifier includes: a first transistor and a second transistor forming a differential pair, the gate of each transistor receiving a respective one of the differential signals; a third transistor and a fourth transistor forming a current mirror, the third transistor being connected between the drain of the first transistor and a reference potential point, the fourth transistor being connected between the drain of the second transistor and the reference potential point; a current source connected to the sources of the first and second transistors; and an adjusting section for adjusting drain current of the first transistor in response to an externally applied current or voltage.
    Type: Grant
    Filed: November 5, 2007
    Date of Patent: August 30, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventors: Toshihide Oka, Masaaki Shimada
  • Patent number: 7999617
    Abstract: An amplifier circuit, comprising a differential input stage (M1, M2), two cross-coupled current mirrors (M3, M4; M5, M6) coupled to respective outputs of the differential input stage (M1, M2), and a minimum selector circuit (M11, M12, M13, M14) coupled to outputs of the current mirrors.
    Type: Grant
    Filed: January 17, 2007
    Date of Patent: August 16, 2011
    Assignee: NXP B.V.
    Inventor: Paul Bruin
  • Patent number: 7994858
    Abstract: An operational trans-conductance amplifier circuit having a voltage clamp circuit. The clamp circuit utilizes low area and power overhead, has a sharp clamp characteristic, and little degradation in the small-signal DC gain at the “knee” of the clamp characteristic. The clamp circuit includes a comparator circuit and a current control circuit. The amplifier and clamp circuits may further include a clamp voltage generator circuit.
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: August 9, 2011
    Assignee: AltaSens, Inc.
    Inventors: David Standley, Laurent Blanquart
  • Publication number: 20110181358
    Abstract: A differential amplifier circuit includes a differential input stage comprising first and second transistors whose sources are connected with each other, a constant current source connected between the sources of the first and second transistors and a ground, a current mirror circuit comprising third and fourth transistors whose sources are connected with a power supply source, a fifth transistor of a same conductive type as that of the first transistor, connected at a drain to a drain of the third transistor, connected at a source to a drain of the first transistor and connected at a gate to a reference voltage source; and a sixth transistor of a same conductive type as that of the second transistor, connected at a drain to a drain of the fourth transistor, connected at a source to a drain of the second transistor, and connected at a gate to the reference voltage source.
    Type: Application
    Filed: January 20, 2011
    Publication date: July 28, 2011
    Applicant: RICOH COMPANY, LTD.
    Inventor: Katsuhiko AISU
  • Patent number: 7986188
    Abstract: A circuit includes a differential amplifier unit that receives an input signal at a non-inverting input thereof, a constant current source, a load circuit, an output transistor that receives an output of the differential amplifier unit as an input and drives a load circuit, a phase compensation circuit including a variable resistor and a capacitor connected in series between the input of the output transistor and a feedback path, an output current monitor circuit that detects an output current flowing through the output transistor, and a bias voltage generation circuit that varies a resistance value of the variable resistor in accordance with a result of the detection of the output current by the output current monitor circuit. A signal obtained by voltage dividing an output of the output transistor by resistors is supplied to an inverting input of the differential amplifier unit.
    Type: Grant
    Filed: April 2, 2010
    Date of Patent: July 26, 2011
    Assignee: Elpida Memory, Inc.
    Inventor: Atsushi Fujiwara
  • Patent number: 7982542
    Abstract: A circuit comprises a first amplifier portion and a second amplifier portion. The first amplifier portion includes first and second transistors coupled together in a common-base configuration. A current mirror is coupled to the first and second transistors. A first filter is coupled between a first input and the first and second transistors. The second amplifier portion includes third and fourth transistors coupled together in a common-base configuration. First and second current sources are coupled to the third and fourth transistors. A second filter is coupled between a second input and the control electrodes of the third and fourth transistors, wherein the first and second filters are coupled together.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: July 19, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Thierry Sicard
  • Patent number: 7982538
    Abstract: A differential includes first and second current mirror circuits that provide the gates of slave transistors with gate voltages of master transistors via a voltage follower where a slew rate at a rise time is equal to a slew rate at a fall time. Thus, when the master current is increased or decreased, an incremental change in slave current and a decremental change in slave current are symmetrical with each other. The use of such current mirrors in a differential manner leads to no generation of common mode noise even in these changes.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: July 19, 2011
    Assignee: Sony Corporation
    Inventors: Hidekazu Kikuchi, Gen Ichimura, Yukihisa Kinugasa
  • Publication number: 20110169808
    Abstract: An amplifier and a display driving circuit. The amplifier includes an input stage, a bias stage and an output stage. The input stage determines voltage levels of two nodes in correspondence to two input voltages received in response to a first bias voltage, and includes four path selecting switches, two input transistors and one bias transistor. The bias stage generates two class AB output voltages which correspond to the voltage levels of the two nodes, and includes current mirrors, ten path selecting switches, class AB bias circuits and two bias transistors. The output stage generates an output voltage VOUT that corresponds to the two class AB output voltages, and includes two coupling capacitors and two push-pull transistors. The plurality of path selecting switches operate by one signal of a first path selecting signal and a second path selecting signal that are exclusively enabled with respect to each other.
    Type: Application
    Filed: September 4, 2009
    Publication date: July 14, 2011
    Applicant: Silicon Works Co. Ltd
    Inventors: Young Suk Son, Yong Sung Ahn, Hyun Ja Cho, Hyung Seog Oh, Dae Keun Han
  • Patent number: 7978010
    Abstract: A boost operational amplifier. A boot operational amplifier may include a differential amplifying unit amplifying and/or outputting an inputted differential voltage, a first mirroring unit mirroring a current flowing through a first output terminal of a differential amplifying unit, which may output a mirrored first mirror current, a second mirroring unit mirroring a current flowing through a second output terminal of a differential amplifying unit, which may output a mirrored second mirror current, a pull-up transistor connected between a first power source and an output node, which may switch based on a first and/or a second mirror current, and/or a pull-down transistor connected between a second power source and an output node, which may switch based on a first and/or a second mirror current.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: July 12, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Won-Hyo Lee
  • Publication number: 20110163809
    Abstract: According to one embodiment, a first transistor is connected between a first power supply rail and an output unit. A second transistor is connected between the output unit and a second power supply rail. A gm amplifier includes an input unit and first and second output terminals and amplifies a difference between a signal input to the input unit and a reference voltage. First and second current mirror circuits are connected to be vertically stacked between the first rail and the first terminal as well as a gate of the second transistor. Third and fourth current mirror circuits are connected to be vertically stacked between the second rail and the second terminal as well as a gate of the first transistor. The gate of the first transistor is connected to the first and second circuits. The gate of the second transistor is connected to the third and fourth circuits.
    Type: Application
    Filed: September 21, 2010
    Publication date: July 7, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiroyuki Tsurumi
  • Publication number: 20110148525
    Abstract: A current mirror circuit provided in an emitter follower configuration achieves linearly output over a range of input currents by operating in response to a bias current that is a replica of the input current. The current mirror may include a pair of transistors and a pair of resistors, in which: a first resistor and a base of a first transistor are coupled to a first input terminal for a first input current, an emitter of the first transistor and a base of the second transistor are coupled to a second input terminal for a second input current, the first and second input currents being replicas of each other, an emitter of the second transistor being coupled to the second resistor, a collector of the second transistor being coupled to an output terminal of the current mirror, and a collector of the first transistor and the two resistors are coupled to a common node.
    Type: Application
    Filed: March 7, 2011
    Publication date: June 23, 2011
    Applicant: ANALOG DEVICES, INC.
    Inventor: Sandro HERRERA
  • Patent number: 7965118
    Abstract: Described herein are methods and apparatuses for achieving a desired duty cycle on an output of a PLL. According to one embodiment, a method is described, including generating a single ended clock signal from a differential common mode clock signal using a limiting differential amplifier, wherein the single ended clock signal has a duty cycle, generating a differential bias current signal in response to the duty cycle of the single ended clock signal, and correcting the duty cycle of the single ended clock signal to a desired duty cycle by applying the differential bias current signal to the limiting differential amplifier.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: June 21, 2011
    Assignee: Honeywell International Inc.
    Inventor: James Douglas Seefeldt
  • Publication number: 20110140782
    Abstract: A fully-differential circuit includes a differential gm-boosting circuit and/or a differential output circuit. The use of differential gm-boosting and output circuits improves input common-mode and power-supply noise rejection relative to the prior art. The fully differential gm-boosted circuit may be used in a wide variety of applications.
    Type: Application
    Filed: December 16, 2009
    Publication date: June 16, 2011
    Inventors: Adrià Bofill-Petit, Xavier Redondo-Navarro
  • Patent number: 7961041
    Abstract: In one embodiment, a circuit having a chopper stabilized amplifier and a network coupled in feedback with the chopper stabilized amplifier is disclosed. The circuit also has a plurality of switches coupled to an output of the chopper stabilized amplifier, and a summing network coupled to the plurality of switches. Ones of the plurality of switches are coupled to ones of a plurality of the summing network inputs.
    Type: Grant
    Filed: May 15, 2008
    Date of Patent: June 14, 2011
    Assignee: Infineon Technologies AG
    Inventor: Mario Motz
  • Patent number: 7956690
    Abstract: An operational amplification circuit includes a differential amplification circuit portion that amplifies a differential input, and an output circuit portion that outputs the amplified output using a signal amplified in the differential amplification circuit portion. The differential amplification circuit portion is provided with a pair of first transistors to which signals are differentially input, and second and third transistors which are connected to current paths of the pair of first transistors and which constitute current mirror circuits with respect to each other. The output circuit portion is provided with a fourth transistor, a gate of which is connected to a drain of the second transistor, and an amplified output is output from a drain of the fourth transistor.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: June 7, 2011
    Assignee: ALPS Electric Co., Ltd.
    Inventor: Kimihiro Nakao
  • Patent number: 7956679
    Abstract: A differential amplifier that has a current supply and a differential current to voltage converter with a positive current input node, a negative current input node and a voltage output node, has offset voltage trimming. The voltage output node provides an output voltage that is proportional to the difference in current values flowing into the positive current input node and a negative current input node. A trimming circuit has a plurality of trimming control inputs, an inverting trimming output, a non-inverting trimming output and trimming inputs coupled to the current supply. Trimming resistances couple the inverting trimming output to the non-inverting trimming output. Trimming selectors, controllable by a trim code provided to the trimming control inputs, provide for selectively connecting the current supply directly to the non-inverting trimming output while selectively connecting the current supply to the inverting trimming output through a first selected group of the trimming resistances.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: June 7, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Hiroyuki Kimura
  • Publication number: 20110121902
    Abstract: In an embodiment of the invention, a differential input signal is coupled to a plurality of transconductance blocks. In some embodiments, each of the transconductance blocks divide an input transconductance among a plurality of signal paths to a plurality of outputs in each transconductance block. In an embodiment, the input transconductance may be divided based a ratio of transistor areas in the plurality of signal paths, though other embodiments may divide the transconductance differently. In some embodiments, transconductance block outputs of a plurality of transconductance blocks may be cross-coupled to provide a gain path for a differential signal than is greater than that of a common mode signal.
    Type: Application
    Filed: November 25, 2009
    Publication date: May 26, 2011
    Inventors: Scott A. WURCER, Robert F. DAY
  • Patent number: 7948314
    Abstract: A tunable, linear operational transconductance amplifier includes a differential voltage to current conversion unit adapted to generate first and second output signals at respective first and second output nodes responsive to first and second differential input signals. A first current amplification unit is adapted to generate a third output signal responsive to the first output signal and first and second control signals. A second current amplification unit is adapted to generate a fourth output signal responsive to the second output signal and the first and second control signals.
    Type: Grant
    Filed: May 27, 2009
    Date of Patent: May 24, 2011
    Assignee: STMicroelectronics (Shenzhen) R&D Co. Ltd.
    Inventors: Kunkun Zheng, Jianhua Zhao
  • Publication number: 20110102086
    Abstract: A circuit provides a first current corresponding to the differential input Inn and Inp, and a second current corresponding to the common mode input Vcm. The circuit then mirrors the differential current and the common mode current to a third current and a fourth current. Based on the difference between the mirrored differential current and the mirrored common mode current, the circuit pulls up or pulls down these currents to balance the corresponding difference between the differential input and the common mode input. In effect, the circuit adjusts the input common mode voltage to a desired level, without providing an opportunity for it to rise to an unwanted level.
    Type: Application
    Filed: November 2, 2010
    Publication date: May 5, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Wei LIN, Yung-Chow PENG
  • Patent number: 7924094
    Abstract: An amplifier includes a signal amplification part that outputs an output signal obtained by amplifying an input signal and a common mode voltage VCM of the output signal, and a common mode feedback part that outputs a signal according to a difference between the common mode voltage VCM and a reference potential Vref as a regulation signal SREG. The regulation signal SREG from the common mode feedback part is fed back to a current source of the signal amplification part and a current source of the common mode feedback part.
    Type: Grant
    Filed: May 8, 2009
    Date of Patent: April 12, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Souji Sunairi
  • Patent number: 7924096
    Abstract: An exemplary negative impedance converting circuit for functioning as a voltage buffer and/or negating the impedance of a connected load. The negative impedance converting circuit includes inputs, outputs, a first transconductance stage and a second transconductance stage. The transconductance gain value of the first transconductance stage is greater than a transconductance gain value of the second transconductance stage. Exemplary embodiments of a reference voltage buffer using the negative impedance converting circuit are also described.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: April 12, 2011
    Assignee: Analog Devices, Inc.
    Inventor: Gregory Patterson
  • Patent number: 7920026
    Abstract: An output stage of an amplifier circuit includes one or more output transistors that are selectively driven by a boosted drive circuit, where the boosted drive circuit is arranged such that the output range of the amplifier circuit is increased while maintaining reduced quiescent current. The drive signal to each output transistor is selectively increased only when demanded by the output load conditions. The threshold for boosting the drive signal can be adjusted for optimized performance. In one example, a class AB output stage includes a separate drive boost circuit for each output transistor. For this example, each drive boost circuit has a separate threshold for boosting each of the drive signals to the output transistors. The boosting can also be adjusted to optimize the differential input stage and current mirror maximum current requirement while maintaining minimum required bias currents.
    Type: Grant
    Filed: April 7, 2008
    Date of Patent: April 5, 2011
    Assignee: National Semiconductor Corporation
    Inventor: Rodney Alan Hughes
  • Patent number: 7916133
    Abstract: A buffer circuit is driven with a low voltage and operates at a high speed has first and second comparators constituted by P channel and N channel MOS transistors provided between an input terminal and an output terminal of a buffer amplifier. A predetermined offset voltage is set for the comparing operation, and a switch circuit turns ON/OFF in response to an output signal from the first comparator and the output signal of the second comparator. A leading up of an output voltage from the buffer amplifier is accelerated by the current flowing from a power source line to the output terminal. The buffer circuit also includes an operation restricting circuit for restricting the comparing operation of the second comparator in a range of a dead band of the transistors.
    Type: Grant
    Filed: September 6, 2005
    Date of Patent: March 29, 2011
    Assignee: Rohm Co., Ltd.
    Inventor: Hiroyuki Inokuchi
  • Patent number: 7911275
    Abstract: This disclosure relates to maintaining constant gain within multi-stage amplifiers.
    Type: Grant
    Filed: April 6, 2009
    Date of Patent: March 22, 2011
    Assignee: Infineon Technologies AG
    Inventor: Dieter Draxelmayr
  • Patent number: 7907012
    Abstract: A current mirror circuit provided in an emitter follower configuration achieves linear output currents over a range of input currents by operating in response to a bias current that is a replica of the input current. The current mirror may include a pair of transistors and a pair of resistors, in which: a first resistor and a base of a first transistor are coupled to a first input terminal for a first input current, an emitter of the first transistor and a base of the second transistor are coupled to a second input terminal for a second input current, the first and second input currents being replicas of each other, an emitter of the second transistor being coupled to the second resistor, a collector of the second transistor being coupled to an output terminal of the current mirror, and a collector of the first transistor and the two resistors are coupled to a common node.
    Type: Grant
    Filed: October 21, 2008
    Date of Patent: March 15, 2011
    Assignee: Analog Devices, Inc.
    Inventor: Sandro Herrera
  • Patent number: 7907011
    Abstract: A folded cascode operational amplifier having an improved phase margin due to pole-zero cancellation by using a plurality of cascode-connected bias circuits and frequency compensation capacitors.
    Type: Grant
    Filed: August 14, 2009
    Date of Patent: March 15, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kyu Young Chung
  • Patent number: 7898330
    Abstract: The present invention comprises class AB amplifier systems exhibiting low quiescent power, low-voltage operation, high gain, high bandwidth, low noise and low offset, and requiring a small die area. The amplifier systems use a differential first stage and a second stage of two pair of nested current mirrors interconnected in a particular way. Using a low quiescent current, the present invention reduces power consumption almost to a theoretical minimum. Also the circuit will operate at an input of only 1.8V with a threshold voltage of 1V. Various embodiments are disclosed.
    Type: Grant
    Filed: April 21, 2009
    Date of Patent: March 1, 2011
    Assignee: Number 14 B.V.
    Inventors: Rudy G. H. Eschauzier, Nico van Rijn
  • Publication number: 20110025655
    Abstract: An operational amplifier is provide with: a first MOS transistor pair connected to a non-inverting input terminal and an inverting input terminal; an intermediate stage connected to the first MOS transistor pair connected to the first MOS transistor pair; a first output transistor having a drain connected to an output terminal; and a first source follower. The first source follower is inserted between a gate of the first output transistor and a first output node of the intermediate stage.
    Type: Application
    Filed: July 30, 2010
    Publication date: February 3, 2011
    Inventors: Kouichi Nishimura, Atsushi Shimatani, Hiromichi Ohtsuka
  • Publication number: 20110025654
    Abstract: A differential amplifier circuit includes: an input terminal and an inversion input terminal; a PMOS transistor pair connected with the non-inversion input terminal and the inversion input terminal; and an output circuit section. The PMOS transistor pair includes first and second PMOS transistors, and the NMOS transistor pair includes first and second non-doped type NMOS transistors as a depletion type of NMOS transistors in which a channel region is formed in a P-type substrate without a P well. The output circuit section includes a first current mirror of a folded cascode type connected with the first and second non-doped type NMOS transistors, and outputs an output voltage in response to a current from the first current mirror.
    Type: Application
    Filed: June 24, 2010
    Publication date: February 3, 2011
    Inventors: Kouichi NISHIMURA, Toshikazu MURATA