Abstract: A low-offset current-sense amplifier and an operating method thereof are disclosed. The low-offset current-sense amplifier includes a sense amplifier, a first current supply unit, a second current supply unit, and a processing unit. The first current supply unit is coupled to the sense amplifier, and includes a first transistor group and a first current output terminal. The second current supply unit is coupled to the sense amplifier, and includes a second transistor group and a second current output terminal. The processing unit controls the on/off of some transistors of the first transistor group and the second transistor group according to electric currents output from the first current output terminal and the second current output terminal, respectively.

Abstract: Methods and apparatus to minimize saturation in a ground fault detection device are disclosed. An example method includes connecting a capacitor simulator to a node of the ground fault detector device to prevent saturation, and monitoring power-line conductors for ground fault conditions with the ground fault detector device. An example apparatus to simulate a saturation capacitance in a ground fault device includes a sense coil induced by power-line conductors, and at least one of an amplifier or a current detector including an input connected to the sense coil and an output connected to a ground fault detector. The example apparatus also includes a saturation capacitor simulator connected to a node of at least one of the amplifier or the current detector to prevent saturation.

Abstract: An operational amplifier includes a first amplifier to which an input signal is applied, and a second amplifier to which an output of the first amplifier is applied, wherein the second amplifier includes a first transistor including a gate to which the output of the first amplifier is applied, and a second transistor including a gate to which the output of the first amplifier is applied, and a drain coupled to a source of the first transistor.

Abstract: A power amplifier provides relatively stable quiescent current while maintaining relatively high signal gains and peak to quiescent current ratios. The power amplifier has an input stage and a current mirror stage and incorporates a control transistor between these stages. The control transistor transitions to the triode mode for small inputs and offset voltages thereby reducing the amplifier circuit's gain. However, the control transistor transitions from the triode region to saturation as the input signal becomes larger thereby allowing the amplifier circuit to maintain a relatively high gain for large inputs. Accordingly, better quiescent current characteristics can be obtained without significantly sacrificing performance.

Abstract: A circuit for power amplification of an input signal includes an input stage and an output stage, the said input stage including: a drive means incorporating a so-called main drive transistor, and a first so-called main input transistor able to receive the input signal, and mounted as a current mirror with the main drive transistor The first main input transistor is coupled to the output stage via a second so-called main input transistor incorporated into the input stage and controlled by the drive means, the first and second main input transistors being coupled together and with the earth according to a structure of Darlington type by way of a resonant circuit

Abstract: An output buffer circuit with enhanced slew rate is disclosed. A first and a second slew-rate enhancing transistor are configured to enhance the slew rate of the source transistor and the sink transistor of an output stage. A first control circuit and a second control circuit turn off the first and the second slew-rate enhancing transistors during the static state, and turn on the first and the second slew-rate enhancing transistors during the transition.

Abstract: An electronic device has a manipulation part which outputs a control signal including a first analog signal and a second analog signal obtained by inverting a phase of the first analog signal; and a display part which includes a semiconductor integrated circuit supplied at an input terminal thereof with the control signal to output a signal depending upon the control signal from an output terminal thereof, and which displays a predetermined image based on the signal output from the semiconductor integrated circuit.

Abstract: Circuits are disclosed that may include a plurality of transistors having controllable current paths coupled between at least a first and second node, the transistors configured to generate an analog electrical output signal in response to an analog input value; wherein at least one of the transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region.

Abstract: Differential input pairs have been used in analog electronics with both CMOS and bipolar transistors for many years. Conventional designs for differential input pairs, though, may not be suitable for emerging technology transistors, such as graphene transistors, carbon nanotube (CNT) transistors, or other ambipolar transistors. Here, a differential input pair has been provided that uses ambipolar transistors, which accounts for the more unusual I-V (drain current to gate-source voltage) characteristics of ambipolar transistors.

Abstract: An apparatus comprises an amplifier circuit and a detection circuit. The amplifier circuit includes a high voltage supply rail, a low voltage supply rail, and an output stage. The detection circuit is electrically coupled to the amplifier output stage and generates an indication when the output voltage at the output stage exceeds a specified output voltage threshold value. The amplifier circuit further includes a bias circuit configured to bias the amplifier circuit with a first bias current value when the output voltage is less than the specified output voltage threshold value, and bias the amplifier circuit with a second bias current value when the output voltage exceeds the specified output voltage threshold value.

Abstract: A circuit provides a first current corresponding to the differential input Inn and Inp, and a second current corresponding to the common mode input Vcm. The circuit then mirrors the differential current and the common mode current to a third current and a fourth current. Based on the difference between the mirrored differential current and the mirrored common mode current, the circuit pulls up or pulls down these currents to balance the corresponding difference between the differential input and the common mode input. In effect, the circuit adjusts the input common mode voltage to a desired level, without providing an opportunity for it to rise to an unwanted level.

Abstract: A comparator includes: a wide-swing operation transconductance amplifier (OTA), having first and second differential input pairs for receiving first and second differential input signals respectively, the wide-swing OTA generating first and second intermediate output voltages in comparing the first with the second differential input signals; a current switch group; a current mirror group, wherein when an input common mode voltage of the first and the second differential input signal tends to one of a first and a second reference voltage, one of the first and the second differential input pair is turned off, and the current switch group and the current mirror group compensate a current flowing through the other of the first and the second differential input pair; and a decision circuit coupled to the wide-swing OTA, for enlarging a voltage difference between the first and the second intermediate output voltage to output a voltage comparison output signal.

Abstract: A voltage adder circuit includes an amplifier circuit having a first operational amplifier and into which a first voltage is input, a circuit that supplies an output current to the amplifier circuit, and a current providing section that detects the output current of the circuit and supplies an output current equal to the output current of the circuit in magnitude so that the output current of the circuit is prevented from inputting to or outputting from the first operational amplifier through an output terminal of the first operational amplifier. A second voltage is input into the circuit.

Abstract: An amplifier includes an output stage circuit, a current source, a PMOS input pair, an NMOS input pair and a current transferring circuit. The output stage circuit is electrically coupled to a supply voltage and a ground voltage. The current source has a node to provide a current. The PMOS input pair is coupled to the node and the ground voltage and controlled by an input voltage. The NMOS input pair coupled to the supply voltage is controlled by the input voltage. The current transferring circuit is coupled to the node and the NMOS input pair. When the input voltage is less than a specific value, the current flows into the PMOS input pair through the node. When the input voltage is larger than or equal to the specific value, the current flows into the NMOS input pair through the node and the current transferring circuit.

Abstract: A slew rate enhancing circuit is disclosed. A current mirror circuit generates a mirrored current according to a current source, and the mirrored current is adaptively provided for an amplifier. A switch circuit is electrically coupled with the current source and the current mirror circuit. The switch circuit includes a first branch and a second branch that are coupled in parallel, wherein passage of the first branch and passage of the second branch are respectively controlled by a first switch and a second switch according to the non-inverting input voltage and the inverting input voltage.

Abstract: An amplifier with a non-linear current mirror comprises an amplification stage having an input terminal for an input signal as well as an output stage coupled to the amplification stage by a current mirror stage. The current mirror stage comprises at least one mirror transistor coupled to the amplification stage and at least one output transistor coupled to the output stage. The amplifier comprises two variable resistive elements, each of them connected in series to one of the mirror transistor and the output transistor. A tuning stage is adapted to tune the variable resistive elements in response to the input signal.

Abstract: An amplifying circuit includes a first circuit component configured to receive and amplify first and second input voltages to generate an output voltage. The first circuit component is formed by a first amplifier and a second amplifier. A second circuit component is configured to provide a first offset current that is associated with a first input current of the first amplifier. The first offset current compensates for variation in the first input current. A third circuit component is configured to provide a second offset current that is associated with a second input current of the second amplifier. The second offset current compensates for variation in the second input current.

Abstract: A comparator includes: a pre-amplification module, configured to generate two amplified differential signal reference currents according to an input voltage and a reference voltage; and a differential signal obtaining module, configured to obtain a differential signal according to the two amplified differential signal reference currents. The pre-amplification module includes a differential unit, an offset unit, and an amplification unit, where the differential unit is configured to generate two direct current bias currents according to the input voltage and the reference voltage; the offset unit is configured to generate an offset current of the two direct current bias currents according to the input voltage and the reference voltage, so as to reduce magnitude of the two direct current bias currents and obtain two differential signal reference currents; the amplification unit is configured to receive the two differential signal reference currents, and amplify the two differential signal reference currents.

Abstract: Provided is a differential amplifier circuit with a small circuit size. When a differential voltage (Vinp?Vinn) is higher than a predetermined voltage, a PMOS transistor (4) is turned ON. At this time, a current source (12) is connected in parallel to a current source (11), and the current source (12) supplies a drive current to a differential amplifier circuit (10). In other words, the current sources (11 and 12), rather than only the current source (11), supply a total current (I11+I12) to the differential amplifier circuit (10) as the drive current. Accordingly, a slew rate of an output voltage (Vout) is increased. Two PMOS transistors and the current source (12) are simply required for controlling the slew rate of the output voltage (Vout), and hence the differential amplifier circuit (10) is small in circuit size.

Abstract: A transconductance amplifier mirror circuit is connected to an electrode for sensing the capacitance of the electrode with reference to ground, or the capacitance between the electrode and another electrode. A voltage level change is produced on the electrode connected to the transconductance amplifier mirror circuit to cause the transconductance amplifier mirror circuit to supply charges to or drain charges from a charge calculation circuit. The charge amount variation is converted to a signal for calculating the sensed capacitance.

Abstract: Matched bipolar transistor pairs for use in differential transistor pair circuitry, current mirror transistor pair circuitry and voltage reference transistor pair circuitry are disclosed. Each transistor in the pair includes a base, emitter and a collector region and a doped polysilicon emitter contact, a metal emitter contact and an metal emitter interconnect which makes an electrical connection to the emitter region by way of the metal emitter contact and the polysilicon emitter contact. The metal emitter interconnect is displaced latterly away from the emitter region so that no part of the metal emitter interconnect overlies any portion of the emitter region.

Abstract: The disclosure relates to an electronic differential amplification device integrated on a semiconductor chip. The device may include first and second transistors having respective source terminals connected to a first potential, and drain terminals to receive a first differential current signal. The device may include third and fourth transistors having respective source terminals connected to the first potential, and drain terminals to provide a second differential current signal to a load obtained by amplifying the first signal. The third and fourth transistors may have a respective gate terminal connected to the drain terminal of the first and the second transistors, respectively, in order to form current mirrors with the latter.

Abstract: An operational amplifier circuit includes: a first differential amplifier section containing a P-type differential pair of P-type transistors; a second differential amplifier section containing an N-type differential pair of N-type transistors; an intermediate stage connected with outputs of the first and second differential amplifier sections and containing a first current mirror circuit of P-type transistors, and a second current mirror circuit of N-type transistors; and an output stage configured to amplify an output of the intermediate stage in power. The first differential amplifier section includes a first current source and a first capacitance between sources of the P-type transistors of the P-type differential pair and a positive side power supply voltage. The second differential amplifier section includes a second current source and a second capacitance between sources of the N-type transistors of the N-type differential pair and a negative side power supply voltage.

Abstract: A differential amplifier has an interpolating function and has: first and second differential pairs including transistors of a first conductivity type; third and fourth differential pairs including transistors of a second conductivity type; first and second current sources providing operating currents to the first and second differential pairs; third and fourth current sources providing operating currents to the third and fourth differential pairs; a first control circuit which controls, in a first operating range where the amounts of currents flowing through the first and second differential pairs become smaller, respectively, a changing point at which the operating current of the first differential pair changes; and a second control circuit which controls, in a second operating range where the amounts of currents flowing through the third and fourth differential pairs become smaller, respectively, a changing point at which the operating current of the fourth differential pair changes.

Abstract: A circuit includes a current mirror circuit and first and second transistors coupled as a differential pair. A first input voltage is provided to a control input of the first transistor. A second input voltage is provided to a control input of the second transistor. The current mirror circuit includes a third transistor, a fourth transistor coupled to the third transistor, and a fifth transistor coupled in series with the fourth transistor. The third transistor provides a current through the differential pair that is proportional to a current through the fourth transistor. A control input of the fourth transistor is coupled between the fifth transistor and a source of current.

Abstract: An output circuit includes a differential amplifier circuit, an output amplifier circuit, a control circuit, input and output terminals, and first to third supply terminals applied with first to third supply voltages, respectively. The third supply voltage is set a voltage between the first and second supply voltages. The differential amplifier circuit differentially receives signals of the input and output terminals. The output amplifier circuit includes first and second transistors of different conduction type each other coupled in series between the first and third supply terminals via the output terminal, and having control terminals coupled to first and second output nodes of the differential amplifier circuit, respectively. The control circuit includes a third transistor and a switch, and controls the third transistor being in a diode coupling mode between the first supply terminal and the control terminal of the first transistor for a given period of the output period.

Abstract: A current mode power amplifier includes a current steering stage configured to steer a scaled current based on differential voltage inputs, a filtered current mirror connected to the current steering stage to receive the scaled current and produce a filtered output current, and a resonant load configured to receive the output current and generate an output voltage signal for transmission.

Abstract: A differential amplifier circuit includes: P-type and N-type differential input units outputting respectively first and second outputs in response to first and second input voltages; a P-type current mirror circuit driven by the second output; an N-type current mirror circuit driven by the first output; an output unit outputting an output voltage in response to control outputs from the P-type and N-type current mirror circuits; a first sub-current source including first and second P-type transistors connected in series; and a second sub-current source including first and second N-type transistors connected in series. Control ends of the second P-type and second N-type transistors receive the control outputs from the P-type and N-type current mirror circuits, respectively. Control ends of the first P-type and first N-type transistors are coupled to a common node between the first and second P-type transistors, and a common node between the first and second N-type transistors, respectively.

Abstract: Various apparatuses, methods and systems for boosting an amplifier slew rate are disclosed herein. For example, some embodiments of the present invention provide an apparatus including a pair of inputs connected to a pair of differential input devices in an amplifier, a current source, a first current path connected to the current source, a second current path connected to the current source and to the pair of differential input devices, a switch in the first current path, and a voltage difference signal connected between the pair of inputs and the switch. The voltage difference signal represents the voltage difference between the pair of inputs. The conductance of the switch is inversely proportional to the voltage difference signal.

Abstract: A digital output sensor includes a sensing structure that outputs a differential sensing signal and includes at least one sensing element. An integrated circuit includes a substrate including signal conditioning circuitry for conditioning the sensing signal that includes a differential amplifier coupled to receive the sensing signal and provide first and second differential outputs and a comparator having input transistors coupled to receive outputs from the differential amplifier. The comparator also includes first and second current-mirror loads that provide differential drive currents and are coupled to the input transistors in a cross coupled configuration to provide hysteresis. An output driver is coupled to receive the differential drive currents. An output stage includes at least one output transistor which is coupled to the output driver for providing a digital output for the sensor. A voltage regulator is coupled to receive a supply voltage and output at least one regulated supply voltage.

Abstract: A differential amplifier layout includes a current mirror having a first transistor, a second transistor, and a third transistor. The current mirror receives a first power supply through the first transistor. The second transistor is part of a reference current branch and the third transistor is part of a mirror current branch. The first transistor comprises a first group of fingers disposed adjacent one side of the second transistor and a second group of fingers disposed adjacent one side of the third transistor.

Abstract: An amplifier circuit (100) has an input stage (OP1) and an output stage (Q1, Q2) operating with different supply voltages and different quiescent voltages. The output stage has a feedback input connected to receive a feedback signal from the output of the output stage. A biasing circuit (602) applies a bias signal (Ioff) to said input stage at an operating level appropriate to establish a quiescent output voltage different from a ground reference level of the input stage.

Abstract: In an embodiment of the invention, a differential input signal is coupled to a plurality of transconductance blocks. In some embodiments, each of the transconductance blocks divide an input transconductance among a plurality of signal paths to a plurality of outputs in each transconductance block. In an embodiment, the input transconductance may be divided based a ratio of transistor areas in the plurality of signal paths, though other embodiments may divide the transconductance differently. In some embodiments, transconductance block outputs of a plurality of transconductance blocks may be cross-coupled to provide a gain path for a differential signal than is greater than that of a common mode signal.

Abstract: A circuit provides a first current corresponding to the differential input Inn and Inp, and a second current corresponding to the common mode input Vcm. The circuit then mirrors the differential current and the common mode current to a third current and a fourth current. Based on the difference between the mirrored differential current and the mirrored common mode current, the circuit pulls up or pulls down these currents to balance the corresponding difference between the differential input and the common mode input. In effect, the circuit adjusts the input common mode voltage to a desired level, without providing an opportunity for it to rise to an unwanted level.

Abstract: A differential amplifier circuit includes: P-type and N-type differential input units outputting respectively first and second outputs in response to first and second input voltages; a P-type current mirror circuit driven by the second output; an N-type current mirror circuit driven by the first output; an output unit outputting an output voltage in response to control outputs from the P-type and N-type current mirror circuits; a first sub-current source including first and second P-type transistors connected in series; and a second sub-current source including first and second N-type transistors connected in series. Control ends of the second P-type and second N-type transistors receive the control outputs from the P-type and N-type current mirror circuits, respectively. Control ends of the first P-type and first N-type transistors are coupled to a common node between the first and second P-type transistors, and a common node between the first and second N-type transistors, respectively.

Abstract: A differential amplifier circuit can reduce consumption current and the circuit size while improving a power supply rejection ratio. The differential amplifier circuit includes a power supply line and an input part that includes an input circuit and an active load. The input circuit includes two differential input elements, and the active load includes two transistors connected to the two differential input elements. The input part generates a differential signal in response to an input signal given to the two differential input elements. The differential amplifier circuit also includes an amplifying part for generating an output voltage generating signal by amplifying the differential signal. The differential amplifier circuit also includes an output part for generating an output voltage based on the output voltage generating signal and a power supply voltage.

Abstract: An LNA circuit for providing a wide range of gain while maintaining the output headroom. In a radio frequency (RF) receiver, the signal received by the receiver may be extremely small. For a transmitter in a short distance, the received signal may be relatively strong. A low power amplifier usually is used to amplify the input signal. The LNA has to be designed to accommodate a wide range of gain. A convention LNA circuit supporting a wide range of gain often suffers from reduced output headroom due to increased current through the load resistor. The present invention discloses the use of current bleeding branch to allow a portion of current to flow through the current bleeding branch and consequently reduces the current that would have flown through the load resistor. Consequently, the voltage across the load resistor may be maintained low to allow adequate output headroom.

Abstract: The amplifier circuit (1) includes a differential pair of PMOS transistors at input (P3, P4), whose source receives a current from a current source (3). The gate of the first transistor (P3) of the pair defines a non-inverting input (XOUT) and the gate of the second transistor (P4) of the pair defines an inverting input (XIN). A drain of the first transistor (P3) of the differential pair is connected to a diode connected NMOS transistor (N2) of a first current mirror (N1, N2), and a drain of the second transistor (P4) of the differential pair is connected to a diode connected NMOS transistor (N3) of a second current mirror (N3, N4).

Abstract: An amplifier arrangement comprises a first transistor (18), a first bias transistor (13) and a first field-effect transistor (51). A first input signal (VN) is supplied for amplification to a control terminal of the first transistor (18). The first bias transistor (13) is coupled to the first transistor (18) via a first node (12). The first field-effect transistor (51) is coupled for clamping of a first node voltage (V1) provided at the first node (12).

Abstract: Provided is an output buffer for a source driver of an LCD with a high slew rate, and a method of controlling the output buffer. The output buffer, which outputs a source line driving signal for driving a source line of the LCD, includes: an amplifier section amplifying an analog image signal; an output section outputting the source line driving signal in response to a signal amplified by the amplifier section; and a slew rate controller section, setting a capacitance of a capacitor section to a first capacitance, during a first charge sharing period in which the source line is precharged to a first precharge voltage, setting the capacitance of the capacitor section to a second capacitance smaller than the first capacitance during a second charge sharing period in which the source line driving signal is supplied to the source line, and setting the capacitance of the capacitor section to the first capacitance while the source line driving signal is maintained after the second charge sharing period.

Abstract: An amplifier capable of operating in multiple modes may include (a) first and second voltage inputs and (b) first and second current outputs that have substantially the same amplitude and polarity. Preferably, the inputs and outputs of the amplifier will have high impedances. The amplifier may operate in a first mode—and function as an operational amplifier—when the first and second current outputs are coupled together. The amplifier may operate in a second mode—and function as a type-2 current conveyor—when the second current output is coupled to the second voltage input. The amplifier may additionally include a third current output that has an amplitude that is substantially the same as the amplitudes of the first and second outputs and a polarity that is substantially opposite to the polarities of the first and second outputs. In this configuration the amplifier may function as a four-terminal floating nullor.

Abstract: A folded cascode differential amplifier includes a high-voltage input stage and a low-voltage output stage. The input stage is formed from high-voltage MOS transistors, two of which constitute a differential pair. The output stage is formed from low-voltage MOS transistors, some of which constitute a current mirror circuit connected to the differential pair. The output stage also includes at least one transistor that amplifies a voltage produced in the current mirror circuit to generate an output voltage signal. The high-voltage MOS transistors have higher breakdown voltages than the low-voltage MOS transistors. Incorporation of both types of transistors into a single amplifier reduces the necessary number of transistors and the necessary number of bias voltages.

Abstract: An error amplifier expected to exhibit rail-to-rail operation, high bandwidth, and high slew rate, is described, the error amplifier comprising a first stage to receive an input differential voltage and to provide transconductance gain, an intermediate stage to provide current gain, and an output stage to drive a load.

Abstract: The invention relates to a transconductance amplifier, intended to supply current variations di when it receives voltage variations dv, with a desired conversion coefficient Gm called transconductance: Gm=di/dv. The amplifier comprises a PMOS transistor (MP1) and an NMOS transistor (MP2) connected by their drains, their gates both being connected to the voltage input receiving dv; the source of the first transistor is connected to a constant current source (IB1) and to a resistor (R) and to the drain of a third MOS transistor (MN3) of the same type as the first; the sources of the second (MN2) and third (MN3) transistors are commoned, the gate of the third transistor being connected to the drains of the first and second; the output is connected to a circuit (MN4) which mirrors the current of the third transistor. The resulting amplifier has good linearity and can be used in a sample and hold device used to sample charges.

Abstract: An amplifier is provided. The amplifier includes a differential amplifier including a tail, a current mirror connected between output terminals of the differential amplifier and a power line receiving a supply voltage, and a first switching circuit for connecting and disconnecting one of the output terminals of the differential amplifier to and from the tail in response to a first switching signal.

Abstract: A circuit for power amplification of an input signal includes an input stage and an output stage, the said input stage including: a drive means incorporating a so-called main drive transistor, and a first so-called main input transistor able to receive the input signal, and mounted as a current mirror with the main drive transistor. The first main input transistor is coupled to the output stage via a second so-called main input transistor incorporated into the input stage and controlled by the drive means, the first and second main input transistors being coupled together and with the earth according to a structure of Darlington type by way of a resonant circuit.

Abstract: The present invention is intended to achieve a transconductance amplifier and a voltage/current converting method which can provide a sufficient amplitude and a high degree of design freedom. The method comprises the steps of converting a first voltage signal to a first current signal; converting a second voltage signal to a second current signal; obtaining the common-mode components of the first and second current signals; and subtracting the common-mode components from the first and second current signals to obtain third and fourth signals, and further, subtracting the fourth current signal from the third current signal to generate a first output, while subtracting the third current signal from the fourth current signal to generate a second output.

Abstract: Provided is a differential amplifier circuit in which an offset voltage is independent from input voltages. A first correction current generation circuit and a second correction current generation circuit are provided and configured to cause the same current as a current flowing through a folded cascode amplifying stage to flow into an output stage. Accordingly, transistors included in the folded cascode amplifying stage and transistors included in the output stage have the same bias condition.

Abstract: A semiconductor integrated circuit receives an input current, and supplies, to a different circuit, an output current that corresponds to the input current. A first terminal of a first variable resistor is connected to an input terminal. A first transistor and a second transistor are sequentially arranged in series between a power supply terminal and a second terminal of the first variable resistor. A third transistor and a fourth transistor are sequentially arranged in series between the power supply terminal and an output terminal. The gates of the first transistor and the third transistor are each connected to the second terminal of the first variable resistor. The gates of the second transistor and the fourth transistor are each connected to the input terminal. The first variable resistor is configured to be capable of switching the resistance value thereof according to the input current.

Abstract: A display device is provided with a plurality of differential amplifiers associated with a plurality of data lines within a display panel. Each of the plurality of differential amplifiers includes: an output stage circuit including a first transistor having a source connected to the positive power supply and a second transistor having a source connected to the negative power supply, an output terminal connected to drains of the first and second transistors; and a bias control circuit provided between the adder circuit and the output stage circuit to achieve bias control of gates of the first and second transistors. During the switching period, the output stage circuit provides short-circuiting between the gate and source of each of the first and second transistors, and the bias control circuit cuts off a current path between the gates of the first and second transistors during the switching period.