Abstract: A sense-amplifier circuit of a memory, which includes a sense-amplifier unit, a first switch unit and a second switch unit. The sense-amplifier unit is constituted by a plurality of transistor switches and having a first, a second, a third and a fourth connection terminal. The first switch unit is configured to be parallel coupled between the first and second connection terminals of the sense-amplifier unit. The second switch unit is configured to be parallel coupled between the third and fourth connection terminals of the sense-amplifier unit. The first and second switch units each are constituted by a plurality of transistor switches coupled in parallel and are configured to control each of the parallel-coupled transistor switches on or off in the first and second switch units so as to calibrate a sensing range of the sense-amplifier unit. A calibrating method for a sense-amplifier circuit of a memory is also provided.

Abstract: In an operational amplifier, a control unit switches an operation mode between first and second operation modes. A first output drive stage circuit section is configured to amplify a first input signal differentially-amplified by a first or a second input differential stage circuit section to output as a first drive voltage, similar to a second output drive stage circuit section. First and second power supplies: supply voltages in a first voltage range to the first differential stage circuit section and the first output drive stage circuit section in the first operation mode, supply voltages in the first voltage range to the second differential stage circuit section and the first output drive stage circuit section in the second operation mode, similar to third and fourth power supplies. The drive voltage on each of the first and second output nodes is fed back.

Abstract: A differential amplifier comprises a first amplifier (A1) with a signal input (Inp) and a signal output (Out1) that is fed back to a first feedback input (In1) of the first amplifier (A1) and is also connected to a first output (outp) of the differential amplifier. Furthermore, a buffer circuit (Buff) is connected to the first output (outp). A nonlinear resistor circuit (Rnl1, Rnl2) is coupled via a first output node (Vmid1) with the first output (outp) and via a second output node (Vmid2) with the buffer circuit (Buff).

Abstract: A signal amplification circuit includes a differential amplifier configured to receive a first signal and a second signal and generate an output signal, a differential amplifier configured to receive first and second signals and generate an output signal; and a controller configured to control an amount of current flowing in the differential amplifier using the output signal.

Abstract: A system for a feedback transimpedance amplifier with sub-40 khz low-frequency cutoff is disclosed and may include amplifying electrical signals received via coupling capacitors utilizing a transimpedance amplifier (TIA) having feedback paths comprising source followers and feedback resistors. The feedback paths may be coupled prior to the coupling capacitors at inputs of the TIA. Voltages may be level shifted prior to the coupling capacitors to ensure stable bias conditions for the TIA. The TIA may be integrated in a CMOS chip and the source followers may comprise CMOS transistors. The TIA may receive current-mode logic or voltage signals. The electrical signals may be received from a photodetector, which may comprise a silicon germanium photodiode and may be differentially coupled to the TIA. The chip may comprise a CMOS photonics chip where optical signals for the photodetector in the CMOS photonics chip may be received via one or more optical fibers.

Abstract: A differential amplifier has an interpolating function and has: first and second differential pairs including transistors of a first conductivity type; third and fourth differential pairs including transistors of a second conductivity type; first and second current sources providing operating currents to the first and second differential pairs; third and fourth current sources providing operating currents to the third and fourth differential pairs; a first control circuit which controls, in a first operating range where the amounts of currents flowing through the first and second differential pairs become smaller, respectively, a changing point at which the operating current of the first differential pair changes; and a second control circuit which controls, in a second operating range where the amounts of currents flowing through the third and fourth differential pairs become smaller, respectively, a changing point at which the operating current of the fourth differential pair changes.

Abstract: There is provided a bias circuit that can operate even at low voltage and control a current reflecting a change in drain voltage. A first current mirror circuit for feeding back a drain terminal current of an FET which receives an output of an operational amplifier at a gate terminal to an input terminal of the operational amplifier and a second current mirror circuit are coupled in parallel. A variable voltage is coupled to the first current mirror circuit, and a fixed voltage is coupled to the second current mirror circuit. Even if the variable voltage becomes lower than the threshold voltage of FETs configuring the first current mirror circuit, the second current mirror circuit feeds back the current to the input terminal of the operational amplifier with reliability.

Abstract: An operational amplifier circuit is provided. The operational amplifier circuit includes a differential amplifier of a cascade structure and a switched-capacitor type Common-Mode FeedBack (CMFB) circuit. The differential amplifier amplifies a difference between two input signals to output an anode output voltage and a negative output voltage. The switched-capacitor type CMFB circuit averages the anode output voltage and the negative output voltage of the differential amplifier, compares the average voltage with a reference voltage to generate a feedback signal based on a result of the comparison, and provides the feedback signal to the differential amplifier. Therefore, power consumption is reduced and a battery use time of a wireless terminal can be extended. Also, since an operational amplifier gain of each analog filter terminal is not negatively affected, a Direct Current (DC) offset is reduced, thereby improving signal quality.

Abstract: Some embodiments of the invention relate a transimpedance amplifier circuit having a negative feedback network that provides additional filtering of an out-of-band transmitted signal is provided herein. In one embodiment, the transimpedance amplifier circuit has a first pole, transimpedance amplifier having a multi-stage operational amplifier with an input terminal and an output terminal. An RC feedback network extends from the output terminal to the input terminal. A negative feedback network, extending from an internal node of the multi-stage operational amplifier to an input terminal of the single pole, transimpedance amplifier provides a negative feedback signal with an amplitude having an opposite polarity as the out-of-band transmitted signal. The negative feedback signal suppresses the out-of-band-transmitted signals within the demodulator circuit, thereby improving linearity of the transimpedance amplifier circuit.

Abstract: Techniques for designing a highly linear programmable gain amplifier (PGA). In an aspect, the PGA includes a plurality of feedback switches selectively coupling an output of an operational amplifier (op amp) to an input of the op amp via a corresponding series-coupled feedback resistance. The PGA may further include a plurality of input switches selectively coupling an input of the op amp to a PGA input voltage via a corresponding series-coupled input resistance. The switches are designed such that the ratio of on-resistances between any two switches is substantially equal to the ratio of the corresponding series-coupled resistances. In an exemplary embodiment, transistors implementing the switches may be accordingly sized to implement the desired on-resistance ratios.

Abstract: An amplifier system has an amplifier for amplifying a plurality of input signals from a plurality of different channels, and a plurality of demodulators each operatively coupled with the amplifier for receiving amplified input signals from the amplifier. Each demodulator is configured to demodulate a single amplified input channel signal from a single channel of the plurality of different channels. The system thus also has a plurality of filters, coupled with each of the demodulators, for mitigating the noise.

Abstract: A signal filter circuit, an amplifier circuit, combinations thereof and methods for configuring and using the same are provided. Embodiments of the amplifier circuit may provide precise reproduction and amplification of input signals. The amplifier may be built entirely with discrete components or an integrated circuit may be configured to provide some or all of the modules included in the amplifier.

Abstract: A low noise amplifier with back-to-back connected diodes and a back-to-back connected diode with high impedance thereof are provided. The low noise amplifier includes a first operational amplifier (OP) and at least two first back-to-back connected diodes. The back-to-back connected diode with high impedance is formed from at least one MOS FET operated within a cut-off region. The first back-to-back connected diodes are connected electrically between the first input end and the first output end, and between the second input end and the second output end, of the first OP respectively. By the implementation of the present invention, the low noise amplifier is not only low noise, but also with low energy consumption, high stability, low circuitry complexity, and easily controlled manufacturing process.

Abstract: In aspects of the invention, at normal operation, an operational amplifier circuit has feedback applied from the output thereof to the input thereof so that currents equal to each other flow in differential pair transistors, respectively. While, in order that currents equal to each other may flow in the differential pair transistors, respectively, for compensating the difference in threshold voltages in the differential pair transistors, a voltage lower by a certain voltage difference than the voltage applied to the gate terminal of the transistor must be applied to the gate terminal of the transistor. From this, the switching of switches, when a virtual short circuit occurs, can make the output voltage of the operational amplifier circuit become a signal in which positive and negative rectangular ripples, with the values thereof being proportional to the value of the certain voltage difference, are superimposed on a true value.

Abstract: A differential amplifier circuit includes a first/second field effect transistor including a gate coupled to a first/second differential input signal terminal, a source coupled to a reference potential node, and a drain coupled to a first/second differential output signal terminal, a first variable capacitor coupled between the gate of the first field effect transistor and the drain of the second field effect transistor, a second variable capacitor coupled between the gate of the second field effect transistor and the drain of the first field effect transistor, and a first envelope detector configured to detect an envelope of a signal at the first differential output signal terminal or the second differential output signal terminal, the first variable capacitor and/or the second variable capacitor has a capacitance that varies in accordance with an envelope detected by the first envelope detector.

Abstract: A fully differential operational amplifier includes a differential input stage, at least one output stage and a common-mode feedback circuit connected with the input stage. The differential input stage includes a differential pair of transistors and a bias circuit for the differential pair of transistors. A start-up circuit operates to detect an operating condition of the differential pair of transistors of the input stage and in response thereto turn on the bias circuit.

Abstract: A reference buffer amplifier within an integrated circuit includes a first output terminal connected to a first bond pad, the first bond pad being connected to a first external pin of the integrated circuit chip, the first external pin to allow an external capacitance to be connected to the output terminal. The reference buffer further includes a variable, settable resistance sub-circuit connected to a second bond pad, the second bond pad also being connected to the first external pin. The resistance sub-circuit is configured to be set to exhibit a resistance value to critically dampen a response of the reference buffer amplifier.

Abstract: A differential voltage sensing method for achieving input impedance matching comprises the steps of: providing a first bio-potential signal to a first variable resistor for generating a first signal; providing a second bio-potential signal to a second variable resistor for generating a second signal; differentially amplifying first and second signals for generating a third signal; selecting an operation band of the third signal for generating first and second logic signals; and dynamically adjusting one of the impedances of the first and second variable resistors according to the first and second logic signals, wherein each of the first and second bio-potential signals has a common signal voltage level and a differential signal voltage level.

Abstract: A current-mode analog baseband apparatus is provided. The apparatus includes a current-mode low-order filter, a current-mode programmable gain amplifier (PGA) unit and a high-order filter. The input impedance is smaller than the output impedance in the current-mode low-order filter. An input terminal of the current-mode PGA unit is connected to an output terminal of the current-mode low-order filter. An input terminal of the high-order filter is connected to an output terminal of the current-mode PGA unit.

Abstract: A fast settling reference voltage buffer and method are disclosed. In one of embodiments, An apparatus comprising: an OTA (operational trans-conductance amplifier) with a positive input terminal coupled to a reference voltage, a negative input terminal coupled to a feedback node, and an output terminal coupled to a circuit node shunt to ground by a shunt capacitor via a current sensor; a tunable resistor, controlled by a control signal, coupling the circuit node to the feedback node; a load circuit coupled to the feedback node via a switch controlled by a logical signal; and a control circuit for receiving an output of the current sensor and outputting the control signal, wherein the control signal is adapted in accordance with the output of the current sensor.

Abstract: A high-voltage driver amplifier for piezo haptics comprises an input amplifier having a gain greater than one, a first amplifier of an amplifier pair coupled to an output of the input amplifier, a second amplifier of the amplifier pair coupled to the output of the input amplifier, a first impedance coupled between an output of the first amplifier of the amplifier pair and an input of the input amplifier, and a second impedance coupled between the output of the first amplifier of the amplifier pair coupled to an output of the second amplifier of the amplifier pair. A substantially capacitive load is coupled to the output of the second amplifier. The substantially capacitive load is a piezo-capacitance, wherein the piezo-capacitance is employed in haptics. The second impedance, a shunt impedance, allows for a feedback of output variations between the first amplifier and the second amplifier over the first impedance.

Abstract: A differential amplifier circuit can reduce consumption current and the circuit size while improving a power supply rejection ratio. The differential amplifier circuit includes a power supply line and an input part that includes an input circuit and an active load. The input circuit includes two differential input elements, and the active load includes two transistors connected to the two differential input elements. The input part generates a differential signal in response to an input signal given to the two differential input elements. The differential amplifier circuit also includes an amplifying part for generating an output voltage generating signal by amplifying the differential signal. The differential amplifier circuit also includes an output part for generating an output voltage based on the output voltage generating signal and a power supply voltage.

Abstract: An operational amplifier includes an input differential stage having one external input receiving an external input voltage and two outputs; and two output stages. A switch section is provided between inputs of the two output stages and the two outputs of the input differential stage, and is configured to alternately connect the two outputs of the input differential stage and inputs of a positive-only output stage of the two output stages; and the two outputs of the input differential stage and inputs of a negative-only output stage of the two output stages.

Abstract: An analog-to-digital converter (ADC) circuit comprising two time-interleaved successive approximation register (SAR) ADCs. Each of the two time-interleaved SAR ADCs comprises a first stage SAR sub-ADC, a residue amplifier, a second stage SAR sub-ADC and a digital error correction logic. The residue amplifier is shared between the time-interleaved paths, has a reduced gain and operates in sub-threshold to achieve power effective design.

Abstract: A voltage level shifter for a direct coupling of an external voltage source to a common mode of a circuit may include an amplifier, a voltage-controlled current source, a first and second resistors. A first input of the amplifier may be connected to the common mode. A second input of the amplifier may, via the first and second resistors, receive a voltage indicative of the external voltage source. The output of the amplifier may indicate a voltage difference between the first and second inputs. The voltage-controlled current source may be controlled by the voltage difference to supply a current to a common node of the first and second resistors so that the voltage difference between the first and second inputs may be minimized.

Abstract: In one embodiment, the present invention includes a mixer having various stages, including a transconductance stage with a differential transistor pair, a bias circuit, and a feedback circuit. The transistor pair can include a first transistor having a first terminal to receive a first input radio frequency (RF) voltage and to output a first RF current via a second terminal of the first transistor, and a second transistor having a first terminal to receive a second input RF voltage and to output a second RF current via a second terminal of the second transistor. In turn, the bias circuit is coupled to the second terminals of the transistors to provide a bias current to these transistors. The feedback circuit is in turn coupled to the second terminals of the transistors to generate a feedback signal corresponding to a common mode voltage at the second terminals of the transistors.

Abstract: A limiting amplifier and method are provided. In one implementation an apparatus includes a plurality of amplifier stages including a first amplifier stage and a last amplifier stage configured in a cascade arrangement, and a transconductance amplifier, wherein the first amplifier stage is configured to receive an input signal; the last amplifier stage outputs an output signal; the transconductance amplifier is configured receive a voltage signal from the last amplifier stage via a first resistor; and the transconductance amplifier is configured to output a current signal to an output node of the first amplifier stage via a second resistor in a negative feedback manner.

Abstract: A circuit includes a transimpedance amplifier portion having a first input node and a second input node, and a feedback circuit portion comprising a first transistor having a drain terminal connected to the first input node, a source terminal, and a gate terminal, a second transistor having a drain terminal connected to the second input node, a source terminal, and a gate terminal, and a third transistor having a drain terminal connected to the source terminal of the first transistor and the source terminal of the second terminal.

Abstract: An isolation circuit includes a low dropout operational current control loop and a shunt regulator. The current control loop is configured to drive the shunt regulator to result in a high dynamic impedance ratio between a voltage source and a load. The current control loop may include a series-pass transistor, a current sensing resistor, and a high side current sensor.

Abstract: An analog floating gate circuit (10-3, 10-4) includes a first sense transistor (21, 3), a first storage capacitor (20, 5), and first (24, 4) and second (31A, 42) tunneling regions. Various portions of a first floating gate conductor (12, 2) form a floating gate of the first sense transistor, a floating first plate of the first storage capacitor (20, 5), a floating first plate of the first tunneling region, and a floating first plate of the second tunneling region, respectively. A second plate of the first storage capacitor is coupled to a first reference voltage (VREF, GND), and a second plate of the second tunneling region is coupled to a second reference voltage (VPROG/GND). Compensation circuitry (44-1, 44-2) is coupled to the first floating gate conductor, for compensating loss of trapped charge from the first floating gate conductor.

Abstract: The invention relates to a configurable low noise amplifier circuit which is configurable between a first topology in which the low noise amplifier circuit includes a degeneration inductance whereby the low noise amplifier circuit operates as an inductively degenerated low noise amplifier, and a second topology in which the low noise amplifier circuit includes a feedback resistance whereby the low noise amplifier circuit operates as a resistive feedback low noise amplifier.

Abstract: A power amplifying circuit includes first and second operational amplifiers. The power amplifying circuit includes first to fourth feedback resistor. The power amplifying circuit includes a fully differential operational amplifier that is connected to the output terminal of the first operational amplifier at a non-inverting input terminal thereof, to the output terminal of the second operational amplifier at an inverting input terminal thereof, to a first signal output terminal at a non-inverting output terminal thereof, and to a second signal output terminal at an inverting output terminal thereof and maintains a constant differential gain. The power amplifying circuit includes a switching circuit. The power amplifying circuit includes first and second input resistors. The power amplifying circuit includes a midpoint potential controlling circuit that monitors a power supply voltage and controls the switching circuit.

Abstract: An amplifier is arranged to receive an input signal and provide an output signal in response, and includes a main amplifier core and an auxiliary circuit. The main amplifier core includes an input node, an output node and a sum node with the input node coupled to the input signal, and is arranged to provide an interior signal to the sum node and output the output signal at the output node in response to signals provided to the sum node. The auxiliary circuit is coupled between the input node and the sum node, and is arranged to match an impedance of the input node and provide a cancelling signal to the sum node in response to the input signal. An associated receiver is also disclosed.

Abstract: An output buffer and a source driver for a display panel are provided. The output buffer includes a differential input stage, a bias current source, a feedback module, and an output stage. The differential input stage has a first input terminal and a second input terminal receiving a first input signal and a second input signal respectively, and a first output terminal. The bias module provides a bias current to the differential input stage. The output stage has a second output terminal coupled to the first input terminal for providing an output current to the second output terminal based on a signal of the first output terminal. The feedback module adjusts the bias current and the output current based on the first input signal and the second input signal. The output buffer has ability of switching the output voltage to be low level and high level in high-speed.

Abstract: Disclosed herein is an amplifier including a voltage follower circuit having differential input terminals and an output terminal fed back to a first one of the differential input terminals, the voltage follower circuit being configured to amplify an input signal inputted to a second one of the differential input terminals and output the amplified signal from the output terminal; a first current source configured to supply a predetermined current to the voltage follower circuit; and a second current source configured to supply current to the voltage follower circuit when a potential difference between the second one of the differential input terminals and the output terminal is equal to or higher than a predetermined value.

Abstract: According to an embodiment, a system for amplifying a signal provided by a capacitive signal source includes a first stage and a second stage. The first stage has a voltage follower device including an input terminal configured to be coupled to a first terminal of the capacitive signal source, and a first capacitor having a first end coupled to an output terminal of the capacitive signal source. The second stage includes a differential amplifier capacitively coupled to the output terminal of the voltage follower device.

Abstract: An operational amplifier may include a transimpedance input stage. The operational amplifier is capable of self-biasing its input voltage(s) including a first stage, an input source connected to the first stage, an output stage connected to the first stage via feedback resistors, and feedback current sources connected to the first stage, wherein the feedback current sources are set to generate feedback currents flowing from the output stage back to the input stage via the feedback resistors, so as to self-bias the input voltage(s) at the input stage. A method for allowing for an op-amp to self-bias its input voltage(s), including generating feedback currents flowing from the output stage back to the input stage via feedback resistors, so as to self-bias the input voltage(s) at the input stage.

Abstract: There is provided a high-frequency differential amplifier circuit comprising: a first MOS transistor, a second MOS transistor, a first positive feedback element and a second positive feedback element. The first MOS transistor and the second MOS transistor each has a source connected to a first power source and a drain connected through loads to a second power source. The first and second MOS transistors receives at their gates, first and second input signals having phases reverse to each other. The first positive feedback element includes a first capacitor and a first variable resistance connected in series between the gate of the first MOS transistor and the drain of the second MOS transistor. The second positive feedback element includes a second capacitor and a second variable resistance connected in series between the gate of the second MOS transistor and the drain of the first MOS transistor.

Abstract: A method of configuring a FET amplifier with two inputs demonstrating similar-phased response to similar-phased inputs. One input can be used as a feedback path in suitable amplifier circuits, improving frequency performance by decreasing feedback resistance. The second input provides the means for a high impedance connection to a drive signal. The present invention is particularly applicable to applications involving constant voltage sources and constant current active sources with or without cascoding, in both single-ended and differential configurations.

Abstract: A differential amplifier including an input of a balanced type relative to a reference potential; a balanced output; first and second bipolar transistors mounted in common emitter configuration, emitters of the first and second transistors linked by two feedback impedances in series; and a perfect current generator, wherein an impedance Zg at the terminals of the current generator is connected between a common point of the two feedback impedances and the reference potential, the input is connected to a base of the first transistor, a base of the second transistor is linked to the reference potential to form, with a base of the first transistor, the unbalanced input, the balanced output is produced by collectors of the first and second transistors through an impedance matching stage of the output, a correction feedback impedance Zcorr, wherein Zcorr=2·Zg, connects the collector of the second transistor and the base of the first transistor.

Abstract: To eliminate the substrate voltage dependences of the respective resistance values of resistor elements, in the resistor elements coupled in series to each other over respective substrate regions, the ends of the resistor elements are coupled to the corresponding substrate regions by respective bias wires such that respective average potentials between the substrate regions of the resistor elements and the corresponding resistor elements have opposite polarities, and equal magnitudes.

Abstract: A switched-capacitor DC blocking amplifier is disclosed. In an embodiment, an integrated circuit is provided that includes an amplifier having an amplifier input and an amplifier output, a capacitor connected to the amplifier input and configured to receive an input signal, and a switched capacitor circuit coupled to provide a resistance between the amplifier input and the amplifier output. In one implementation, the switched capacitor circuit is configured with a feed forward circuit to reduce aliasing. In another implementation, the switched capacitor circuit includes a switched impedance circuit to reduce noise.

Abstract: A method for providing common-mode feedback is provided. A common-mode current is applied to a common-gate amplifier, and the common-mode current is sensed. In response to the sensed common-mode current, a control voltage is generated. A first feedback current (which is generated in response to the control voltage) can then be applied to differential ground of the common-gate amplifier if the common-mode current is less than a predetermined threshold. Additionally, a second feedback current (which is generated in response to the control voltage) can be applied to input terminals of the common-gate amplifier if the common-mode current is greater than the predetermined threshold.

Abstract: Circuits, devices and methods are provided, such as an amplifier (e.g., a voltage regulator) that includes a feedback circuit that supplies negative feedback through a feedback path. One such feedback path includes a capacitance coupled in series with a “one-way” isolation circuit through which a feedback signal is coupled. The “one-way” isolation circuit may allow the feedback signal to be coupled from a “downstream” node, such as an output node, to an “upstream” node, such as a node at which an error signal is generated to provide negative feedback. However, the “one-way” isolation circuit may substantially prevent variations in the voltage at the upstream node from being coupled to the capacitance in the isolation circuit. As a result, the voltage at the upstream node may quickly change since charging and discharging of the capacitance responsive to voltage variations at the upstream node may be avoided.

Abstract: A power amplifier for amplifying a signal includes: an operation amplifier stage, at least one buffer stage and an output stage which are consecutively connected with each other; a first feedback unit connected between an output end of the output stage and a negative input end of the operation amplifier stage; a second feedback unit connected between an input end of the output stage and the negative input end of the operation amplifier stage; a third feedback unit connected between an input end of the at least one buffer stage and the negative input end of the operation amplifier stage; and feedback signals provided by the first feedback unit, the second feedback unit and the third feedback unit being superposed at the negative input end of the operation amplifier stage.

Abstract: An amplifier with a cascode device contains a common mode feedback circuit to ensure correct operating point in the amplifier. Common mode feedback is provided to the amplifier to maintain the common mode operating point during active operation. Additional common mode feedback is provided to the cascode devices to ensure correct start-up by forcing the node voltages to go to their desired voltage levels.

Abstract: The invention relates to a configurable low noise amplifier circuit which is configurable between a first topology in which the low noise amplifier circuit includes a degeneration inductance whereby the low noise amplifier circuit operates as an inductively degenerated low noise amplifier, and a second topology in which the low noise amplifier circuit includes a feedback resistance whereby the low noise amplifier circuit operates as a resistive feedback low noise amplifier.

Abstract: An amplifier with a cascode device contains a common mode feedback circuit to ensure correct operating point in the amplifier. Common mode feedback is provided to the amplifier to maintain the common mode operating point during active operation. Additional common mode feedback is provided to the cascode devices to ensure correct start-up by forcing the node voltages to go to their desired voltage levels.

Abstract: An operational amplifier may include a transimpedance input stage. The operational amplifier is capable of self-biasing its input voltage(s) including a first stage, an input source connected to the first stage, an output stage connected to the first stage via feedback resistors, and feedback current sources connected to the first stage, wherein the feedback current sources are set to generate feedback currents flowing from the output stage back to the input stage via the feedback resistors, so as to self-bias the input voltage(s) at the input stage. A method for allowing for an op-amp to self-bias its input voltage(s), including generating feedback currents flowing from the output stage back to the input stage via feedback resistors, so as to self-bias the input voltage(s) at the input stage.

Abstract: An integrator circuit cancels a DC offset component related to an average DC value of a burst mode input signal from the output of an amplifier. The integrator circuit outputs an average DC value of the input signal in a response time that is shorter than the preamble of a burst mode signal. The integrator output signal remains stable within selected amplitude limits for a length of time corresponding to the data portion of a burst mode signal. A transimpedance amplifier embodiment of the invention comprises a TIA gain stage, an integrator, and a voltage-controlled current course. Other embodiments comprise an amplifier for converting single-ended input signals to differential output signals, an amplifier for differential output offset cancellation, a monolithic semiconductor integrated circuit die, and a packaged semiconductor integrated circuit device.