Abstract: A complementary balanced low-noise amplifier is disclosed. In one aspect, the low-noise amplifier (LNA) may be a single-ended cascoded complementary common-source LNA that is capable of operating in low-power conditions. In particular, the LNA may include a first path with a common-source amplifier formed from an N-type material and a second path with a common-source amplifier formed from a P-type material that collectively form a complementary common-source amplifier. By providing two paths in the complementary amplifier, headroom may be preserved for output transistors. Additionally, higher-order intercept points (e.g., IP2 or IP3) characteristics have better performance profiles resulting in better overall performance and improved user experience.

Abstract: A signal envelope detector is provided. The signal envelope detector includes an input node configured to receive an input signal. Further, the signal envelope detector includes a capacitive voltage divider coupled to the input node and configured to generate an attenuated input signal by voltage division of the input signal. The signal envelope detector additionally includes a source follower transistor coupled between a first node configured to receive a first voltage supply signal and a second node configured to receive a second voltage supply signal. A gate terminal of the source follower transistor is coupled to the capacitive voltage divider and configured to receive the attenuated input signal. The signal envelope detector includes a rectifier circuit configured to receive and rectify an output signal of the source follower transistor.

Abstract: A power amplifier structure includes at least one power amplifier circuit. The power amplifier circuit includes a transistor of a first type connected in series with a transistor of a second type connected between the same voltage supply. In a non-limiting nonexclusive example, an n-type transistor is connected in series with a p-type transistor connected between Vdd. The power amplifier structure can include two amplifier circuits configured in a differential amplifier structure. The differential amplifier structure includes two amplifier circuits operably connected in parallel between the same voltage supply.

Abstract: An operational amplifier, any of a pair of amplification circuits of its output-stage amplification circuit unit comprises: a first and second transistors, a capacitor and a DC bias circuit; a control electrode of the first transistor is connected with a corresponding output terminal of a preceding-stage amplification circuit unit, a first electrode thereof is connected with a first power terminal and a second electrode thereof is connected with an output terminal of an amplification circuit of the output-stage amplification circuit unit; an output terminal of the DC bias circuit is connected with a control electrode of the second transistor, a first electrode of which is connected with a second power terminal, and a second electrode thereof is connected with the output terminal; both ends of the capacitor are respectively connected with the control electrodes of the first and second transistors; and the first and second transistors are of opposite polarities.

Abstract: Described embodiments include a rectifier circuit comprising a first resistor with first and second resistor terminals, and a second resistor with third and fourth resistor terminals. The first and third resistor terminals are coupled to an auxiliary power terminal. A current source is coupled between the second resistor terminal and a ground terminal. An amplifier has a first amplifier input coupled to the second resistor terminal, and a second amplifier input coupled to the fourth resistor terminal. A first transistor is coupled between the fourth resistor terminal and a damping terminal, and has a first control terminal coupled to the first amplifier output. A gate drive circuit has an input coupled to the damping terminal. A second transistor is coupled between the damping terminal and a bootstrap supply terminal, and has a second control terminal coupled to an output of the gate drive circuit.

Abstract: First and second output transistors are connected in series between a power supply terminal and a ground terminal through an output node connected to an output terminal. An output transistor control circuit is arranged corresponding to at least one of the first and second output transistors and is configured to input a voltage at the output terminal to the gate of the first output transistor at a time of occurrence of disconnection of the power supply terminal and input the same to the gate of the second output transistor at a time of occurrence of disconnection of the ground terminal. The first output transistor has a conductivity type to turn off when a power supply voltage is input to the gate, and the second output transistor has a conductivity type to turn off when a ground voltage is input to the gate.

Abstract: Examples of amplifiers accurately generate control currents for control terminals of output drivers using current-replication transistors and current mirrors. An input terminal of a first current mirror is coupled to the control terminal of a first current-replication transistor, and an input terminal of a second current mirror is coupled to the control terminal of a second current-replication transistor. The output terminals of the first and second current mirrors are coupled to the control terminals of first and second output drivers, respectively. First and second intermediate currents indicative of first and second currents flowing to the first and second output driver elements, respectively, are generated. Using the first and second current mirrors, first and second control currents are generated to control the first and second output driver elements, respectively, by scaling the first and second intermediate currents according to the gain factors of the current mirrors.

Abstract: Examples of amplifiers use current-replication transistors and a separation circuit coupled to such transistors to separate error current components from other current components in a pre-driver of an amplifier. In response to driving the current-replication transistors with the separated error current components, replica base current components that approximate error-modulation components of the pre-driver base currents are generated. Replica-current subtraction circuitry coupled to the current-replication transistors then subtract the replica base current components from the pre-driver base currents, affecting cancellation of the error-modulation components of the pre-driver base currents.

Abstract: Disclosed are a slew boost amplifier and a display driver having the same, which include a first current generation circuit configured to apply a first current to an upper current mirror circuit, a second current generation circuit configured to apply a second current to a lower current mirror circuit, and a comparison circuit configured to detect a difference between an input voltage and an output voltage and to apply the first current when the difference is greater than or equal to a first predetermined threshold and the second current generation circuit to apply the second current when the difference is less than a second predetermined threshold.

Abstract: The present disclosure is to improve the power added efficiency of a power amplifier at high output power. The power amplifier includes: a first capacitor with a radio frequency signal input to one end thereof; a first transistor whose base is connected to the other end of the first capacitor to amplify the radio frequency signal; a bias circuit for supplying bias to the base of the first transistor; and a second capacitor with one end connected to the base of the first transistor and the other end connected to the emitter of the first transistor.

Abstract: A wideband tunable frequency single-subband converter is proposed. The wideband frequency tunable converter operates within a wideband and tunable frequency range, and has process, voltage, and temperature (PVT) tracking capability. In one embodiment, the wideband converter comprises a frequency tunable polyphase filter having a plurality of switchable polyphase resistors. The polyphase resistors are controlled by a frequency tuning control signal to achieve wideband frequency tunability. In a preferred embodiment, a triode mode transistor is used as a polyphase resistor, and a different resistance value of the polyphase filter is realized by turning on one or multiple of the different transistors in triode mode. In addition, a constant Gm(R) bias generator is used to provide the gate biases to the triode mode transistors to maintain a constant and stable resistance value across PVT and other variation.

Abstract: A sensing circuit for an organic light-emitting diode (OLED) driver includes a sample and hold circuit and a clamping circuit. The sample and hold circuit includes a capacitor. The clamping circuit, coupled to the sample and hold circuit, is configured to clamp a sensing voltage received by the sample and hold circuit to conform to a withstand voltage of the capacitor.

Abstract: An amplifier device includes an alternate current (AC) coupling circuit, an amplifier circuit, and a first bias circuit. The amplifier circuit is configured to amplify an input signal to generate an output signal, in which the amplifier circuit includes a first input terminal, and the first input terminal receives the input signal via the AC coupling circuit. The first bias circuit is configured to apply a first bias voltage to the first input terminal according to one of the output signal and a first voltage, such that the amplifier circuit amplifies the input signal to output the output signal.

Abstract: A system for correcting a duty cycle comprises a digital quadrature generator circuit, a frequency doubler circuit, a first duty cycle correction circuit coupled between the digital quadrature generator circuit and the frequency doubler circuit, and a second duty cycle correction circuit coupled between the digital quadrature generator circuit and the frequency doubler circuit. The first duty cycle correction circuit comprises a first stacked duty cycle correction circuit and the second duty cycle correction circuit comprises a second stacked duty cycle correction circuit.

Abstract: An amplification device comprising: a push pull circuit which amplifies an input signal; a diamond buffer circuit to which the signal which is amplified by the push pull circuit is input; and a current mirror circuit which is connected to a power supply and the diamond buffer circuit and is connected to a retraction current terminal of the push pull circuit.

Abstract: A power amplifier and method for operating the same is disclosed. The amplifier includes a number of transistors coupled in series between a power node and a ground node. These transistors include a first transistor having a source terminal coupled to the power node, and a second transistor having its source terminal coupled to a ground node. A subset of transistors is also coupled in series between the first and second transistors. During operation in a first mode, the first and second transistors act as switching transistors, switching according to data received thereby. The subset of transistors, during the first mode, act as cascode transistors. During a second mode of operation, the transistors of the subset act as switching transistors, switching in accordance with the received data.

Abstract: A multi-stage radio frequency power amplifier (RFPA) includes an output stage SMPA and a driver stage SMPA. As the multi-stage RFPA operates, the magnitude of an RF switch drive signal generated by the driver stage SMPA is dynamically minimized based on I-V characteristic curves of the output stage SMPA's power transistor and the output stage SMPA's dynamically changing load line. By constraining the magnitude of the RF switch drive signal as the multi-stage RFPA operates, VGS feedthrough of the RF switch drive signal is minimized, to the extent possible. Amplitude distortion and phase distortion in the RF output that might occur due to unconstrained VGS feedthrough, particularly at low output RF power levels, are therefore avoided. Operating all stages of the multi-stage RFPA in switch mode also results in high energy efficiency and an output RF spectrum with very low wideband noise (WBN).

Abstract: The present invention reveals a new biasing method which can be used in solid state audio power amplifier design despite of the Class of operation. The proposed biasing technology relies only on traditional electrical feedback to build up and maintain the desired biasing current and doesn't need thermal coupling or thermal tracking techniques in order to overcome power transistor device's temperature dependent input-output characteristics as required by traditional approach. An ingenious current sensing and amplification circuit is devised in order to generate an voltage output which is only corresponding to the quiescent biasing current of the output stage. This voltage output is then used as an representative of the power stage biasing current to be regulated by a feedback loop comprising a traditional voltage multiplier, the output stage and the aforementioned current sensing and amplification circuit.

Abstract: The acoustic energy induced by a transmitter module of an acoustic logging tool is dependent on several factors. In some implementations, the induced acoustic energy is dependent on the electromagnetic energy input into the transmitter module, the response behavior of the transmitter module, and the operating conditions of the transmitter module. Variation in one or more of these factors can result in a corresponding variation in the induced acoustic. Thus, a desired acoustic signal can be produced by applying an appropriately selected input signal to the transmitter module, while accounting for other factors that influence the output of the transmitter module.

Abstract: A switch-mode RFPA driver includes first and second field-effect transistors (FETs) arranged in a totem-pole-like configuration. The switch-mode RFPA driver operates to generate a switch-mode RFPA drive signal having a generally square-wave-like waveform from an input RF signal having a generally sinusoidal-like waveform. To maximize high-frequency operation and avoid distorting the switch-mode RFPA drive signal, the switch-mode RFPA driver is designed so that its output can be connected directly to the input of the switch-mode RFPA to be driven, i.e., without using or requiring the use of an AC coupling capacitor. The first and second FETs of the switch-mode RFPA driver are designed and configured to limit and control the upper and lower magnitude levels of the switch-mode RFPA drive signal to levels suitable for switching the switch-mode RFPA directly, obviating any need for DC biasing at the input of the switch-mode RFPA.

Abstract: The present invention relates to a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. In particular, the present invention relates to a solid state device based on a complementary pair of n-type and p-type current field-effect transistors, each of which has two control ports, namely a low impedance port and gate control port, while a conventional solid state device has one control port, namely gate control port. This novel solid state device provides various improvement over the conventional devices.

Abstract: A source follower method, system, and apparatus provide rail-to-rail capability to an output voltage terminal of a voltage follower feedback biased CMOS output circuit by providing a control circuit which includes first and second bypass transistors that are connected in parallel between first and second control circuit input/output terminals and controlled, respectively, by first and second control circuit inputs, and which also includes first and second current sources for injecting source and sink currents in the output node as a function, respectively, of a first bypass current through the first bypass transistor which turns ON when the output voltage rises above a top threshold voltage level and of a second bypass current through the second bypass transistor which turns ON when the output voltage falls below a bottom threshold voltage level.

Abstract: A pseudo resistance circuit is disclosed that is capable of suppressing fluctuation in resistance value with fluctuation in process or temperature and facilitating adjustment. The pseudo resistance circuit includes a first MOSFET, a second MOSFET, a first current source which generates a first current substantially proportional to absolute temperature, and voltage source which generates a first voltage, which is a substantially linear function of absolute temperature. The gate of the first MOSFET and the gate of the second MOSFET are connected together, the second MOSFET is diode-connected, the first current is supplied to the drain of the second MOSFET, the first voltage is applied to the source of the second MOSFET, and a resistor having a resistance value according to the gate voltage of the first MOSFET is formed between the drain and the source of the first MOSFET.

Abstract: An integrated circuit comprises a first amplifier circuit with a push-pull amplifier configured to be calibrated to a low second order distortion. The integrated circuit further comprises a second amplifier circuit with at least one push-pull amplifier, wherein a size ratio between sizes of the transistors is adjustable by adjusting the size of at least one transistor device. The size ratio can be consecutively adjusted to a plurality of values, and for each value, a first output signal of a push-pull amplifier with an applied test signal and a second output signal of a push-pull amplifier without applied test signal, are determined. The size ratio for which a difference between the push-pull amplifier output signals is closest to zero is determined, and the push-pull amplifier of the first amplifier circuit is calibrated in dependence of the determined size ratio.

Abstract: Circuits for power-combined power amplifier array are provided, the circuits comprising: an input splitter coupled to an input that provides a plurality of outputs; a plurality of power amplifier unit cells, each power amplifier unit cell coupled to a corresponding output of the input splitter and each power amplifier unit cell providing an output signal at an output of the power amplifier unit cell; and a power combiner having an output, a plurality of inputs, each input coupled to the output of a corresponding power amplifier unit cell, and a plurality of C-L-C-section equivalents, each having an input connected to a corresponding one of the plurality of inputs of the power combiner and an output connected to the output of the power combiner.

Abstract: A current-bootstrap comparator includes a receiving unit, a first current generation unit and a second current generation unit. The receiving unit receives a load voltage signal, a low threshold voltage and a high threshold voltage. The first current generation unit generates a first current. The second current generation unit generates a second current having a magnitude substantially same as a magnitude of the first current and a direction reverse to the first current. The first current and the second current are supplied to a next-stage circuit as a source current and a corresponding sink current, respectively, when the level of the load voltage signal is higher than the high threshold voltage or lower than the low threshold voltage. The magnitudes of the first current and the second current substantially equal zero when the level of the load voltage signal is between the high threshold voltage and the low threshold voltage.

Abstract: A switch-mode RFPA driver includes first and second field-effect transistors (FETs) arranged in a totem-pole-like configuration. The switch-mode RFPA driver operates to generate a switch-mode RFPA drive signal having a generally square-wave-like waveform from an input RF signal having a generally sinusoidal-like waveform. According to one embodiment of the invention, to maximize high-frequency operation and avoid distorting the switch-mode RFPA drive signal, the switch-mode RFPA driver is designed so that its output can be connected directly to the input of the switch-mode RFPA to be driven, i.e., without using or requiring the use of an AC coupling capacitor. The first and second FETs of the switch-mode RFPA driver are designed and configured to limit and control the upper and lower magnitude levels of the switch-mode RFPA drive signal to levels suitable for switching the switch-mode RFPA directly, obviating any need for DC biasing at the input of the switch-mode RFPA.

Abstract: Systems, methods and apparatus for practical realization of an integrated circuit comprising a stack of transistors operating as an RF amplifier are described. As stack height is increased, capacitance values of gate capacitors used to provide a desired distribution of an RF voltage at the output of the amplifier across the stack may decrease to values approaching parasitic/stray capacitance values present in the integrated circuit which may render the practical realization of the integrated circuit difficult. Coupling of an RF gate voltage at the gate of one transistor of the stack to a gate of a different transistor of the stack can allow for an increase in the capacitance value of the gate capacitor of the different transistor for obtaining an RF voltage at the gate of the different transistor according to the desired distribution.

Abstract: An inductor-less low noise amplifier (LNA) with high linearity is disclosed. The low noise amplifier includes: an input signal stage receiving an input signal; a first amplifier configured to receive the input signal, generate a first amplification signal by amplifying the received input signal, and output the generated first amplification signal, as a first output signal, to a first output terminal; a second amplifier configured to receive the input signal, generate a second amplification signal by amplifying the received input signal, and output the generated second amplification signal, as a second output signal, to a second output terminal; an output signal stage outputting a superimposition signal obtained by superimposing the first output signal and the second output signal; a first resistor feeding back the superimposition signal to the input signal stage; and a switch connecting/disconnecting between the input signal stage and the output signal stage.

Abstract: An integrated circuit with voltage regulator circuitry is provided. The voltage regulator circuitry may include an adaptive bleeder circuit. The adaptive bleeder circuit may include one or more switchable current leaker paths and an associated bleeder control circuit having current sensing circuitry and voltage comparison circuitry. The current sensing circuitry may monitor the amount of current that is being delivered to a load circuit, whereas the voltage comparison circuitry may output control signals that selectively activate one or more of the current leaker paths depending on the monitored current values. Adaptive bleeder circuit configured in this way can help maintain stability of the voltage regulator while minimizing dynamic power consumption.

Abstract: A semiconductor device includes: a depletion-type field-effect transistor including a gate terminal, a drain terminal and a source terminal; a group III-V heterojunction bipolar transistor including a base terminal, an emitter terminal electrically connected to the gate terminal and a collector terminal connected to same potential as that of the source terminal; a first resistor connected between the base terminal and the emitter terminal; and a second resistor connected between the base terminal and the collector terminal.

Abstract: A wideband highly-linear buffer circuit exhibiting a low output impedance comprises a first PFET (PFET1), a second PFET (PFET2), a first NFET (NFET1), and a second NFET (NFET2). Sources of PFET1 and PFET2 are coupled to VDD. PFET1's drain is coupled to an output lead. PFET2 acts as a current source. NFET1's drain is coupled to PFET2's drain and to PFET1's gate. NFET1's source is coupled to the output lead. NFET2's source is coupled to ground. NFET2's drain is coupled to NFET1's source and to the output lead. NFET1's gate is AC coupled to a first input lead. In a single-ended input example, NFET2's gate is AC coupled NFET1's drain. In a differential input example, NFET2's gate is AC coupled to a second input lead. In another differential input example, PFET2 is not just a current source, but rather PFET2's gate is AC coupled to the first input lead.

Abstract: Power amplifier having biasing with selectable bandwidth. In some embodiments, a power amplifier can include an amplifying transistor having a base for receiving a signal to be amplified, and a bias circuit configured to bias the amplifying transistor. The bias circuit can include a reference transistor having a base coupled to the base of the amplifying transistor and a collector coupled to a reference current source. The bias circuit can further include a coupling circuit that couples the collector and the base of the reference transistor. The coupling circuit can include a switchable element configured to allow the coupling circuit to be in a first state to provide a first bandwidth for the bias circuit or a second state to provide a second bandwidth for the bias circuit.

Abstract: In a preamplifier (amplifier) for the radiation detector, an interconnection layer connected to the bonding pad forms one electrode of a feedback capacitor. Since there is no wiring for connecting the bonding pad and capacitor, a parasitic capacitance caused by the wiring will not be generated. Moreover, the capacitor is arranged below the bonding pad with a conductive layer serving as the other electrode, so that the feedback capacitance of the capacitor is included in the parasitic capacitance between the interconnection layer and the substrate. Compared to the conventional case, an amount of capacitance corresponding to the parasitic capacitance caused by wiring and the feedback capacitance for the capacitor is reduced from the input capacitance. Thus, the input capacitance for the amplifying circuit is reduced.

Abstract: Apparatus (301) for switchable attenuation of a differential input signal from a microphone includes positive and negative non-attenuating paths (406, 410) have n- and p-type MOSFETs (421, 422, 423, 424) in back-to-back configurations; positive and negative attenuating paths (405, 409) have n- and p-type MOSFETs (415, 416, 418, 419) in back-to-back configurations in combination with resistors; a gate driver (425) applies a drive signal of one polarity (QNEG) to gates of the n-type MOSFETs in the attenuating paths and the p-type MOSFETs in the non-attenuating paths, and a drive signal of opposite polarity (QPOS) to the gates of the p-type MOSFETs in the attenuating paths and the n-type MOSFETs in the non-attenuating paths; and the state of the MOSFETs depends on the drive signals at their gates, and thus the input signal may be routed via either the non-attenuating paths or the attenuating paths by controlling the drive signals.

Abstract: A current generator includes a first current generation circuit configured to generate a first current having a first current noise which depends on a change in a supply voltage, a second current generation circuit configured to generate a second current having a second current noise which depends on the change in the supply voltage, and a current subtracting circuit configured to generate a third current with the first current noise and the second current noise removed by subtracting the second current from the first current.

Abstract: Representative implementations of devices and techniques provide a speed increase to a comparator circuit. An active clamp device may be positioned between an input stage and an output stage of the comparator, limiting the voltage range of the output of the first stage.

Abstract: A power converter for transmitting a resonance power is provided that includes: an input end that receives a direct current (DC) voltage of a predetermined level; a first power converter that converts the DC voltage of a predetermined level to an alternating current (AC) signal using a first switching pulse signal having substantially the same frequency as a resonant frequency; a second power converter that converts the DC voltage of a predetermined level to an AC signal using a second switching pulse signal having an opposite phase to the first switching pulse signal; a first short circuit that reduces or eliminates an odd harmonic of the AC signal outputted from the first power converter, and provides the AC signal; and a second short circuit that reduces or eliminates an odd harmonic of the AC signal outputted from the second power converter, and provides the AC signal.

Abstract: A solid state relay circuit arrangement for audio signals is described, of the type comprising a first MOSFET and a second MOSFET in a back-to-back configuration, adapted to receive an input signal on the source electrode of the first MOSFET and to take the output signal on the source electrode of the second MOSFET, with a driving voltage being applied to the gate electrodes of said first MOSFET and second MOSFET, apt to change, on the basis of its value, the operational state of said first MOSFET and second MOSFET, According to the invention, each of said first MOSFET and second MOSFET includes a respective bypass capacitor arranged between its source electrode and its gate electrode, having such a capacitance value to determine a bypass path for the input signal from the source electrode to the gate electrode in the operating frequency range of said input signal.

Abstract: An amplifier operates to provide a high output impedance at an output through a push stage having a first transistor of a first transistor type and a pull stage having a second transistor of a second transistor type that is different from the first transistor type. The first transistor and the second transistor are coupled in a common-gate configuration. The first transistor and the second transistor are shorted together via a capacitor coupled to an input and share a common current path as a push-pull current-reusing common-gate low noise amplifier with a broadband input matching.

Abstract: A step down unit steps down an external power supply voltage Vcc. A bias current control circuit controls the magnitude of bias current flowing through an auxiliary path connecting an output node and the ground. A system controller increases the magnitude of the bias current, prior to a change of the operation state of a load circuit by which a relatively large change occurs to the amount of current consumed by the load circuit including a central processing unit.

Abstract: A Class AB amplifier has a control stage and a push-pull stage. The control stage has a programmable resistor that allows a floating constant voltage to applied to the push-pull stage such that the quiescent current of the amplifier is relatively low. The configuration enables the amplifier to operate properly at relatively low power-supply voltage levels. The amplifier can be configured as the output driver for an operational amplifier (op-amp) with a Miller compensation configuration that replaces the conventional Miller compensation resistor with a transistor that is part of the op-amp.

Abstract: A switch-mode RFPA driver includes first and second field-effect transistors (FETs) arranged in a totem-pole-like configuration. The switch-mode RFPA driver operates to generate a switch-mode RFPA drive signal having a generally square-wave-like waveform from an input RF signal having a generally sinusoidal-like waveform. To maximize high-frequency operation and avoid distorting the switch-mode RFPA drive signal, the switch-mode RFPA driver is designed so that its output can be connected directly to the input of the switch-mode RFPA to be driven, i.e., without using or requiring the use of an AC coupling capacitor. The first and second FETs of the switch-mode RFPA driver are designed and configured to limit and control the upper and lower magnitude levels of the switch-mode RFPA drive signal to levels suitable for switching the switch-mode RFPA directly, obviating any need for DC biasing at the input of the switch-mode RFPA.

Abstract: An amplifier including a first transistor of a first conduction type; a second transistor of a second conduction type, the second transistor being coupled to the first transistor; an input for receiving an input signal, a control terminal of the first transistor being coupled to a control terminal of the second transistor, the control terminals being coupled to the input; an output for outputting an output signal, the output being coupled to the first transistor and the second transistor; and a current supply coupled to the first transistor and configured to supply current so as to cause a predetermined transconductance of the amplifier.

Abstract: In one embodiment, a circuit includes a first transistor having a control terminal, a first terminal, and a second terminal where the first transistor is a first device type. The control terminal of the first transistor receives an input signal. The circuit also includes a second transistor having a control terminal, a first terminal, and a second terminal where the second transistor is a second device type. The control terminal of the second transistor is coupled to the second terminal of the first transistor. A voltage shift circuit has an input coupled to the first terminal of the first transistor and an output coupled to the first terminal of the second transistor and a voltage between the input of the voltage shift circuit and an output of the voltage shift circuit increases as a current from the output of the voltage shift circuit increases.

Abstract: It is possible to increase linearity in a power amplification circuit. A power amplification circuit includes a first amplification element which amplifies and outputs an input signal with a gain according to the level of the input signal and the level of a bias voltage, a second amplification element which has the same gain characteristic as the first amplification element and amplifies and outputs the input signal, and a variable bias voltage generation circuit which generates a bias voltage decreasing with an increase in level of an output signal of the second amplification element.

Abstract: A system and method for enhancing the real and/or perceived bass band of an audio signal is disclosed. A computationally simple yet effective bass band enhancement system for use in consumer electronics applications is disclosed. An audio processing system including bass enhancement functionality for use in a mobile audio system is disclosed.

Abstract: There is provided an amplifier arrangement comprising: a main amplifier connected to receive an input signal and generate an amplified version of the input signal; an additional amplifier, having a smaller geometry than the main amplifier, connected to receive the input signal and generate an amplified version thereof; and wherein the outputs of the main amplifier and the additional amplifier are combined to provide an amplified output.

Abstract: There is provided an integrated circuit comprising a main push-pull amplifier (108, 110) with balanced outputs and an additional push-pull amplifier (862, 863) with balanced outputs. Each of these balanced outputs is connected to an off-chip load (822) via respective bonding wires (818, 828, 830, 880) to provide a combined amplified signal to the load. The additional amplifier serves to compensate for crossover distortions generated by the main amplifier.

Abstract: An amplifier and a transceiver including the amplifier are provided. The amplifier includes an input terminal; a first transistor of a first conductivity and a second transistor of a second conductivity, each transistor comprising a source terminal, a gate terminal and a drain terminal respectively, the source terminal of the first transistor being coupled to the source terminal of the second transistor, and the gate terminal of the first transistor and the gate terminal of the second transistor being coupled to the input terminal; and an output terminal coupled to the drain terminal of the first transistor and the drain terminal of the second transistor.