And Field Effect Transistor Patents (Class 330/264)
  • Patent number: 10998896
    Abstract: A system for correcting a duty cycle comprises a digital quadrature generator circuit, a frequency doubler circuit, a first duty cycle correction circuit coupled between the digital quadrature generator circuit and the frequency doubler circuit, and a second duty cycle correction circuit coupled between the digital quadrature generator circuit and the frequency doubler circuit. The first duty cycle correction circuit comprises a first stacked duty cycle correction circuit and the second duty cycle correction circuit comprises a second stacked duty cycle correction circuit.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: May 4, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Tien-Ling Hsieh
  • Patent number: 10862437
    Abstract: An amplification device comprising: a push pull circuit which amplifies an input signal; a diamond buffer circuit to which the signal which is amplified by the push pull circuit is input; and a current mirror circuit which is connected to a power supply and the diamond buffer circuit and is connected to a retraction current terminal of the push pull circuit.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: December 8, 2020
    Inventor: Makoto Yoshida
  • Patent number: 10707813
    Abstract: A power amplifier and method for operating the same is disclosed. The amplifier includes a number of transistors coupled in series between a power node and a ground node. These transistors include a first transistor having a source terminal coupled to the power node, and a second transistor having its source terminal coupled to a ground node. A subset of transistors is also coupled in series between the first and second transistors. During operation in a first mode, the first and second transistors act as switching transistors, switching according to data received thereby. The subset of transistors, during the first mode, act as cascode transistors. During a second mode of operation, the transistors of the subset act as switching transistors, switching in accordance with the received data.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: July 7, 2020
    Assignee: Apple Inc.
    Inventors: David M. Signoff, Morteza Nick, Anuranjan Jha
  • Patent number: 10680563
    Abstract: A multi-stage radio frequency power amplifier (RFPA) includes an output stage SMPA and a driver stage SMPA. As the multi-stage RFPA operates, the magnitude of an RF switch drive signal generated by the driver stage SMPA is dynamically minimized based on I-V characteristic curves of the output stage SMPA's power transistor and the output stage SMPA's dynamically changing load line. By constraining the magnitude of the RF switch drive signal as the multi-stage RFPA operates, VGS feedthrough of the RF switch drive signal is minimized, to the extent possible. Amplitude distortion and phase distortion in the RF output that might occur due to unconstrained VGS feedthrough, particularly at low output RF power levels, are therefore avoided. Operating all stages of the multi-stage RFPA in switch mode also results in high energy efficiency and an output RF spectrum with very low wideband noise (WBN).
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: June 9, 2020
    Assignee: Eridan Communications, Inc.
    Inventors: Earl W McCune, Jr., Quentin Diduck
  • Patent number: 10432153
    Abstract: The present invention reveals a new biasing method which can be used in solid state audio power amplifier design despite of the Class of operation. The proposed biasing technology relies only on traditional electrical feedback to build up and maintain the desired biasing current and doesn't need thermal coupling or thermal tracking techniques in order to overcome power transistor device's temperature dependent input-output characteristics as required by traditional approach. An ingenious current sensing and amplification circuit is devised in order to generate an voltage output which is only corresponding to the quiescent biasing current of the output stage. This voltage output is then used as an representative of the power stage biasing current to be regulated by a feedback loop comprising a traditional voltage multiplier, the output stage and the aforementioned current sensing and amplification circuit.
    Type: Grant
    Filed: March 4, 2018
    Date of Patent: October 1, 2019
    Inventor: Zhenwu Wang
  • Patent number: 10401521
    Abstract: The acoustic energy induced by a transmitter module of an acoustic logging tool is dependent on several factors. In some implementations, the induced acoustic energy is dependent on the electromagnetic energy input into the transmitter module, the response behavior of the transmitter module, and the operating conditions of the transmitter module. Variation in one or more of these factors can result in a corresponding variation in the induced acoustic. Thus, a desired acoustic signal can be produced by applying an appropriately selected input signal to the transmitter module, while accounting for other factors that influence the output of the transmitter module.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: September 3, 2019
    Assignee: Halliburton Energy Services, Inc.
    Inventors: Yinghui Lu, Daniel Viassolo
  • Patent number: 10348256
    Abstract: A switch-mode RFPA driver includes first and second field-effect transistors (FETs) arranged in a totem-pole-like configuration. The switch-mode RFPA driver operates to generate a switch-mode RFPA drive signal having a generally square-wave-like waveform from an input RF signal having a generally sinusoidal-like waveform. To maximize high-frequency operation and avoid distorting the switch-mode RFPA drive signal, the switch-mode RFPA driver is designed so that its output can be connected directly to the input of the switch-mode RFPA to be driven, i.e., without using or requiring the use of an AC coupling capacitor. The first and second FETs of the switch-mode RFPA driver are designed and configured to limit and control the upper and lower magnitude levels of the switch-mode RFPA drive signal to levels suitable for switching the switch-mode RFPA directly, obviating any need for DC biasing at the input of the switch-mode RFPA.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: July 9, 2019
    Assignee: Eridan Communications, Inc.
    Inventor: Earl W. McCune, Jr.
  • Patent number: 10211781
    Abstract: The present invention relates to a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. In particular, the present invention relates to a solid state device based on a complementary pair of n-type and p-type current field-effect transistors, each of which has two control ports, namely a low impedance port and gate control port, while a conventional solid state device has one control port, namely gate control port. This novel solid state device provides various improvement over the conventional devices.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: February 19, 2019
    Assignee: Circuit Seed, LLC
    Inventors: Robert C. Schober, Susan Marya Schober
  • Patent number: 10205423
    Abstract: A source follower method, system, and apparatus provide rail-to-rail capability to an output voltage terminal of a voltage follower feedback biased CMOS output circuit by providing a control circuit which includes first and second bypass transistors that are connected in parallel between first and second control circuit input/output terminals and controlled, respectively, by first and second control circuit inputs, and which also includes first and second current sources for injecting source and sink currents in the output node as a function, respectively, of a first bypass current through the first bypass transistor which turns ON when the output voltage rises above a top threshold voltage level and of a second bypass current through the second bypass transistor which turns ON when the output voltage falls below a bottom threshold voltage level.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: February 12, 2019
    Assignee: NXP USA, Inc.
    Inventors: Pedro B. Zanetta, Ricardo P. Coimbra
  • Patent number: 10187041
    Abstract: A pseudo resistance circuit is disclosed that is capable of suppressing fluctuation in resistance value with fluctuation in process or temperature and facilitating adjustment. The pseudo resistance circuit includes a first MOSFET, a second MOSFET, a first current source which generates a first current substantially proportional to absolute temperature, and voltage source which generates a first voltage, which is a substantially linear function of absolute temperature. The gate of the first MOSFET and the gate of the second MOSFET are connected together, the second MOSFET is diode-connected, the first current is supplied to the drain of the second MOSFET, the first voltage is applied to the source of the second MOSFET, and a resistor having a resistance value according to the gate voltage of the first MOSFET is formed between the drain and the source of the first MOSFET.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: January 22, 2019
    Assignees: MURATA MANUFACTURING CO., LTD., MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventors: Shumpei Ida, Hae-Seung Lee
  • Patent number: 10135404
    Abstract: An integrated circuit comprises a first amplifier circuit with a push-pull amplifier configured to be calibrated to a low second order distortion. The integrated circuit further comprises a second amplifier circuit with at least one push-pull amplifier, wherein a size ratio between sizes of the transistors is adjustable by adjusting the size of at least one transistor device. The size ratio can be consecutively adjusted to a plurality of values, and for each value, a first output signal of a push-pull amplifier with an applied test signal and a second output signal of a push-pull amplifier without applied test signal, are determined. The size ratio for which a difference between the push-pull amplifier output signals is closest to zero is determined, and the push-pull amplifier of the first amplifier circuit is calibrated in dependence of the determined size ratio.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: November 20, 2018
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (publ)
    Inventor: Henrik Sjoland
  • Patent number: 10063197
    Abstract: Circuits for power-combined power amplifier array are provided, the circuits comprising: an input splitter coupled to an input that provides a plurality of outputs; a plurality of power amplifier unit cells, each power amplifier unit cell coupled to a corresponding output of the input splitter and each power amplifier unit cell providing an output signal at an output of the power amplifier unit cell; and a power combiner having an output, a plurality of inputs, each input coupled to the output of a corresponding power amplifier unit cell, and a plurality of C-L-C-section equivalents, each having an input connected to a corresponding one of the plurality of inputs of the power combiner and an output connected to the output of the power combiner.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: August 28, 2018
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Ritesh Bhat, Harish Krishnaswamy
  • Patent number: 10038417
    Abstract: A current-bootstrap comparator includes a receiving unit, a first current generation unit and a second current generation unit. The receiving unit receives a load voltage signal, a low threshold voltage and a high threshold voltage. The first current generation unit generates a first current. The second current generation unit generates a second current having a magnitude substantially same as a magnitude of the first current and a direction reverse to the first current. The first current and the second current are supplied to a next-stage circuit as a source current and a corresponding sink current, respectively, when the level of the load voltage signal is higher than the high threshold voltage or lower than the low threshold voltage. The magnitudes of the first current and the second current substantially equal zero when the level of the load voltage signal is between the high threshold voltage and the low threshold voltage.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: July 31, 2018
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Min-Hung Hu, Ping-Lin Liu, Pin-Han Su
  • Patent number: 9985593
    Abstract: A switch-mode RFPA driver includes first and second field-effect transistors (FETs) arranged in a totem-pole-like configuration. The switch-mode RFPA driver operates to generate a switch-mode RFPA drive signal having a generally square-wave-like waveform from an input RF signal having a generally sinusoidal-like waveform. According to one embodiment of the invention, to maximize high-frequency operation and avoid distorting the switch-mode RFPA drive signal, the switch-mode RFPA driver is designed so that its output can be connected directly to the input of the switch-mode RFPA to be driven, i.e., without using or requiring the use of an AC coupling capacitor. The first and second FETs of the switch-mode RFPA driver are designed and configured to limit and control the upper and lower magnitude levels of the switch-mode RFPA drive signal to levels suitable for switching the switch-mode RFPA directly, obviating any need for DC biasing at the input of the switch-mode RFPA.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: May 29, 2018
    Assignee: Eridan Communications, Inc.
    Inventor: Earl W McCune, Jr.
  • Patent number: 9948252
    Abstract: Systems, methods and apparatus for practical realization of an integrated circuit comprising a stack of transistors operating as an RF amplifier are described. As stack height is increased, capacitance values of gate capacitors used to provide a desired distribution of an RF voltage at the output of the amplifier across the stack may decrease to values approaching parasitic/stray capacitance values present in the integrated circuit which may render the practical realization of the integrated circuit difficult. Coupling of an RF gate voltage at the gate of one transistor of the stack to a gate of a different transistor of the stack can allow for an increase in the capacitance value of the gate capacitor of the different transistor for obtaining an RF voltage at the gate of the different transistor according to the desired distribution.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: April 17, 2018
    Assignee: pSemi Corporation
    Inventor: Jaroslaw Adamski
  • Patent number: 9935587
    Abstract: An inductor-less low noise amplifier (LNA) with high linearity is disclosed. The low noise amplifier includes: an input signal stage receiving an input signal; a first amplifier configured to receive the input signal, generate a first amplification signal by amplifying the received input signal, and output the generated first amplification signal, as a first output signal, to a first output terminal; a second amplifier configured to receive the input signal, generate a second amplification signal by amplifying the received input signal, and output the generated second amplification signal, as a second output signal, to a second output terminal; an output signal stage outputting a superimposition signal obtained by superimposing the first output signal and the second output signal; a first resistor feeding back the superimposition signal to the input signal stage; and a switch connecting/disconnecting between the input signal stage and the output signal stage.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: April 3, 2018
    Assignee: FCI INC
    Inventors: DongHyun Ko, Myung Woon Hwang
  • Patent number: 9917513
    Abstract: An integrated circuit with voltage regulator circuitry is provided. The voltage regulator circuitry may include an adaptive bleeder circuit. The adaptive bleeder circuit may include one or more switchable current leaker paths and an associated bleeder control circuit having current sensing circuitry and voltage comparison circuitry. The current sensing circuitry may monitor the amount of current that is being delivered to a load circuit, whereas the voltage comparison circuitry may output control signals that selectively activate one or more of the current leaker paths depending on the monitored current values. Adaptive bleeder circuit configured in this way can help maintain stability of the voltage regulator while minimizing dynamic power consumption.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: March 13, 2018
    Assignee: Altera Corporation
    Inventors: Thien Le, Ping-Chen Liu
  • Patent number: 9906217
    Abstract: A semiconductor device includes: a depletion-type field-effect transistor including a gate terminal, a drain terminal and a source terminal; a group III-V heterojunction bipolar transistor including a base terminal, an emitter terminal electrically connected to the gate terminal and a collector terminal connected to same potential as that of the source terminal; a first resistor connected between the base terminal and the emitter terminal; and a second resistor connected between the base terminal and the collector terminal.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: February 27, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shohei Imai, Kazuya Yamamoto, Yoshinobu Sasaki, Shinichi Miwa
  • Patent number: 9893728
    Abstract: A wideband highly-linear buffer circuit exhibiting a low output impedance comprises a first PFET (PFET1), a second PFET (PFET2), a first NFET (NFET1), and a second NFET (NFET2). Sources of PFET1 and PFET2 are coupled to VDD. PFET1's drain is coupled to an output lead. PFET2 acts as a current source. NFET1's drain is coupled to PFET2's drain and to PFET1's gate. NFET1's source is coupled to the output lead. NFET2's source is coupled to ground. NFET2's drain is coupled to NFET1's source and to the output lead. NFET1's gate is AC coupled to a first input lead. In a single-ended input example, NFET2's gate is AC coupled NFET1's drain. In a differential input example, NFET2's gate is AC coupled to a second input lead. In another differential input example, PFET2 is not just a current source, but rather PFET2's gate is AC coupled to the first input lead.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: February 13, 2018
    Assignee: MEDIATEK INC.
    Inventors: Fei Song, Osama Shana'a, Yuen Hui Chee
  • Patent number: 9774307
    Abstract: Power amplifier having biasing with selectable bandwidth. In some embodiments, a power amplifier can include an amplifying transistor having a base for receiving a signal to be amplified, and a bias circuit configured to bias the amplifying transistor. The bias circuit can include a reference transistor having a base coupled to the base of the amplifying transistor and a collector coupled to a reference current source. The bias circuit can further include a coupling circuit that couples the collector and the base of the reference transistor. The coupling circuit can include a switchable element configured to allow the coupling circuit to be in a first state to provide a first bandwidth for the bias circuit or a second state to provide a second bandwidth for the bias circuit.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: September 26, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventors: Matthew Lee Banowetz, Ramanan Bairavasubramanian, Michael Lynn Gerard, Philip H. Thompson
  • Patent number: 9768737
    Abstract: In a preamplifier (amplifier) for the radiation detector, an interconnection layer connected to the bonding pad forms one electrode of a feedback capacitor. Since there is no wiring for connecting the bonding pad and capacitor, a parasitic capacitance caused by the wiring will not be generated. Moreover, the capacitor is arranged below the bonding pad with a conductive layer serving as the other electrode, so that the feedback capacitance of the capacitor is included in the parasitic capacitance between the interconnection layer and the substrate. Compared to the conventional case, an amount of capacitance corresponding to the parasitic capacitance caused by wiring and the feedback capacitance for the capacitor is reduced from the input capacitance. Thus, the input capacitance for the amplifying circuit is reduced.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: September 19, 2017
    Assignees: HORIBA, LTD., POLITECNICO DI MILANO
    Inventors: Carlo Fiorini, Luca Bombelli
  • Patent number: 9723405
    Abstract: Apparatus (301) for switchable attenuation of a differential input signal from a microphone includes positive and negative non-attenuating paths (406, 410) have n- and p-type MOSFETs (421, 422, 423, 424) in back-to-back configurations; positive and negative attenuating paths (405, 409) have n- and p-type MOSFETs (415, 416, 418, 419) in back-to-back configurations in combination with resistors; a gate driver (425) applies a drive signal of one polarity (QNEG) to gates of the n-type MOSFETs in the attenuating paths and the p-type MOSFETs in the non-attenuating paths, and a drive signal of opposite polarity (QPOS) to the gates of the p-type MOSFETs in the attenuating paths and the n-type MOSFETs in the non-attenuating paths; and the state of the MOSFETs depends on the drive signals at their gates, and thus the input signal may be routed via either the non-attenuating paths or the attenuating paths by controlling the drive signals.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: August 1, 2017
    Assignee: Red Lion 49 Limited
    Inventor: David Joseph Mate
  • Patent number: 9618958
    Abstract: A current generator includes a first current generation circuit configured to generate a first current having a first current noise which depends on a change in a supply voltage, a second current generation circuit configured to generate a second current having a second current noise which depends on the change in the supply voltage, and a current subtracting circuit configured to generate a third current with the first current noise and the second current noise removed by subtracting the second current from the first current.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: April 11, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae Kwang Jang, Jen Lung Liu, Nan Xing, Jae Jin Park
  • Patent number: 9608607
    Abstract: Representative implementations of devices and techniques provide a speed increase to a comparator circuit. An active clamp device may be positioned between an input stage and an output stage of the comparator, limiting the voltage range of the output of the first stage.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: March 28, 2017
    Assignee: Infineon Technologies Austria AG
    Inventor: Adriano Sambucco
  • Patent number: 9553456
    Abstract: A power converter for transmitting a resonance power is provided that includes: an input end that receives a direct current (DC) voltage of a predetermined level; a first power converter that converts the DC voltage of a predetermined level to an alternating current (AC) signal using a first switching pulse signal having substantially the same frequency as a resonant frequency; a second power converter that converts the DC voltage of a predetermined level to an AC signal using a second switching pulse signal having an opposite phase to the first switching pulse signal; a first short circuit that reduces or eliminates an odd harmonic of the AC signal outputted from the first power converter, and provides the AC signal; and a second short circuit that reduces or eliminates an odd harmonic of the AC signal outputted from the second power converter, and provides the AC signal.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: January 24, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin Sung Choi, Sang Wook Kwon, Yun Kwon Park, Eun Seok Park, Young Tack Hong, Young Ho Ryu, Nam Yun Kim, Dong Zo Kim
  • Patent number: 9544686
    Abstract: A solid state relay circuit arrangement for audio signals is described, of the type comprising a first MOSFET and a second MOSFET in a back-to-back configuration, adapted to receive an input signal on the source electrode of the first MOSFET and to take the output signal on the source electrode of the second MOSFET, with a driving voltage being applied to the gate electrodes of said first MOSFET and second MOSFET, apt to change, on the basis of its value, the operational state of said first MOSFET and second MOSFET, According to the invention, each of said first MOSFET and second MOSFET includes a respective bypass capacitor arranged between its source electrode and its gate electrode, having such a capacitance value to determine a bypass path for the input signal from the source electrode to the gate electrode in the operating frequency range of said input signal.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: January 10, 2017
    Assignee: Magneti Marelli S.p.A.
    Inventors: Jacopo Cecchin, Roberto Vettori, Davide Gonella, Alessandro Bergamini
  • Patent number: 9537457
    Abstract: An amplifier operates to provide a high output impedance at an output through a push stage having a first transistor of a first transistor type and a pull stage having a second transistor of a second transistor type that is different from the first transistor type. The first transistor and the second transistor are coupled in a common-gate configuration. The first transistor and the second transistor are shorted together via a capacitor coupled to an input and share a common current path as a push-pull current-reusing common-gate low noise amplifier with a broadband input matching.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: January 3, 2017
    Assignee: Intel IP Corporation
    Inventors: Vadim Issakov, Konrad Hirsch, Herbert Stockinger, Harald Doppke
  • Patent number: 9529402
    Abstract: A step down unit steps down an external power supply voltage Vcc. A bias current control circuit controls the magnitude of bias current flowing through an auxiliary path connecting an output node and the ground. A system controller increases the magnitude of the bias current, prior to a change of the operation state of a load circuit by which a relatively large change occurs to the amount of current consumed by the load circuit including a central processing unit.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: December 27, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Soichi Kobayashi, Akira Oizumi, Yoshihiko Yasu, Hiromi Notani
  • Patent number: 9407208
    Abstract: A Class AB amplifier has a control stage and a push-pull stage. The control stage has a programmable resistor that allows a floating constant voltage to applied to the push-pull stage such that the quiescent current of the amplifier is relatively low. The configuration enables the amplifier to operate properly at relatively low power-supply voltage levels. The amplifier can be configured as the output driver for an operational amplifier (op-amp) with a Miller compensation configuration that replaces the conventional Miller compensation resistor with a transistor that is part of the op-amp.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: August 2, 2016
    Assignee: LATTICE SEMICONDUCTOR CORPORATION
    Inventors: Vinh Ho, Carl Chai, Allan Lin
  • Patent number: 9397621
    Abstract: A switch-mode RFPA driver includes first and second field-effect transistors (FETs) arranged in a totem-pole-like configuration. The switch-mode RFPA driver operates to generate a switch-mode RFPA drive signal having a generally square-wave-like waveform from an input RF signal having a generally sinusoidal-like waveform. To maximize high-frequency operation and avoid distorting the switch-mode RFPA drive signal, the switch-mode RFPA driver is designed so that its output can be connected directly to the input of the switch-mode RFPA to be driven, i.e., without using or requiring the use of an AC coupling capacitor. The first and second FETs of the switch-mode RFPA driver are designed and configured to limit and control the upper and lower magnitude levels of the switch-mode RFPA drive signal to levels suitable for switching the switch-mode RFPA directly, obviating any need for DC biasing at the input of the switch-mode RFPA.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: July 19, 2016
    Assignee: Eridan Communications, Inc.
    Inventor: Earl W McCune, Jr.
  • Patent number: 9391563
    Abstract: An amplifier including a first transistor of a first conduction type; a second transistor of a second conduction type, the second transistor being coupled to the first transistor; an input for receiving an input signal, a control terminal of the first transistor being coupled to a control terminal of the second transistor, the control terminals being coupled to the input; an output for outputting an output signal, the output being coupled to the first transistor and the second transistor; and a current supply coupled to the first transistor and configured to supply current so as to cause a predetermined transconductance of the amplifier.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: July 12, 2016
    Assignee: QUALCOMM TECHNOLOGIES INTERNATIONAL, LTD.
    Inventor: Michael John Story
  • Patent number: 9354649
    Abstract: In one embodiment, a circuit includes a first transistor having a control terminal, a first terminal, and a second terminal where the first transistor is a first device type. The control terminal of the first transistor receives an input signal. The circuit also includes a second transistor having a control terminal, a first terminal, and a second terminal where the second transistor is a second device type. The control terminal of the second transistor is coupled to the second terminal of the first transistor. A voltage shift circuit has an input coupled to the first terminal of the first transistor and an output coupled to the first terminal of the second transistor and a voltage between the input of the voltage shift circuit and an output of the voltage shift circuit increases as a current from the output of the voltage shift circuit increases.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: May 31, 2016
    Assignee: QUALCOMM, Incorporated
    Inventors: Ngai Yeung Ho, Liangguo Shen, Bing Liu, Vincenzo F Peluso
  • Patent number: 9331639
    Abstract: It is possible to increase linearity in a power amplification circuit. A power amplification circuit includes a first amplification element which amplifies and outputs an input signal with a gain according to the level of the input signal and the level of a bias voltage, a second amplification element which has the same gain characteristic as the first amplification element and amplifies and outputs the input signal, and a variable bias voltage generation circuit which generates a bias voltage decreasing with an increase in level of an output signal of the second amplification element.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: May 3, 2016
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Masatoshi Hase
  • Patent number: 9307323
    Abstract: A system and method for enhancing the real and/or perceived bass band of an audio signal is disclosed. A computationally simple yet effective bass band enhancement system for use in consumer electronics applications is disclosed. An audio processing system including bass enhancement functionality for use in a mobile audio system is disclosed.
    Type: Grant
    Filed: November 22, 2012
    Date of Patent: April 5, 2016
    Assignee: Actiwave AB
    Inventor: Pär Gunnars Risberg
  • Patent number: 9054649
    Abstract: There is provided an amplifier arrangement comprising: a main amplifier connected to receive an input signal and generate an amplified version of the input signal; an additional amplifier, having a smaller geometry than the main amplifier, connected to receive the input signal and generate an amplified version thereof; and wherein the outputs of the main amplifier and the additional amplifier are combined to provide an amplified output.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: June 9, 2015
    Assignee: Nujira Limited
    Inventor: Martin Paul Wilson
  • Patent number: 8963642
    Abstract: There is provided an integrated circuit comprising a main push-pull amplifier (108, 110) with balanced outputs and an additional push-pull amplifier (862, 863) with balanced outputs. Each of these balanced outputs is connected to an off-chip load (822) via respective bonding wires (818, 828, 830, 880) to provide a combined amplified signal to the load. The additional amplifier serves to compensate for crossover distortions generated by the main amplifier.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: February 24, 2015
    Assignee: Nujira Limited
    Inventor: Martin Paul Wilson
  • Patent number: 8957732
    Abstract: An amplifier and a transceiver including the amplifier are provided. The amplifier includes an input terminal; a first transistor of a first conductivity and a second transistor of a second conductivity, each transistor comprising a source terminal, a gate terminal and a drain terminal respectively, the source terminal of the first transistor being coupled to the source terminal of the second transistor, and the gate terminal of the first transistor and the gate terminal of the second transistor being coupled to the input terminal; and an output terminal coupled to the drain terminal of the first transistor and the drain terminal of the second transistor.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: February 17, 2015
    Assignee: Agency for Science, Technology and Research
    Inventors: Hyouk Kyu Cha, Yuan Gao, Xiaojun Yuan
  • Patent number: 8952757
    Abstract: An amplifier circuit is disclosed. The amplifier circuit includes a detection circuit, a control amplifier circuit and an output stage. The detection circuit detects disturbances occurring in a first supply voltage and provides detection results. The control amplifier circuit controls a first voltage provided to a first control node and a second voltage provided to a second control node in response to the detection results. The output stage circuit includes a first output power transistor coupled to the control amplifier circuit at the first control node and a second output power transistor coupled to the control amplifier circuit at the second control node. The first voltage and the second voltage are controlled differently when a disturbance is detected to have occurred.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: February 10, 2015
    Assignee: MediaTek Inc.
    Inventors: Sung-Han Wen, Chien-Chung Yang
  • Patent number: 8937797
    Abstract: An integrated circuit includes circuitry to sense the occurrence of a break in a ground connection and/or supply connection and to indicate same to an exterior environment. In at least one implementation, the break may be indicated by providing a signal on an output terminal of the device that is not associated with a normal output of the device.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: January 20, 2015
    Assignee: Allegro Microsystems, LLC
    Inventors: Franco Noel Martin Pirchio, Cory Voisine, Hernan D. Romero, Gerardo Monreal
  • Patent number: 8933755
    Abstract: A unity-gain buffer includes an operational amplifier, a control stage, and an auxiliary output stage. The operational amplifier includes a non-inverting input terminal, an output terminal, and an inverting input terminal. The control stage is connected between the non-inverting input terminal and the output terminal of the unity-gain buffer. The auxiliary output stage is connected between the control stage and the output terminal of the unity-gain buffer. According to an input voltage at the input terminal of the unity-gain buffer, the control stage generates a first driving current, the auxiliary output stage generates a second driving current, and the operational amplifier generates a third driving current, so that an overall driving current outputted from the output terminal of the unity-gain buffer is equal to the sum of the first driving current, the second driving current and the third driving current.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: January 13, 2015
    Assignee: Orise Technology Co., Ltd.
    Inventors: Yen-Cheng Cheng, Chien-Chun Huang, Kuan-Han Chen
  • Patent number: 8854138
    Abstract: A buffer amplifier with unity voltage gain, high input impedance, high speed, high current gain, high output power and low offset includes three stages and a DC servo circuit. The first stage of the buffer amplifier contains complementary N-channel and P-channel MOSFET source followers that provide high input impedance to buffer the input signal source. A feedback DC servo signal is provided to correct the subsequent stages so as to maintain the output at virtual DC ground level. The second stage is a driver stage that also contains complementary N-channel and P-channel MOSFET source followers to provide sufficient current to drive the output stage. The last stage is an output stage that contains at least one pair of complementary power MOSFETs or BJTs to deliver high currents to a load.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: October 7, 2014
    Inventor: Chi Ming John Lam
  • Patent number: 8847685
    Abstract: A push-pull amplifier includes an amplifier input, a push amplifier stage, a pull amplifier stage and an inverting amplifier output.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 30, 2014
    Assignee: Intel Mobile Communications GmbH
    Inventors: Ashkan Naeini, Martin Simon, Herbert Stockinger, Werner Schelmbauer, Bernd-Ulrich Klepser
  • Patent number: 8836420
    Abstract: The invention provides an analog circuit that decreases an effect of variation of a transistor. By flowing a bias current in a compensation operation, a voltage between the gate and source of the transistor to be compensated is held in a capacitor. In a normal operation, the voltage stored in the compensation operation is added to a signal voltage. As the capacitor holds the voltage according to the characteristics of the transistor to be compensated, the effect of variation can be decreased by adding the voltage stored in the capacitor to the signal voltage. Further, an analog circuit which decreases the effect of variation can be provided by applying the aforementioned basis to a differential circuit, an operational amplifier and the like.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: September 16, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 8786366
    Abstract: An amplifier circuit is described comprising a first field effect transistor comprising a first source/drain terminal coupled to a first supply terminal, a second source/drain terminal coupled to an output of the amplifier circuit and a gate terminal; a second field effect transistor comprising a first source/drain terminal coupled to an input of the amplifier circuit, a second source/drain terminal coupled to the gate terminal of the first field effect transistor and a gate terminal; a third field effect transistor comprising a first source/drain terminal coupled to a first bias current source of the amplifier circuit, a second source/drain terminal and a gate terminal coupled to its first source/drain terminal and the gate terminal of the second field effect transistor; a fourth field effect transistor comprising a first source/drain terminal coupled to a second bias current source, a second source/drain terminal coupled to a second supply terminal and a gate terminal coupled to the second source/drain term
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: July 22, 2014
    Assignee: Intel Mobile Communications GmbH
    Inventors: Georgi Panov, Rinaldo Zinke
  • Patent number: 8736374
    Abstract: An amplifier includes a first switch and a second switch each having a first terminal and a second terminal. The first terminals of the first and second switches respectively communicate with a first tank circuit and a second tank circuit. The second terminal of the second switch communicates with the second terminal of the first switch. A first capacitance having a first terminal connected directly to (i) the second terminal of the first switch and (ii) the second terminal of the second switch. A second terminal of the first capacitance is connected directly to a first input voltage of the amplifier. A first load is connected across (i) the first terminal of the first switch and (ii) the first terminal of the second switch. The amplifier generates a first output across the first load.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: May 27, 2014
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Farbod Aram
  • Patent number: 8692578
    Abstract: A transmitter includes a power amplifier (PA) and a direct current (DC) voltage tuning circuit. The PA is arranged for receiving a radio-frequency (RF) clock derived from a clock source, and producing an output signal according to at least the RF clock. The DC voltage tuning circuit is arranged for tuning at least one DC voltage supplied to the PA for pulling mitigation of the clock source. A method of pulling mitigation of a source clock by a power amplifier (PA) includes adjusting a direct current (DC) voltage supplied to the PA.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: April 8, 2014
    Assignee: Mediatek Inc.
    Inventors: Jie-Wei Lai, Meng-Hsiung Hung, Robert Bogdan Staszewski
  • Patent number: 8692179
    Abstract: The invention discloses an optical communication system using grounded coplanar waveguide, comprising a current buffer and a transimpedance amplifier (TIA). Transmission lines of the optical communication system have grounded coplanar waveguide (GCPW) structures. The current buffer receives a current signal from a signal source, and outputs the current signal after reducing capacitance effects of the signal source. The TIA converts the current signal to a voltage signal, wherein a first end of the TIA receives the current signal, a second end of the TIAn outputs the voltage signal, and a shunt-shunt feedback circuit is coupled between the first end and the second end. Therefore, the present invention can minimize the circuit area and lower the power consumption as well.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: April 8, 2014
    Assignee: National Tsing Hua University
    Inventors: Wei-Han Cho, Chia-Hou Tu, Shawn S. H. Hsu
  • Patent number: 8680924
    Abstract: A differential power amplifier is provided and includes a first pair of transistors. A first transistor is inductively coupled to a voltage source and is connected to a node at a ground reference potential. A second transistor is inductively coupled to the node and is connected to the voltage source. Gates of the transistors are configured to receive an AC signal with a fundamental frequency. Drain of the first and second transistors are respectively first and second output nodes. The output nodes provide a first differential output. A capacitor is connected between the output nodes and provides a pathway for cancellation of even harmonic signals of the fundamental frequency. A second pair of transistors provides a second differential output. A first inductor is connected between the output nodes. A second inductor is connected between output nodes of the second pair of transistors. A combiner is inductively coupled to the inductors.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: March 25, 2014
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Poh Boon Leong, Ping Song, Nuntha Kumar Krishnasamy Maniam
  • Patent number: 8680917
    Abstract: The invention provides an analog circuit that decreases an effect of variation of a transistor. By flowing a bias current in a compensation operation, a voltage between the gate and source of the transistor to be compensated is held in a capacitor. In a normal operation, the voltage stored in the compensation operation is added to a signal voltage. As the capacitor holds the voltage according to the characteristics of the transistor to be compensated, the effect of variation can be decreased by adding the voltage stored in the capacitor to the signal voltage. Further, an analog circuit which decreases the effect of variation can be provided by applying the aforementioned basis to a differential circuit, an operational amplifier and the like.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: March 25, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 8629721
    Abstract: A method for controlling an output amplification stage comprising first and second complementary SOI-type power MOS transistors, in series between first and second power supply rails, the method including the steps of: connecting the bulk of the first transistor to the first rail when the first transistor is maintained in an off state; connecting the bulk of the second transistor to the second rail when the second transistor is maintained in an off state; and connecting the bulk of each of the transistors to the common node of said transistors, during periods when this transistor switches from an off state to an on state.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: January 14, 2014
    Assignee: STMicroelectronics SA
    Inventors: Dimitri Soussan, Sylvain Majcherczak