Abstract: A method and system to increase life of a direct current (DC) battery that powers an electronic device is disclosed. In one embodiment the system includes a first stage to convert the DC from the battery to an alternating current (AC), and a second stage to covert the AC from the first stage to a regulated direct current.

Abstract: A measurement instrument configured to perform an associated method separates two signals which are present on the same signal line at the same time (e.g., an incident signal and a reflected signal) so that it can measure each signal by itself. In an example, the method may include: receiving a first probed waveform from a first location on a signal line between a source device and a destination device while an output of the source device sends an incident signal to an input of the destination device via the signal line; receiving a second probed waveform from a second location on the signal line, while the output of the source device sends the incident signal to the input of the destination device via the signal line; and ascertaining from the first probed waveform and the second probed waveform the reflection coefficient at the input of the destination device.

Abstract: An apparatus includes an amplifier to drive a piezo print nozzle in response to a bias current. A bias adjuster includes a plurality of side legs and a plurality of current mirrors. The bias adjuster varies the bias current in the amplifier based on a variable slew rate associated with an input signal of a print command. The bias adjuster is to selectively mitigate power loss and increase slew rate performance of the amplifier.

Abstract: An output circuit outputs communication signals and communicates with an external device ED, and includes: a PNP first transistor, which is capable of outputting a collector current as the communication signals; and a first current source, which is capable of changing a base current of the first transistor, and which reduces the base current to a predetermined current value after the first transistor is turned on and before the first transistor is turned off.

Abstract: A circuit includes a pair of high side transistors, a pair of low side transistors, a first sense resistor coupled to one of the low side transistors at a first sense node, and a second sense resistor coupled to another of the low side transistors at a second sense node. The first and second sense resistors couple together at a ground node. The circuit includes a first switch network coupled to the first sense resistor, a second switch network coupled to the second sense resistor, a first pair of switches configured to selectively provide a potential of the ground node or a potential of the first sense node as a ground potential to the first switch network, and a second pair of switches configured to selectively provide the potential of the ground node or a potential of the second sense node as a ground potential to the second switch network.

Abstract: An RF amplifier is described including an input, an output, a parallel arrangement of a first branch and at least one further branch, each branch comprising a bipolar transistor in a degenerative emitter configuration having a base coupled to the input, a collector coupled to a common collector node, and an emitter degeneration impedance arranged between the emitter and a common rail. The common collector node is coupled to the output, the base of the first branch bipolar transistor is biased at a first bias voltage and the base of the at least one further branch bipolar transistor is biased at a bias voltage offset from the first bias voltage. In operation of the RF amplifier a IM3 distortion current output by the first branch bipolar transistor is in antiphase to a IM3 distortion current output by the at least one further branch bipolar transistor.

Abstract: A power factor correction (PFC) integrated circuit having a feed forward circuit. The feed forward circuit comprises a first current source, a second current source, and a third current source, a first bi-polar junction transistor (BJT), a second BJT, a third BJT, and a fourth BJT coupled together in a translinear cell, where the first current source is coupled to the first BJT, the second current source is coupled to the second BJT, and the third current source is coupled to the third BJT, a biasing network coupled to the first BJT and to the second BJT and configured to maintain equal collector-to-emitter voltage across the first BJT and the second BJT, where the feed forward circuit is configured to output a current based on a current of the first current source, a current of the third current source, and a current of the second current source.

Abstract: A timing regulation circuit includes a fixed and tunable timer. A current source generates a source current I1 proportional to an inductor voltage ?V1 of a DC-DC converter during an energizing phase and a current source generates a sink current I2 proportional to inductor voltage ?V2 during a de-energizing phase. The fixed timer controls a first switch in series with I1 or I2 and the tunable timer controls a balancing switch in series with the other current. I1 or I2 is coupled by the first switch and the other current is coupled by the balancing switch to a common capacitor that provides a regulation voltage to the tunable timer which outputs a regulated duration (Tregulated) for an energizing or de-energizing phase. When Tregulated closes the balancing switch the common capacitor provides a predicted current returning inductor current to a starting value when all phases finish for providing a volt-second balance.

Abstract: One example includes an amplifier system. The amplifier system includes an input stage configured to receive an input pulse signal and to generate a reference voltage pulse based on the input pulse signal. The amplifier system also includes an amplifier stage that receives at least one power voltage and is configured to amplify the reference voltage pulse and to provide pulse-shaping of the amplified reference voltage pulse based on a change of amplitude of the at least one power voltage resulting from an amplitude of the reference voltage pulse.

Abstract: According to an embodiment, a circuit includes a protection voltage generator coupled to a first voltage node, a second voltage node, and a ground voltage node, the protection voltage generator configured to generate a plurality of protection voltages at a first plurality of nodes based on the first voltage node and the second voltage node, and a voltage protection ladder coupled between the first voltage node and a low voltage circuit, the voltage protection ladder coupled to the plurality of protection voltages at the first plurality of nodes, the voltage protection ladder configured to generate a first low voltage based on the first voltage node and the plurality of protection voltages.

Abstract: There are provided a driver circuit, a method of driving a power switch, and a ballast circuit. For example, there is provided a driver circuit configured to receive a control signal and operate a power switch. The driver circuit includes a first switch, a second switch, and a capacitor coupled to control terminals of the first and second switches. The driver circuit further includes a first diode coupled to a first bias terminal of the driver circuit and to the capacitor. Furthermore, the driver circuit includes a second diode coupled to a second bias terminal of the driver circuit and to a terminal of the power switch.

Abstract: An electronic device may include wireless communications circuitry that has first and second digital predistortion circuits. The first predistortion circuit receives a first signal at a first frequency while the second predistortion circuit receives a second signal at a second frequency. The first circuit may perform predistortion operations on the first signal using non-unity predistortion coefficients to generate a predistorted signal. The second circuit may apply unity predistortion coefficients to the second signal to generate an undistorted signal. An adder may combine the predistorted and undistorted signals to generate a combined signal that is amplified by amplifier circuitry. An antenna may transmit the amplified signal.

Abstract: A differential output stage of an amplification device, for driving a load, comprises a first and a second differential output stage portion. The first differential output stage portion comprises: a first and a second output circuit; a first driving circuit comprising a first biasing circuit; a second driving circuit comprising a second biasing circuit. The first differential output stage portion comprises: a third output circuit connected between a first node of said first biasing circuit and a first differential output terminal, having a third driving terminal connected to a first driving terminal; a fourth output circuit connected between a first node of the second biasing circuit and the first differential output terminal, having a fourth driving terminal connected to a second driving terminal.

Abstract: In some embodiments, a source follower circuit may include a first level shifter configured to receive an input voltage; an N-type Metal-Oxide-Semiconductor (NMOS) transistor having a gate terminal coupled to an output of the first level shifter; a second level shifter configured to receive the input voltage; a P-type Metal-Oxide-Semiconductor (PMOS) transistor having a gate terminal coupled to an output of the second level shifter and a source terminal coupled to a source terminal of the NMOS transistor; and an amplifier configured to receive the input voltage and to output a current at a node between the source terminal of the NMOS transistor and the source terminal of the PMOS transistor, wherein the current is determined based upon a difference between the input voltage and a reference voltage.

Abstract: In order to enable to quickly and efficiently execute, by one system, various modulation/demodulation/synchronous processes in a plurality of radio communication methods, a co-processor (22) for complex arithmetic processing, which forms a processor system (100), includes a complex arithmetic circuit (22) that executes for complex data a complex arithmetic operation required for radio communication in accordance with an instruction from a primary processor (10), and a memory controller (20, 21) that operates in parallel with the complex arithmetic circuit and accesses a memory. A trace circuit provided in the complex arithmetic circuit (22) monitors arithmetic result data for first complex data series sequentially read from the memory, and detects a normalization coefficient for normalizing the arithmetic result data.

Abstract: The method for terminating an operation of a CPE device, which comprises a front-end component for an xDSL connection of a Central Office Equipment supplying a multitude of customers, comprises the steps of: sending a power loss information to the Central Office Equipment in case of a power loss or a switch-off operation of the CPE device and powering the front-end component for a predetermined time to avoid a termination impedance change of the front-end component, by keeping the supply power up for the front-end component, to keep the termination impedance stable as long as necessary for the Central Office Equipment to avoid introduction of non-cancelled crosstalk, which may arise in xDSL connections of other customers.

Abstract: A receive circuit for use in a power converter controller includes a first amplifier coupled to receive an input pulse. A second amplifier is coupled to a first output of the first amplifier. The first output is coupled to be responsive to the input pulse and to a second output of the second amplifier. An output circuit is coupled to generate an output signal in response to the second output.

Abstract: A Class-G amplifier including a first and second driving transistor configured to receive an input voltage; a first supplying terminal connected to the first driving transistor to supply a first supplying voltage. The amplifier also comprises: a second supplying terminal connected to the second driving transistor to supply a second supplying voltage in absolute value higher than said first voltage; a first power transistor connected to the first driving transistor to form a first Sziklai pair structured to be activated by a first input voltage lower in absolute value than the first supplying voltage; a second power transistor connected to the second driving transistor to form a second Sziklai pair structured to be activated by an input signal comprised between the first supplying voltage and the second supplying voltage.

Abstract: An amplification circuit includes a first power supply; a first bipolar transistor whose collector is connected to the first power supply; a first resistor one terminal of which is connected to an emitter of the first bipolar transistor; a second bipolar transistor whose collector is connected to the other terminal of the first resistor; a second power supply; a third bipolar transistor whose collector is connected to the second power supply; a second resistor one terminal of which is connected to an emitter of the third bipolar transistor; and a fourth bipolar transistor whose collector is connected to the other terminal of the second resistor. An emitter of the second bipolar transistor is directly connected to an emitter of the fourth bipolar transistor, thereby becoming an output terminal.

Abstract: An amplifier circuit for actuating a light diode is provided. The amplifier circuit may have a small output impedance of approximately 3 Ohms, a large bandwidth having a lower threshold frequency of 200 kHz and an upper threshold frequency of 5 MHz, for example, and an amplitude of the output current of several 100 mA, for example. The amplifier circuit may have an entry stage for actuating a driver circuit that actuates the light diode by means of a direct current supply.

Abstract: A push-pull amplifier has an input node and a series connection of two resistors. The series connection comprises a first terminal, a second terminal, and a third terminal. A first resistor of the two resistors is connected between the first terminal and the second terminal. A second resistor is connected between the second and third terminals. The input node is connected to the second terminal. A first controllable current source is connected to the first terminal of the series connection for sourcing a first current to the series connection. A second controllable current source is connected to the third terminal of the series connection for sinking a second current from the series connection. A first transistor and a second transistor are connected in push-pull configuration, wherein a control input of the first transistor is connected to the first terminal of the series connection and a control input of the second transistor is connected to the third terminal of the series connection.

Abstract: A Class-G amplifier including a first and second driving transistor configured to receive an input voltage; a first supplying terminal connected to the first driving transistor to supply a first supplying voltage. The amplifier also comprises: a second supplying terminal connected to the second driving transistor to supply a second supplying voltage in absolute value higher than said first voltage; a first power transistor connected to the first driving transistor to form a first Sziklai pair structured to be activated by a first input voltage lower in absolute value than the first supplying voltage; a second power transistor connected to the second driving transistor to form a second Sziklai pair structured to be activated by an input signal comprised between the first supplying voltage and the second supplying voltage.

Abstract: The present disclosure is directed to a switched capacitor amplifier that includes a switched capacitor network and a complementary push-pull amplifier. The switched capacitor amplifier of the present disclosure can provide a larger fraction of the charge provided by a power supply and flowing through the amplifier to a capacitive load at the output of the amplifier compared to switched capacitor amplifiers that use single-ended class-A amplifiers. The switched capacitor amplifier of the present disclosure can be used in a converter stage of a pipelined analog-to-digital converter (ADC) to improve the ADC's power efficiency and/or bandwidth. It can be further generalized to be used in other applications other than pipelined ADCs.

Abstract: Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis.

Abstract: Power amplifiers (PAs) using a Doherty or other power output level sensitive configuration have been employed for several years in telecommunications (as well as other applications) to take advantage of efficiency gains. For many of these applications, baseband signals are predistorted to compensate for nonlinearities in the PAs, but because there is a “switching event” in a Doherty-type amplifier (for example), the nonlinearities become dynamically varying. As a result, digital predistortion (DPD) becomes increasingly difficult to perform. Here, DPD modules are provided that adapt to changes in dynamically varying PAs based on a determination of the average power or other relevant metric prior to transmission.

Abstract: The invention relates to a programmable filter for a radiofrequency receiver, embodiments disclosed including a filter (600) comprising an input (601) for receiving a radiofrequency signal, an output (602) for providing a filtered version of the input radiofrequency signal and a plurality of filter paths (603a-c) connected in parallel between the input (601) and output (602), each filter path comprising a buffer (604a-c) connected between the input (601) and one or more polyphase filters (605a-f), wherein each of the plurality of filter paths (603a-c) is configured to be individually selectable by providing an enable signal to a corresponding one of the buffers (604a-c).

Abstract: Systems and methods for providing one or more reference currents with respective negative temperature coefficients are provided. A first voltage is divided to provide a divided voltage, which is compared to a reference voltage (e.g., a bandgap reference voltage) to provide a control voltage. The first voltage and the one or more reference currents are based on the control voltage.

Abstract: When a conventional optical receiver circuit is used, it is difficult to achieve noise reduction or provide a multichannel capability due to a considerable circuit area increase. Disclosed is an amplifier for optical communications that includes a CMOS inverter, which has a PMOS transistor and an NMOS transistor; an input terminal, which inputs a signal into the CMOS inverter; an output terminal, which outputs a signal from the CMOS inverter; a power supply, which is connected to the CMOS inverter; a first element and a second element, which are respectively connected to the CMOS inverter; and two types of power supply paths, which are in opposite phase to each other.

Abstract: An amplifier includes a separating unit, a generator, first to fourth switching amplifiers, and an outputting unit. The separating unit separates a pulse signal into a first separated pulse signal and a second separated pulse signal. The generator generates first to fourth low speed pulse signals by using the first and the second separated pulse signal. The first switching amplifier amplifies the first low speed pulse signal. The second switching amplifier amplifies the second low speed pulse signal by using the output of the first switching amplifier as a power-supply. The third switching amplifier amplifies the third low speed pulse signal. The fourth switching amplifier amplifies the fourth low speed pulse signal by using the output of the third switching amplifier as a power-supply. The outputting unit combines and outputs the first and the second output pulse signal.

Abstract: Several push-pull linear hybrid class H amplifiers are disclosed. A split power rail provides a positive supply rail and a negative supply rail in response to a power supply control voltage. A push-pull amplifier stage is powered by the positive and negative supply rails. The amplifier stage receives an input signal and provides a corresponding amplified output signal. A power supply control circuit provides the power supply control voltage in response to the smaller of the positive and negative supply rails, and the input signal.

Abstract: Several push-pull linear hybrid class H amplifiers are disclosed. A split power rail provides a positive supply rail and a negative supply rail in response to a power supply control voltage. A push-pull amplifier stage is powered by the positive and negative supply rails. The amplifier stage receives an input signal and provides a corresponding amplified output signal. A power supply control circuit provides the power supply control voltage in response to the smaller of the positive and negative supply rails, and the input signal.

Abstract: An amplifier including complementary push and pull components, a bias component and a quiescent current balancer. The complementary push and pull components are serially coupled to one another between an electrical source and sink to generate an output signal at a common output terminal responsive to the input signal source. The bias component is coupled between the input signal source and the complementary push-pull components to bias the input signal to the push component and the input signal to the pull component by discrete amounts which reduce cross-over clipping exhibited in the output signal. The quiescent current balancer is coupled to the output terminal to balance quiescent currents in the push and the pull component at discrete levels which equilibrate amplification levels of the input signal generated by the push component and the pull component in the output signal at the output terminal.

Abstract: A semiconductor device stabilizes an operation of an input buffer. A semiconductor device includes an input potential detection unit, an input buffer, and a current sink unit. The input potential detection unit outputs a detection signal in response to a level of an input signal. The input buffer buffers the input signal by differentially amplifying the input signal through a first current sink unit. The current sink unit receives the detection signal, and in response to the detection signal, performs an auxiliary differential amplifying operation with respect to the input signal buffered by the input buffer.

Abstract: Power consumption of current sources in an amplifier circuit is reduced even during amplifier operation while keeping linearity of an output signal. The amplifier circuit is suitable for use in a signal generator that provides an output signal previously set by a user and having a known level. Positive and negative current sources receive an input voltage Vi depending on an output voltage Vo. An output resistor derives the output voltage Vo from currents provided by the positive and negative current sources. A variable bias generation circuit produces positive and negative bias voltages applied to the positive and negative current sources wherein the positive and negative bias voltages are set while the linearity of the output voltage is maintains using the known output level information.

Abstract: An amplifier including complementary push and pull components, a bias component and a quiescent current balancer. The complementary push and pull components are serially coupled to one another between an electrical source and sink to generate an output signal at a common output terminal responsive to the input signal source. The bias component is coupled between the input signal source and the complementary push-pull components to bias the input signal to the push component and the input signal to the pull component by discrete amounts which reduce cross-over clipping exhibited in the output signal. The quiescent current balancer is coupled to the output terminal to balance quiescent currents in the push and the pull component at discrete levels which equilibrate amplification levels of the input signal generated by the push component and the pull component in the output signal at the output terminal.

Abstract: A method and apparatus is provided for use in power amplifiers for reducing the peak voltage that transistors are subjected to. A power amplifier is provided with first and second switching devices and an inductor connected between the switching devices. The switching devices are driven such that the switching devices are turned on and off during the same time intervals. Differential RF power amplifiers are also provided with inductive networks coupled at various nodes of the power amplifiers. In some examples, techniques are used to stabilize differential power amplifiers by stabilizing common-mode feedback loops.

Abstract: A switched current source has a first voltage source, a second voltage source, and a third voltage source. A first transistor has a drain terminal coupled to one terminal of a load and a source terminal coupled to the third voltage source. A second transistor has drain, gate and source terminals. The drain terminal of the second transistor is coupled to the gate terminal of the first transistor. The source terminal of the second transistor is coupled to the source terminal of the first transistor. The gate terminal of the second transistor is coupled to the first voltage source. A third transistor has drain, gate and source terminals. The drain terminal of the third transistor is coupled to the gate terminal of the first transistor. The source terminal of the third transistor is coupled to the second voltage source. The gate terminal of the third transistor is coupled to the first voltage source.

Abstract: A unity gain buffer is provided. The unity gain buffer includes two complementary pairs of emitter followers and two bias current sources. The top bias current source is arranged to provide a bias current so that, if the input voltage is greater than zero, the bias current provided by the top current source increases at the input voltage increases. The bottom current source is arranged to provide a bias current so that, if the input voltage is less than zero, the bias current provided by the bottom current source decreases as the input voltage decreases.

Abstract: An opposing currents (OC) differential amplifier is disclosed that eliminates headroom constraints and other problems associated with conventional differential pair amplifiers with current source biasing. The OC differential amplifier has a higher differential gain and differential gain bandwidth than conventional differential pair amplifiers.

Abstract: An operational amplifier and use of an operational amplifier is provided that includes an input differential amplifier, which is connected to a first input and to a second input and a differential output stage, which is connected to the input differential amplifier and a first output and a second output. The differential output stage has a first branch with two first transistors, whose drain and/or collector are connected to one another and to the first output. The differential output stage has a second branch with two second transistors, whose drain and/or collector are connected to one another and to the second output. The first gates and/or the first bases of the two first transistors in the first branch are connected to one another and to a first output of the input differential amplifier. The second gates and/or the second bases of the two second transistors in the second branch are connected to one another and to a second output of the input differential amplifier.

Abstract: A disclosed operational amplifier includes: a pair of differential stages; a cascode amplifier stage; and an output stage. A threshold voltage of an output transistor constituting the output stage is higher than a threshold voltage of other transistors.

Abstract: Power amplifier circuit outputs an output voltage corresponding to an input voltage supplied, and includes positive and negative-side output units including a positive or negative-side output resistor and a positive or negative-side transistor having its source terminal connected to one end of the positive or negative-side output resistor to make a current corresponding to a voltage supplied to its gate terminal flow to the positive or negative-side output resistor, positive and negative-side bias generating units which generate a positive or negative-side bias voltage corresponding to the input voltage, and positive and negative-side control units which control the voltage to be applied to the gate terminal of the positive or negative-side transistor such that the positive or negative-side bias voltage and source voltage of the positive or negative-side transistor become generally equal, and the voltage at connection node between the positive and negative-side output units is output as the output voltage.

Abstract: The invention relates to an amplifier circuit comprising supply terminals (12, 14) for supplying the circuit with first and second supply potentials (Vdd, Vss); a current path, which runs from the first supply terminal (12) via a first biased transistor (P1a, P1b), a first node (K1a, K1b), an input transistor (Q1a, Q1b), a second node (K2a, K2b) and a second biased transistor (N1a, N1b) to the second supply terminal (14), wherein a control terminal of the input transistor is loaded with an input signal (inp-inn), and wherein the second node (K2a, K2a) forms a pick-up in a resistor chain (R2a, R1, R2b), at whose ends is supplied an output signal (outp-outn) as a voltage drop; and a feedback stage enabling the current to flow the resistor chain (R2a, R1, R2b) dependent on the input signal (inp-inn) so that the current flowing through the input transistor (Q1a, Q1b) is essentially independent of the input signal (inp-inn), wherein the feedback stage has a pair of complementarily coupled transistors (P3a, N3a, P3

Abstract: A class AB output stage includes first (MP) and a second (MN) output transistors having sources coupled to first (VDD) and second reference voltages, respectively, drains coupled to an output (13), and gates coupled to first (11A) and second (12A) conductors, respectively. Portions of first (IIN1) and a second (IIN2) input currents are sourced via a first input conductor (11) and a second input conductor (12), respectively, into and from sources of first (M2) and second (M4) transistors, respectively. Gates of the first (M2) and second (M4) transistors are coupled to the first and second conductors, respectively. First (VrefP) and second (VrefN) bias voltages are applied to gates of third (M1) and fourth (M3) transistors respectively, having sources coupled to the first and second input conductors, respectively, and drains coupled to the second conductor.

Abstract: An amplifying circuit includes an operational amplifier, a pull-up circuit and a pull-down circuit. The operational amplifier generates a first pull-up signal, a first pull-down signal and an output signal, wherein the phases of the first pull-up signal and the first pull-down signal are out of phase with the output signal. The pull-up circuit includes a first controlling module for outputting a second pull-up signal according to the first pull-up signal, and a first adjusting module for adjusting the output signal according to the second pull-up signal. The pull-down circuit includes a second controlling module for outputting a second pull-down signal according to the first pull-down signal, and a second adjusting module for adjusting the output signal according to the second pull-down signal.

Abstract: An electron turbulence damping circuit (40) for a complimentary-symmetry unit (10?) includes a first output device (12?) having a first conductivity and a second output device (14?) having a second conductivity that is opposite the conductivity of the first output device (12?). A common load connector (28?) is secured in electrical communication between a load (30?), a first current output (18?) of the first output device (12?) and a second current output (24?) of the second output device (14?). First and second resistive elements (42, 46) are secured in parallel between current inputs (16?, 22?) of the output devices (12?, 14?) and the common load connector (28?). The first and second resistive elements have a virtually identical resistance value that is greater than ten times a minimum impedance of the load (30?). The output devices (12?, 14?) may be transistors.

Abstract: An electron turbulence damping circuit (40) for a complimentary-symmetry unit (10?) includes a first output device (12?) having a first conductivity and a second output device (14?) having a second conductivity that is opposite the conductivity of the first output device (12?). A common load connector (28?) is secured in electrical communication between a load (30?), a first current output (18?) of the first output device (12?) and a second current output (24?) of the second output device (14?). First and second resistive elements (42, 46) are secured in parallel between current inputs (16?, 22?) of the output devices (12?, 14?) and the common load connector (28?). The first and second resistive elements have a virtually identical resistance value that is greater than ten times a minimum impedance of the load (30?). The output devices (12?, 14?) may be transistors.

Abstract: A wide band amplifier includes a core amplifier having input terminals and output terminals for, respectively, receiving differential input signals and providing amplified differential output signals. A bandwidth peaking network is coupled to the core amplifier and includes (a) a first coil and a first resistor connected in series and (b) a second coil and a second resistor connected in series. The first coil and resistor and the second coil and resistor, respectively, are coupled to the core amplifier for receiving the amplified differential output signals. The bandwidth peaking network is configured to increase the frequency bandwidth of the amplifier. The bandwidth peaking network includes (a) a first node formed between the first coil and resistor, (b) a second node formed between the second coil and resistor, and (c) a third resistor is connected between the first node and the second node. This resistor is free of current flow at low frequency operation of the amplifier.

Abstract: An amplifying circuit which may be useful in a diamond buffer amplifier or operational amplifier includes an input transistor including an emitter, a collector, and a base coupled to receive an input voltage. An adjustable current source circuit is coupled between a first reference voltage and the emitter of the input transistor. A current source is coupled between a second reference voltage and the collector of the input transistor. An isolation resistor has a first terminal coupled to an output terminal of the adjustable current source circuit and a second terminal coupled to the emitter of the input transistor. A current follower circuit is coupled between the collector of the input transistor and an input terminal of the adjustable current source circuit. A feed-forward capacitor is coupled between the collector of the input transistor and the first terminal of the isolation resistor.

Abstract: A voltage comparator that realizes high-speed operation with a simple structure includes an input differential stage having a first differential pair and a second differential pair, into which a differential voltage is inputted from differential input terminals In+ and In?, with reverse polarity to each other, folded cascode-type differential stages, which adds a differential output signal of the first differential pair and a differential output signal of the second differential pair and is connected to a differential output of the input differential stage, and oppositely disposed first and second current mirror circuits, which receive differential outputs of the folded cascode-type differential stages into their respective inputs, with reverse polarity to each other and their outputs connected in common to an output terminal. The folded cascode-type differential stage adds the differential output signal of the first differential pair and the differential output signal of the second differential pair.