Abstract: A turn-around stage is provided that accepts the full current swing from an input stage while maintaining a low quiescent current. The circuitry provides Class AB operation with quiescent currents that are significantly less than the maximum signal current so that overall power consumption is significantly reduced. Also, the amount of noise and offset contributions of the circuit are reduced by reducing the transconductances associated with transistors included in the turn-around stage.

Abstract: Disclosed is a CMOS transistor amplifier for small RF signals which operates in a Class AB mode. The serially connected P channel and N channel transistors of the CMOS transistor pair have DC bias voltages applied to the control gates, and the small input signal is capacitively coupled to the gates of the CMOS transistor pair. In a preferred embodiment, the DC voltage bias for the P channel transistor is derived from a second P channel transistor which is approximately identical to the first P channel transistor in structure with the second P channel transistor serially connected with the current source and the voltage at the gate/drain of the transistor resistively coupled to the gate of the first P channel transistor.

Abstract: A source follower circuit receives, at its gate, an input signal and outputs an input current that is in accordance with the input signal. A current transfer circuit maintains constant the sum of the input current and an output current that is to be applied to a first node. A push-pull circuit includes a first transistor that directly receives, at its gate, the input signal and a second transistor having its gate connected to the first node. The voltage gain of the source follower circuit that receives the input signal is equal to or less than 1, so that the gain of the gate voltage of the second transistor to the input signal can be reduced. The difference in voltage gain between the first and second transistors can be reduced, so that it is possible to easily design a push-pull amplifier with a stable operation.

Abstract: A circuit configuration with an integrated amplifier is described. The amplifier has an output stage that is connected to a supply potential terminal and a reference potential terminal. A pair of complementary output transistors couples the amplifier with a tri-state output. Given an interruption of an operating-current supply that is connectible to the reference and supply potential terminals, the tri-state output is put into a high-impedance state by the circuit configuration. To this end, two blocking transistors are provided, which can be supplied by respective charge pump circuits. For instance, for sensor applications in which a high operational reliability is required, the present circuit configuration prevents the misinterpretation of measurement results given disturbances, for a small outlay.

Abstract: A class AB amplifier circuit includes a complementary output stage and a biasing circuit for biasing the output stage. The complementary output stage includes a P-type MOS transistor and an N-type MOS transistor, and the biasing circuit includes a bipolar transistor. The emitter and collector of the bipolar transistor are respectively connected to the gates of the P-type and N-type MOS transistors. The bipolar transistor is biased for controlling a bias voltage between the respective gates of the P-type and N-type MOS transistors.

Abstract: A power amplifier has a pair of FETs of opposite kinds connected together to form a source/drain circuit connected with an output. A second pair of high speed transistors is connected to the input and forms a collector/emitter circuit connected to the gates of the FETs. Capacitors are connected across the second pair of transistors and the pair of FETs respectively. Opposing current sources connect with the bases of the second pair of transistors via a resistor divider.

Abstract: An operational amplifier includes a first stage, and a second stage with an input connected to an output of the first stage and an output connected to a load. The second stage includes between its input and its output a first signal path for driving the load in a first direction, and a second signal path for driving the load in the opposite direction. The first and second signal paths have substantially equal gains for small signals, substantially equal output impedances for small and large signals, and substantially equal output-current capabilities.

Abstract: An improved line driver and method for increasing the available signal transmit power on a transmission line are disclosed. The improved line driver achieves an available transmit power increase by limiting the output stage signal path to NMOS and NPN bipolar semiconductor devices. The output stage of the improved line driver may comprise a first amplifier, a second amplifier, a first transformer, a second transformer, and a plurality of back-matching resistor networks. A second embodiment of an improved output stage of a line driver may comprise a first amplifier, a second amplifier, a transformer, and a plurality of back-matching resistor networks. Both preferred embodiments may be implemented with CMOS and bipolar semiconductor devices, as well as, a combination of the two semiconductor technologies.

Abstract: A high output amplifier includes a comparison amplifier having a first input, a second input, and an output, wherein a set voltage is applied to the first input, a voltage of the output is coupled to the second input, and the output is generated in response to a difference between the voltage applied to the first input and the voltage coupled to the second input. The high output amplifier also includes a low-pass filtering device that receives and performs low-pass filtering on the output of the comparison amplifier, a conversion device that converts the output of the low-pass filtering device to complementary signals, and a push-pull output device, driven by the complementary signals, that supplies electrical current to a load, wherein an increase in the electrical current supplied by the push-pull output device is decreased by changes in the load due to the low-pass filtering device.

Abstract: An amplifier circuit that includes an amplifier stage and an output stage, and local feedback between these stages to drive a biasing string associated with the amplifier stage using the potential at the output stage. In one embodiment, the local feedback line is coupled between the output stage and the biasing string to remove the loading effect of the biasing string on the amplifier stage. In another embodiment, the local feedback line is coupled between the switches of the amplifier stage and the switches of the output stage to bias the amplifier stage using the output stage.

Abstract: An amplifier includes a push-up circuit and a pull-down circuit. The push-up circuit includes a first differential pair and a first driving circuit. The first driving circuit is connected to the first differential pair in a cascade manner. The first driving circuit has a common source amplifying circuit formed of a MOS (metal-oxide-semiconductor). The pull-down circuit includes a second differential pair and a second driving circuit. The second driving circuit is connected to the second differential pair in a cascade manner. The second driving circuit has a common source amplifying circuit formed of a MOS. A portion of a normal operation voltage range of the push-up circuit overlaps a portion of a normal operation voltage range of the pull-down circuit.

Abstract: An RF power amplifier is provided for use with wireless transmission systems such as cellular phones. An RF power amplifier includes direct drive amplifier circuitry operating in a push-pull scheme. The RF power amplifier includes a pair of switching devices driven by a pair of mutually coupled inductive devices. The inductive devices may be magnetically or capacitively coupled together. The RF power amplifier may be formed on a single integrated circuit and include an on-chip bypass capacitor. The RF power amplifier may utilize a voltage regulator for providing a regulated voltage source. The RF power amplifier may be provided using a dual oxide gate device resulting in an improved amplifier. The RF power amplifier may be packaged using flip chip technology and multi-layer ceramic chip carrier technology.

Abstract: Disclosed is a CMOS transistor amplifier for small RF signals which operates in a Class AB mode. The serially connected P channel and N channel transistors of the CMOS transistor pair have DC bias voltages applied to the control gates, and the small input signal is capacitively coupled to the gates of the CMOS transistor pair. In a preferred embodiment, the DC voltage bias for the P channel transistor is derived from a second P channel transistor which is approximately identical to the first P channel transistor in structure with the second P channel transistor serially connected with the current source and the voltage at the gate/drain of the transistor resistively coupled to the gate of the first P channel transistor.

Abstract: A power amplifying circuit according to the invention is provided with a first predriver that amplifies input voltage and outputs first driving voltage and second driving voltage lower than the first driving voltage, a second predriver that amplifies the input voltage and outputs third driving voltage and fourth driving voltage higher than the third driving voltage, a first push-pull output circuit including a first PMOS transistor and a first NMOS transistor to the respective gates of which the first driving voltage and the third driving voltage are respectively input, a second push-pull output circuit including a second PMOS transistor and a second NMOS transistor to the respective gates of which the second driving voltage and the fourth driving voltage are respectively input and a common output terminal connected to the output terminal of the first push-pull output circuit and the output terminal of the second push-pull output circuit in common.

Abstract: A method and apparatus is directed to a rail-to-rail MOS amplifier that operates with a very low power supply. An input stage amplifier operates over rail-to-rail common-mode voltages. The input stage amplifier includes two differential input stages that steer current to loads in a class AB turnaround stage. The class AB turnaround stage converts the differential signals into a single signal that is driven into an output stage amplifier. The output stage amplifier includes level shifting buffer amplifiers that are arranged to bias a pair of MOS output transistors. Each level shifting buffer amplifier is arranged to bias a MOS transistor in a sub-threshold operating region such that the MOS transistor operates as a resistor. The MOS resistor works in conjunction with a MOS diode to provide an AB bias voltage to a gate of a respective one of the output transistors.

Abstract: An apparatus for an improved output buffer includes a symmetrical pre-gain stage and a gain stage. The pre-gain stage includes a pair of matched differential amplifiers that are arranged to provide a differential intermediary signal. The gain stage is arranged to receive the differential intermediary signal and provide a single-ended output signal. The pre-gain stage differential amplifiers include transistors that are arranged as differential pairs, where each of differential pair transistors is minimally sized to provide very low capacitive loading. The pre-gain stage differential amplifiers are matched such that symmetrical amplification is obtained from the differential intermediary signal. The pre-gain stage arrangement provides for a differential intermediary signal such that common-mode noise rejection and power supply noise rejection are enhanced.

Abstract: A class AB buffer (or amplifier) is disclosed for driving a large capacitive load. The disclosed CMOS class AB buffer can drive capacitive loads, for example, in excess of 100 pF, while operating from a voltage supply as low as 1.5 volts. The disclosed class AB buffer includes a pair of driving transistors that are cross-coupled through an amplifier and level shifting circuitry, such as transistor circuitry, and a pair of current source transistors each having a gate terminal connected to an output of the corresponding amplifier and a gate terminal of an output transistor, and a drain terminal connected to a source terminal of the driving transistors. The driving transistors are prevented from entering a linear region by connecting a drain terminal of each of the driving transistors to a positive power supply voltage. The threshold voltage of only one transistor must be overcome before the transistors conduct current, since the gate-sources of the driving and current source transistors are not in series.

Abstract: A CMOS amplifier which has improved linear performance by using nonlinear amplifier circuits. The CMOS amplifier provides the same input signal to an NMOS transistor amplifier and a PMOS transistor amplifier. The output of one of the two amplifiers is phase-shifted 180 degrees, and the outputs of both amplifiers are then combined for providing an output signal having reduced nonlinearities.

Abstract: A wide bandwidth, multi-FET current sharing output stage, MOS audio power amplifier employs multiple feedback loops. An audio input is supplied to a voltage feedback amplifier stage driving a push-pull voltage gain/phase splitter stage. A bias adjustment stage driven from the push-pull voltage gain/phase splitter stage drives a current drive stage. The current drive stage drives an output stage comprising a plurality of paralleled current shared individual MOS output transistors driving an output nodeconnected to a load. Up to three feedback loops are employed. A first voltage feedback loop comprises a voltage feedback stage having an input connected to a voltage divider driven from the first terminal of the load and an output connected to a feedback input node in the voltage feedback amplifier stage.

Abstract: In an amplifier device, a negative output voltage (−) of a differential amplifier stage corresponding to an input signal voltage (Vin) is supplied to the gate of Output transistor M25 for charging electrical charges to Capacitive load (80). A current corresponding to a positive output voltage (+) of the differential amplifier stage is supplied to Node (A) through which the gate of Output transistor M26 for discharging electrical charges from Capacitive load (80) is connected to Constant current source (4). This current becomes a value (Iy+&Dgr;I) according to the voltage (Vin). By changing the gate voltage of Output transistor M26, it enters ON, and the electrical charges are discharged as a current I3 from Capacitive load (80). The voltage (Vin) is converted to a current by Voltage-current converter (1), and Current-voltage converter (2) then converts this current to a voltage.

Abstract: An amplifier output stage is described containing a preliminary stage, a final stage and a control device. The quiescent current that flows through transistors of the final stage is adjusted by the preliminary stage. For this, a current that is proportional to the quiescent current is generated in the control device from which control voltages are derived and controlled. The preliminary stage contains adjustable current sources for adjusting the quiescent current in a final step which are controlled by the control voltages.

Abstract: A circuit configuration with an integrated amplifier is described. The amplifier has an output stage that is connected to a supply potential terminal and a reference potential terminal. A pair of complementary output transistors couples the amplifier with a tri-state output. Given an interruption of an operating-current supply that is connectible to the reference and supply potential terminals, the tri-state output is put into a high-impedance state by the circuit configuration. To this end, two blocking transistors are provided, which can be supplied by respective charge pump circuits. For instance, for sensor applications in which a high operational reliability is required, the present circuit configuration prevents the misinterpretation of measurement results given disturbances, for a small outlay.

Abstract: A dual-drive coupling for an output stage of class AB amplifier is disclosed. A class AB amplifier comprises a PMOS output device and an NMOS output device coupled together. Two signal sources are used; one to drive the PMOS output device and one to drive the NMOS output device. The signal source driving the PMOS output device has a transconductance that is three times greater than the signal source driving the NMOS output device because the PMOS device is about three times bigger than the NMOS output device. A floating resistor network, comprised of an NMOS transistor and a PMOS transistor is coupled between the coupling of the signal sources with the output devices. A replica device can be added between the PMOS output device and its corresponding signal source to replicate the drain voltage of the signal source for the NMOS output device.

Abstract: An active digital voltage regulator circuit is a two terminal device that is connected in shunt to first and second power supply input lines. The active digital voltage regulator circuit stores energy during times when the local power supply voltage is greater than a predefined voltage, e.g., during times when the parasitic inductances supplement the local power supply voltage. The active digital voltage regulator circuit uses the stored energy to supplement the local power supply voltage during times when the local power supply voltage starts to collapse, e.g., during periods when inductive losses are preventing the power supply from maintaining the local power supply voltage. Consequently, digital active voltage regulator circuit smooths the local power supply voltage by greatly ameliorating the ripple voltages associated with parasitic inductances and resistances. A control circuit within the regulator circuit is a combination of two self-biasing and off-set nulling power supply monitor circuits.

Abstract: A class AB amplifier having an output stage comprising complementary common source transistors (T1, T2) has means for setting the quiescent current. These comprise a bias resistor (R1) through which a bias current is passed and which is connected between the gates of transistors (T1 and T2) to set their voltages. The current through the bias resistor (R1) is derived from two reference transistors (T3 and T4) which each have the desired quiescent current passed through them by current sources (3, 5). The gate voltages of the reference transistors (T3, T4) are applied across a reference resistor (R2) and the current through the reference resistor (R2) is mirrored (T5 to T9) to the bias resistor (R1).

Abstract: A CMOS class AB amplifier has an adaptive level shift circuit, a compensated capacitor, and an output transistor pair. The adaptive level shift circuit includes a current mirror circuit, a diode transistor, a switch transistor, and a current source transistor. The diode transistor is utilized as a bias for driving the switch transistor so as to provide a relatively low linear resistor for being used as a feedback. Therefore, the Q (quality factor) value of the gyration inductance can be effectively reduced and the occurrence of the peak gain can be suppressed effectively, so as to maintain a desired gain margin.

Abstract: A push-pull amplifier circuit includes a push-pull output circuit having a P-channel FET 11 and an N-channel FET 10 connected in series between supply potentials VDD and VSS, a gate potential difference circuit 16A having ends OP and ON connected to the gates of the FET 11 and FET 10, respectively, wherein the voltage VPN between OP and ON is adjusted depending on a control signal VG3, an input circuit 17 for changing potentials of OP and ON in response to an input voltage VI while keeping the voltage VPN between OP and ON substantially constant, a constant current source 40 for outputting a reference current IS, and an idle current detecting and comparing circuit 30 for detecting a current proportional to an idle current flowing through the FET 11 and FET 10 and generating a control signal VG3 for the circuit 16A so that the detected current approaches a reference current IS.

Abstract: A class AB amplifier biasing circuit is provided for controlling the quiescent state of a pull-up output device and a complimentary pull-down output device. The biasing circuit includes first and second current sources, each having a floating resistor configured to supply current to the pull-up and pull-down devices, respectively. The biasing circuit also includes gate control circuits for controlling the gate voltages of the first and second floating resistors. A device replica transistor is connected to a voltage node associated with the gate of the either the pull-up device or the pull-down device.

Abstract: A CMOS Class F amplifier uses a differential input to eliminate even-order harmonics, thereby avoiding the need for circuits that are tuned to the second harmonic. This also minimizes the sensitivity of the design to changes in the second harmonic frequency and/or the particular component values selected for the tuned circuit. Third-order harmonics are reduced by controlling the phase relationship between the differential inputs. Additional efficiency is achieved by dynamically controlling the impedance of the amplifier as a function of output power level.

Abstract: An operational amplifier includes a differential input stage (30) having first (2) and second (3) input conductors, a class AB output stage (20) coupled to an output of the differential input stage (30) and including a pull-up transistor (M11) having a source coupled to a first supply voltage (VDD), a drain coupled to an output conductor (17), and a gate coupled to a first terminal (14) of a class AB control circuit (11), and a pull-down transistor (M12) having a source coupled to a second supply voltage (GND), a drain coupled to the output conductor (17), and a gate coupled to a second terminal (15) of the class AB control circuit (11). A differential input signal is applied between the first (2) and second (3) input conductors, and simultaneously also is applied between first and second inputs of a first unbalanced differential amplifier (31) and between first and second input to the second unbalanced differential amplifier (32).

Abstract: An output stage suitable for low voltage operation and capable of providing an essentially symmetrical rail-to-rail output voltage is disclosed. The output stage includes a first field effect device having a first drain, a first gate, and a first source coupled to a power supply VCC. The output stage further includes a second field effect device complimentary to the first field effect device, having a second drain, a second gate, and a second source coupled to a power supply having a nominal voltage of VEE. Further, the second drain is coupled to the first drain. Also included in the output stage is an output sink network coupled to the second field effect device. The output sink network drives the second field effect device such that a product of a current in the first field effect device and a current in the second field effect device is essentially equal to a predetermined constant during operation of the output stage.

Abstract: An operational amplifier including a differential amplifier circuit, and a reverse output buffer. The reverse output buffer has a first forward switch, a second forward switch, a first reverse switch, and a second reverse switch. The first forward switch and the first reverse switch and the second forward switch are connected in series between a reference voltage source and a grounding terminal. The second forward switch being connected between the output terminal of the operational amplifier and the grounding terminal. The second reverse switch and the second forward switch are electrically connected by a bias voltage provided from a bias voltage input terminal connected thereto, so that when the second bias voltage input terminal is at low potential and the first bias voltage is at high potential, the second reverse switch is on, and the second forward switch is off. The operational amplifier will then function normally.

Abstract: Apparatus and methods to provide high supply rejection and rail-to-rail output swing at the output of an amplifier circuit. A power source supplies power to a low noise regulator and to a differential amplifier output stage. The low noise regulator supplies power to an input stage that is coupled to the output stage, and also provides a reference to the output stage for power supply noise reduction purposes. This configuration of first and second circuits give the output both full rail-to-rail swing and good supply rejection in both stages. Exemplary embodiments are disclosed.

Abstract: An operational amplifier includes a first stage, and a second stage with an input connected to an output of the first stage and an output connected to a load. The second stage includes between its input and its output a first signal path for driving the load in a first direction, and a second signal path for driving the load in the opposite direction. The first and second signal paths have substantially equal gains for small signals, substantially equal output impedances for small and large signals, and substantially equal output-current capabilities.

Abstract: An amplifier output stage is described containing a preliminary stage, a final stage and a control device. The quiescent current that flows through transistors of the final stage is adjusted by the preliminary stage. For this, a current that is proportional to the quiescent current is generated in the control device from which control voltages are derived and controlled. The preliminary stage contains adjustable current sources for adjusting the quiescent current in a final step which are controlled by the control voltages.

Abstract: A wide bandwidth, multi-FET current sharing output stage, MOS audio power amplifier employs multiple feedback loops. An audio input is supplied to a voltage feedback amplifier stage driving a push-pull voltage gain/phase splitter stage. A bias adjustment stage driven from the push-pull voltage gain/phase splitter stage drives a current drive stage. The current drive stage drives an output stage comprising a plurality of paralleled current shared individual MOS output transistors driving an output nodeconnected to a load. Up to three feedback loops are employed. A first voltage feedback loop comprises a voltage feedback stage having an input connected to a voltage divider driven from the first terminal of the load and an output connected to a feedback input node in the voltage feedback amplifier stage.

Abstract: An ultra low voltage CMOS, class AB power amplifier has internal compensation using only parasitic gate capacitance.

Abstract: An active digital voltage regulator circuit is a two terminal device that is connected in shunt to first and second power supply input lines. The active digital voltage regulator circuit stores energy during times when the local power supply voltage is greater than a predefined voltage, e.g., during times when the parasitic inductances supplement the local power supply voltage. A control circuit within the regulator circuit is a combination of two self-biasing and off-set nulling power supply monitor circuits. Each power supply monitor circuit further includes a differencing, non-overlapped, dual-output amplifier connected to the first and second power supply input lines. The differencing, non-overlapped, dual-output amplifier includes a predriver stage and an output stage, both of which are connected to the first and second power supply input lines.

Abstract: An improved bias network for reducing cross-over distortion in a device having complementary p-MOS and n-MOS power transistors includes complementary helper transistors coupled to power transistors for discharging currents while the power transistors are biased in sub-threshold regions of operation. The bias network further includes complementary resistors coupled to the power transistors for biasing the power transistors within saturation regions of operation and for biasing the helper transistors within saturation regions of operation, and complementary feedback circuits connected to the power transistors and operating in conjunction with the resistors for biasing the helper transistors within the saturation regions of operation. Preferably, each of the power transistors are biased into the saturation regions by gate voltage swings of no more than 200 millivolts from the sub-threshold region.

Abstract: A power amplifier that provides wide-band, high efficiency, high voltage, HF power amplification over a large dynamic operating range. In one embodiment, the power amplifier includes a driver amplifier, an intermediate power amplifier comprising a coherently combined array of two transistors, and a final power amplifier comprising a coherently combined array of multiple transistors. The two stage driver amplifier drives the intermediate power amplifier, which drives the final power amplifier. Preferably, because of the inherent linearity, dynamic range, and power limiting requirements, the driver amplifier includes two transistor devices that are of the silicon power bipolar type, operating in class A with classic common-emitter circuit configuration. Preferably, the transistors used in the intermediate power amplifier and the final power amplifier are MOSFETS operating in a non-classic DC grounded-drain, RF common source circuit configuration.

Abstract: A class AB CMOS output stage for an operational amplifier with a rail-to-rail output swing includes a pair of complementary control transistors connected in opposing phase to each other. Connection of the complementary control transistors is made between driving nodes of a pair of complementary output transistors driven by a differential signal. The differential signal is provided by a pair of differential signal input lines connected to an input stage of the operational amplifier. Biasing of the pair of complementary control transistors is by the differential signal.

Abstract: A parallel push-pull amplifier using a complementary device, which basically operates for a B or AB-level amplification while having a common source configuration, thereby being capable of amplifying the full wave of an input signal without any distortion while obtaining a high gain at a radio frequency. The complementary device consists of an active element for amplifying a half wave of an input signal and a complementary active element for amplifying the other half wave of the input signal. The complementary active element has a duality with respect to the active element. The amplifier also includes bias circuits adapted to set respective operating points of the active and complementary active elements. Where the active and complementary active elements constitute a CMOS device, they are connected together in the form of a push-pull connection using a common source type configuration.

Abstract: An output stage of an amplifier circuit includes a sinking bipolar circuit 22 for sinking current from an external load 12; a sourcing MOS transistor 14 for sourcing current to the external load 12, a source of the MOS transistor 14 coupled to the sinking bipolar circuit 22 to form a common output node 34; a mirroring MOS transistor 16 having a gate coupled to a gate of the sourcing MOS transistor 14 such that current in the sourcing transistor 14 approximately mirrors current in the mirroring transistor 16; and a current mirror circuit 39 responsive to the mirroring transistor 16 and coupled to control current flow through the sinking bipolar circuit 22.

Abstract: A complementary class AB current mirror circuit with a constant current gain which, when driven by a transconductance amplifier, provides a constant overall voltage gain over a wide range of output current. Such current mirror circuit includes cross-coupled pairs of current mirror circuits, both of which are driven by a common reference current and each of which selectively receives a respective portion of the input signal current. The upper pair of current mirror circuits includes: an input current mirror circuit which generates a drive current for the output stage of the lower pair of current mirror circuits; and an output current mirror circuit which generates the source, or "push," portion of the output signal current.

Abstract: A CMOS output stage for providing stable quiescent current. The output stage includes a circuit that relates the quiescent current to the channel geometry of a power NMOS transistor and of an NMOS reference transistor of a reference current source. This configuration removes the dependency of the quiescent current on a power PMOS transistor used in the CMOS output stage, the threshold voltage of which may drift over time under high current and voltage operation, and adversely affects quiescent current stability.

Abstract: A novel amplifier circuit having a wide output signal amplitude range and a small current consumption is disclosed. A signal conversion circuit converts the input signal thereof into a first current signal. A current calculation circuit calculates the difference between a predetermined current value and the first current signal. A current amplifier circuit amplifies the difference current. Since the difference current calculated by the current calculation circuit is amplified, the dynamic range of the output can be widened with a small current flowing in the signal conversion circuit and the current calculation circuit. Further, this amplifier circuit, if designed to supply no output current under no load, can reduce the current consumption since the only steady current that flows under that condition is the small one flowing in the signal conversion circuit and the current calculation circuit.

Abstract: A monolithic class AB (push-pull) low noise amplifier having feedback and self bias. The low noise amplifier exhibits low power, high intercept point, low noise figure, well matched terminal impedances over wide range of frequency, and may be monolithically implemented. The amplifier may be produced using CMOS process technologies. The amplifier comprises NMOS and PMOS transistors serially coupled between a voltage rail and ground. The amplifier uses self biasing embodied in a bias resistor coupled between an input shunt capacitor and respective drains of the NMOS and PMOS transistors, which allows for maximum gate-to-source voltage and higher transconductance for a minimum aspect ratio (W/L). This results in a wider bandwidth and reduced power for the amplifier.

Abstract: An amplifier arrangement having a first and a second output transistor, which are drain-connected to the output terminal. A driver stage (100), prevents the output transistors from becoming non-conductive, thereby reducing cross-over distortion. This is achieved by applying an input signal via the sources of a source coupled transistor pair to the gates of the output transistors. Additional source followers are provided for defining gate-sources voltages which prevent the output transistors from becoming non-conductive.

Abstract: A differential cMOS push-pull buffer includes a pair of push-pull sections, a cMOS current source transistor connected to the push-pull sections for providing current thereto, and two cMOS trickle current transistors, each connected to an output node of a respective push-pull section for conducting a trickle current at the output node. In each push-pull section a trickle current enhances the speed of operation, thereby maintaining desirable attributes in output waveforms.

Abstract: An operational amplifier has a differential amplification section, an output section, a control signal generation unit, and a drive control unit. The output section has a first transistor of a first conductivity type and a second transistor of a second conductivity type that is opposite to the first conductivity type. The first and second transistors are connected in series between a first power source unit and a second power source unit, and the first transistor is driven according to an output of the differential amplification section. The control signal generation unit is used to detect a current flowing through the first transistor and generate a control signal in response to the detected current. The drive control unit is used to drive the second transistor in response to the control signal.