Abstract: A system and a method are disclosed for providing a constant swing high-gain complementary differential limiting amplifier. High gain for the differential amplifier is created by providing a current to the driving transistors that is a combination of any of (a) constant current, (b) transconductance based current, and (c) temperature compensated based current. A constant differential output swing is created by providing a varying differential current to the output load resistors of the differential amplifier that tracks process and temperature variations within the output load resistors.

Abstract: A power amplifier includes an input circuit, three power supply lines with voltages successively decreasing in an order of first, second and third power supply lines, a push-side driving circuit and a pull-side driving circuit which receive control signals from the input circuit, three driving signal lines which are led out of the driving circuits, three output transistors which have current paths connected at one ends to the first, second and third power supply lines, and have gates connected to the three driving signal lines, respectively, an output terminal which is commonly connected to the other ends of the current paths of the output transistors, an impedance circuit which adjusts a gate impedance of the output transistor connected to the third power supply line, and a feedback circuit connected between the output terminal and the input circuit.

Abstract: A method and apparatus is provided for use in power amplifiers for reducing the peak voltage that transistors are subjected to. A power amplifier is provided with first and second switching devices and an inductor connected between the switching devices. The switching devices are driven such that the switching devices are turned on and off during the same time intervals.

Abstract: Efficient low EMI switching output stages and methods that may be used, by way of example, in class D amplifiers. The output stages comprise class AB output stages having complementary FETs for the output. The FETs are switched in response to a switch control signal in a manner to simultaneously switch the FETs so that both FETs are not off at the same time. The extent to which both FETs are on at the same time is controlled to maintain efficiency of the circuit, and preferably the output voltage slew rate is set by circuit parameters to a relatively low slew rate. By maintaining conduction in one or both the FETs during the transition, forced conduction through a parasitic diode in either FET, as may occur in response to an inductive load (an effect commonly called freewheeling), together with the rapid and wide voltage swing associated therewith, is avoided.

Abstract: A low voltage, high bandwidth, enhanced transconductance, source follower circuit constructed from MOS FET devices, which operates in a class AB mode. The drain current of the source follower is sensed with a folded cascode device. The sensed current is multiplied by a common source device of same type (NMOS or PMOS) as the source follower, and directed to the output load. Over limit current load at the source follower drain is sensed by a common source device of the opposite type (NMOS or PMOS), which also supplies the necessary extra current to the output load. This allows the device to supply significantly more than the quiescent current in both sourcing and sinking the output. Average power consumption for driving a given load is significantly reduced, while maintaining the large bandwidth of traditional source follower designs, and the capability for use in either voltage regulators or in a current conveyor.

Abstract: An operational amplifier is provided that includes a Class-AB stage and a Class-B stage coupled in parallel with each other to form an output stage. The Class-AB stage is operable to drive an output load. The Class-B stage is also operable to drive the output load and includes a first level-shifting circuit and a second level-shifting circuit. Each of the level-shifting circuits includes a neutralizing transistor.

Abstract: A CMOS operational amplifier with a Class AB output stage has an output terminal and an input stage driving the output stage. The Class AB output stage includes a pair of p-channel and n-channel output transistors series-connected between the VDD and VSS supply terminals of a power supply. Each of the output transistors has associated biasing circuitry with a pair of positive and negative driving inputs and a biasing input. The input stage has driving outputs connected to corresponding ones of the driving inputs of the output stage. Each driving output is derived from the drain of a MOS transistor connected in series with a diode connected MOS transistor between the VDD and VSS supply terminals. By avoiding the conventional stacked MOSFETs that would set the minimum supply voltage to more than two threshold voltages, the op-amp can be operated over the full range of supply voltage.

Abstract: A CMOS-implemented transconductance amplifier has an input gain stage coupled to a CMOS output stage. The inverting input of the input gain stage is coupled to an input/output port to which an input voltage is coupled. The CMOS output stage has a first, transconductance CMOS transistor pair, whose source-drain paths are series-coupled between first and second outputs of the input stage. A second, transimpedance CMOS transistor pair have their source-drain paths series-coupled between first and second power supply terminals, and gate inputs coupled to outputs of the input stage. A third CMOS transistor pair is coupled in parallel with the second CMOS transistor pair to form a pair of current mirror stages. The current output is coupled to a common connection of the third CMOS pair.

Abstract: A digital transmitter (20) that may be advantageously used in a high-frequency transceiver, such as a wireless telephone handset, is disclosed. The transmitter (20) includes digital upconverter functions (36I, 36Q) that operate in combination with a digital band-pass sigma-delta modulator (40) to generate modulated digital signals at a sample frequency that is a multiple of the transmit frequency. The digital band-pass sigma-delta modulator (40) applies a noise transfer function in a feedback filter (72) in which the center of the pass band corresponds to the transmit frequency, and in which notches in the characteristic can be symmetrically or asymmetrically selected to correspond to specific frequencies, such as the receive band frequency, in which transmit noise is to be minimized.

Abstract: A semiconductor integrated circuit includes first and second differential amplification devices to amplify a voltage difference of input signals inputted from a positive input terminal and a negative input terminal, first and second addition devices to add an output of the first differential amplification device and the output of the second differential amplification device, an output stage control device controlled by the first and second addition devices, and output stage controlled by the output stage control device, and an output terminal connected to the output stage.

Abstract: A method and circuits of a high isolation and high-speed buffer amplifier capable to handle frequencies in the GHz range have been achieved. The output to input isolation is primary dependent on the gate-source capacitance of the active buffer transistor. Having two or more in series and by reducing the impedance between them a high isolation can be achieved. The input signals are split in several signal paths and are amplified in the push-pull mode using source follower amplifiers. Then the amplified signals are being combined again. The amplified output current is mirrored applying a multiplication factor. Said method and technology can be used for buffer amplifiers having differential input and differential output or having single input and single output or having differential input and single output. A high reversed biased (output to input) isolation and a reduced quiescent current have been achieved.

Abstract: The present invention is provided with a first, a second and a third differential amplifier which operate at a source voltage with respect to a reference voltage or a voltage between these; an output stage having a first and a second transistor driven complimentarily; a first resistor connected to an input terminal; a second resistor connected to an output of the first differential amplifier circuit; and a first and a second feed back resistor connected to an output terminal of the output stage circuit.

Abstract: A common operational amplifier for a pipeline circuit is provided. The common operational amplifier is used by the stage circuits of the pipeline circuit by turns according to a predetermined timing. The common operational amplifier comprises an operational amplifier circuit, a multiplexer circuit and a demultiplexer circuit. The multiplexer circuit is provided for selecting a signal set of a stage circuit to be amplified to couple to the operational amplifier circuit, and the demultiplexer circuit is provided for transmitting the amplified signal set to the corresponding stage circuit.

Abstract: A CMOS amplifier includes a CMOS inverter and a bias circuit coupled in a feedback loop between the output and input of the inverter. The bias circuit provides linear biasing so that the inverter can apply a desired gain to a high frequency input signal. The bias circuit can include an operational amplifier (op-amp) providing positive feedback control between the output and input of the inverter. By providing a reference voltage to the other input of the op-amp, the input of the inverter is regulated such that its output is driven to the reference voltage. This in turn forces the inverter to operate in its linear region, so that the inverter applies non-distorting amplification to the input AC signal. The AC signal is prevented from affecting the operation of the bias circuit by resistors coupling the bias circuit to the op-amp.

Abstract: A class-AB MOS output stage that provides higher gain and significantly lower distortion. The class-AB MOS output stage includes a PMOS output transistor and an NMOS output transistor coupled between positive and negative supply voltages such that the MOS output transistors operate in a common source mode, a first biased class-AB control circuit coupled between the output transistor gates, a first current source coupled between the gate of the PMOS output transistor and the positive supply, a second biased class-AB control circuit, and a second current source coupled between the second control circuit and the positive supply. The second class-AB control circuit is coupled between the second current source and a non-inverting input of the output stage. The gate of the NMOS output transistor is employed as the inverting input of the output stage, which further includes two differential amplifiers for controlling the first and second current sources.

Abstract: A class AB output circuit includes a P-channel pullup transistor (M13) having a source coupled to a supply voltage, a drain coupled to an output(10), a gate coupled to respond to an input signal on an input(9), an N-channel pulldown transistor (M1) having a drain coupled to the output, a source coupled to ground, and a gate coupled to respond to the input signal. A first N-channel transistor (M2) has a drain coupled to a gate of the output transistor and the supply voltage by means of a current source (8) and a source coupled to ground by means of a second current source (13). A first diode-connected N-channel transistor (M3), a second diode-connected N-channel transistor (M4), and a first level shifting circuit (17) are coupled in series between ground and a gate of the N-channel transistor, and a current source (7) is coupled between the first supply voltage and the gate of the first N-channel transistor.

Abstract: In an operational amplifier, a differential amplifying circuit is configured to amplify an input voltage inputted from the input terminal. An outputting transistor is connected to the output terminal. A driving transistor is connected to the differential amplifying circuit and the outputting transistor. The driving transistor turns on according to a control signal supplied from the differential amplifying circuit to the driving circuit. The driving transistor is also configured to drive the outputting transistor according to the control signal. A control signal reducing circuit, when a voltage is applied on the driving transistor through the outputting transistor, is configured to reduce the control signal within a range that the driving transistor is kept to on state. The voltage applied on the driving transistor exceeds a predetermined threshold voltage.

Abstract: The invention provides a method for amplification of analog push-pull signals (101a, 101b) by means of a push-pull amplifier output stage (100) which has a first output stage transistor (102a) and a second output stage transistor (102b), with first and second analog push-pull signals (101a, 101b) being applied to the first and second output stage transistors (102a, 102b) and to first and second control transistors (103a, 103b), by which means first and second control currents (104a, 104b) are controlled, furthermore with the second control current (104b) which is controlled by the second control transistor (103b) being mirrored by means of a current mirror device (105) into a mirrored second control current (104c), with the first control current (104a) being compared with a first reference current, with the mirrored second control current (104c) being compared with a second reference current, with reference voltage levels (107a, 107b) which are produced by the comparison processes being logically linked in an

Abstract: An amplifier has a p-type and an n-type difference transistor pairs providing respective outputs, and is adapted to provide the outputs of the pairs in an integrated form. When the level of the input signal is below a predetermined level, only the p-type difference transistor pair is activated, and when the level of the input signal is higher than the predetermined level, the n-type difference transistor pair is also activated. The amplifier has an expanded dynamic range with a suppressed noise level.

Abstract: The present invention relates to an amplifying circuit that can change load drivability responding to load conditions, and reduce power consumption. The amplifying circuit according to the present invention comprises an amplifying means that amplifies input signals a first time to generate a first and a second amplified signals through a first and a second transistors, and further amplifies the first and second amplified signals once again through a third and a fourth transistors, for final outputs; a detecting means for detecting the first and second amplified signals from the amplifying means and generating a first and a second detection signals; and a load drivability control means that is controlled by the first and second detection signals from the detecting means to change load drivability of the amplifying means.

Abstract: A differential line driver includes first, second, third and fourth cascode transistors connected in parallel, wherein drains of the first and third transistors are connected to a negative output of the differential line driver, and wherein drains of the second and fourth transistors are connected to a positive output of the differential line driver. First, second, third and fourth switching transistors are connected in series with corresponding first, second, third and fourth cascode transistors and driven by a data signal. First and second compound transistors inputting a class AB operation signal at their gates, wherein the first compound transistor is connected to sources of the first and second switching transistors, and wherein the second compound transistor is connected to sources of the third and fourth switching transistors.

Abstract: A class-A amplifier circuit having output voltage varied according to input voltage includes a class-A amplifier, a voltage pull-up switch level circuit, an output voltage of the class-A amplifier, a voltage pull-up switch circuit, a voltage pull-down switch level circuit, a voltage pull-down circuit, a voltage pull-down switch circuit, and a bias circuit. The circuit utilizes the voltage pull-up and the voltage pull-down circuits to enable an output voltage of the class-A amplifier to rapidly and precisely change as an input voltage changes. Moreover, the circuit utilizes the voltage pull-up and the voltage pull-down switch circuits to prevent an overshooting from occurring.

Abstract: An AB class buffer amplifier controls quiescent current. The AB class buffer amplifier includes a first current controller and a second current controller. The first current controller sources current to an output node in response to a first logic level of a first signal, and buffers and outputs an input voltage to the output node in response to a second logic level of the first signal. The second current controller sinks the current from the output node in response to a second logic level of a second signal, and buffers and outputs the input voltage to the output node in response to a first logic level of the second signal. The first and second signals are generated at the first logic levels if the input voltage is higher than the output voltage and at the second logic level if the input voltage is lower than the output voltage.

Abstract: A three-stage transimpedance amplifier, where the first stage is a shunt-shunt feedback amplifier, the second stage is a simple voltage amplifier, and the third stage is a shunt-shunt feedback amplifier. The third stage comprises a pMOSFET serially connected with a nMOSFET, where their gates are connected together and to the output port of the second stage, and comprises a feedback pMOSFET or resistor to provide negative feedback from the drains of the pMOSFET and nMOSFET to the output port of the second stage.

Abstract: An output stage provides increased current sourcing capability through a technique of local positive feedback. Current through a transistor MP2 is mirrored by the output current source IOUT that is desired to be increased. Without positive feedback, the gate of MN2 would be fixed by MP1 and MN1, and when input voltage VIN decreases by an incremental voltage &Dgr;V, the resulting current increase would distribute an increased voltage not only across MP2's VGS but also in the VGS of another transistor MN2; therefore, undesirably, not all of the &Dgr;V voltage change is mirrored in IOUT. However, if positive feedback such as MP5 is provided, the feedback dynamically increases the voltage at the gate of MN2. The increased voltage of MN2's gate essentially provides more voltage “headroom” for MP2 and MN2, and allows current through MP2 to increase with any voltage decrease in VIN.

Abstract: A method and circuits of a high isolation and high-speed buffer amplifier capable to handle frequencies in the GHz range have been achieved. The output to input isolation is primary dependent on the gate-source capacitance of the active buffer transistor. Having two or more in series and by reducing the impedance between them a high isolation can be achieved. The input signals are split in several signal paths and are amplified in the push-pull mode using source follower amplifiers. Then the amplified signals are being combined again. The amplified output current is mirrored applying a multiplication factor. Said method and technology can be used for buffer amplifiers having differential input and differential output or having single input and single output or having differential input and single output. A high reversed biased (output to input) isolation and a reduced quiescent current have been achieved.

Abstract: A method and apparatus is provided for use in power amplifiers for reducing the peak voltage that transistors are subjected to. A power amplifier is provided with first and second switching devices and an inductor connected between the switching devices. The switching devices are driven such that the switching devices are turned on and off during the same time intervals.

Abstract: A power amplifier has a pair of FETs of opposite kinds connected together to form a source/drain circuit connected with an output. A second pair of high speed transistors is connected to the input and forms a collector/emitter circuit connected to the gates of the FETs. Capacitors are connected across the second pair of transistors and the pair of FETs respectively. Opposing current sources connect with the bases of the second pair of transistors via a resistor divider.

Abstract: The invention provides a method for amplification of analog push-pull signals (101a, 101b) by means of a push-pull amplifier output stage (100) which has a first output stage transistor (102a) and a second output stage transistor (102b), with first and second analog push-pull signals (101a, 101b) being applied to the first and second output stage transistors (102a, 102b) and to first and second control transistors (103a, 103b), by which means first and second control currents (104a, 104b) are controlled, furthermore with the second control current (104b) which is controlled by the second control transistor (103b) being mirrored by means of a current mirror device (105) into a mirrored second control current (104c), with the first control current (104a) being compared with a first reference current, with the mirrored second control current (104c) being compared with a second reference current, with reference voltage levels (107a, 107b) which are produced by the comparison processes being logically linked in an

Abstract: An amplifier comprising: 1) a class-AB push-pull stage comprising a first P-channel output transistor and a first N-channel output transistor for driving an output load; and 2) a class-B current booster stage coupled in parallel with the class-AB push-pull stage comprising a second P-channel output transistor and a second N-channel output transistor for driving the output load. The small class-AB transistors have a minimum quiescent transconductance. The class-B current booster transistors are inactive in the quiescent state, but deliver large currents for output voltages approaching the power supply rails.

Abstract: A class AB amplifier circuit includes a complementary output stage and a biasing circuit for biasing the output stage. The complementary output stage includes a P-type MOS transistor and an N-type MOS transistor, and the biasing circuit includes a bipolar transistor. The emitter and collector of the bipolar transistor are respectively connected to the gates of the P-type and N-type MOS transistors. The bipolar transistor is biased for controlling a bias voltage between the respective gates of the P-type and N-type MOS transistors.

Abstract: An amplifier has a p-type and an n-type difference transistor pairs providing respective outputs, and is adapted to provide the outputs of the pairs in an integrated form. When the level of the input signal is below a predetermined level, only the p-type difference transistor pair is activated, and when the level of the input signal is higher than the predetermined level, the n-type difference transistor pair is also activated. The amplifier has an expanded dynamic range with a suppressed noise level.

Abstract: A three-stage transimpedance amplifier, where the first stage is a shunt-shunt feedback amplifier, the second stage is a simple voltage amplifier, and the third stage is a shunt-shunt feedback amplifier. The third stage comprises a pMOSFET serially connected with a nMOSFET, where their gates are connected together and to the output port of the second stage, and comprises a feedback pMOSFET or resistor to provide negative feedback from the drains of the pMOSFET and nMOSFET to the output port of the second stage.

Abstract: A transimpedance amplifier having a first input port to connect to a signal source having an output impedance, and a second input port loaded by an impedance matched to the output impedance of the signal source, the amplifier comprising three stage pairs. The first stage pair comprises two inverting amplifiers, each employing negative feedback. The second stage pair comprises two inverting amplifiers with cross-coupled negative feedback. The third stage pair is similar in structure to the first stage pair. The inverter amplifiers in the third stage pair provide the differential voltage.

Abstract: A method and circuits of a high isolation and high-speed buffer amplifier capable to handle frequencies in the GHz range have been achieved. The output to input isolation is primary dependent on the gate-source capacitance of the active buffer transistor. Having two or more in series and by reducing the impedance between them a high isolation can be achieved. The input signals are split in several signal paths and are amplified in the push-pull mode using source follower amplifiers. Then the amplified signals are being combined again. The amplified output current is mirrored applying a multiplication factor. Said method and technology can be used for buffer amplifiers having differential input and differential output or having single input and single output or having differential input and single output. A high reversed biased (output to input) isolation and a reduced quiescent current have been achieved.

Abstract: A set of class AB output stages are cascaded to provide a class AB device circuit which utilizes relatively small transistors, low power, and virtually eliminates crossover distortion. The input may be powered by a voltage or a current source.

Abstract: A differential line driver includes first, second, third and fourth cascode transistors connected in parallel, wherein drains of the first and third transistors are connected to a negative output of the differential line driver, and wherein drains of the second and fourth transistors are connected to a positive output of the differential line driver. First, second, third and fourth switching transistors are connected in series with corresponding first, second, third and fourth cascode transistors and driven by a data signal. First and second compound transistors inputting a class AB operation signal at their gates, wherein the first compound transistor is connected to sources of the first and second switching transistors, and wherein the second compound transistor is connected to sources of the third and fourth switching transistors.

Abstract: A voltage amplifier circuit inhibits excessive output phase shifts from a voltage amplifier that could result in oscillation, while still providing for rail-to-rail outputs. A first output stage that includes a blocking impedance dominates the output for low output values, while a second output stage that excludes the blocking impedance dominates for higher output voltages up to rail-to-rail. The output stages are preferably implemented with CMOS transistors, with the relative sizes of the transistors and the resistance of the blocking resistor selected to enable both phase shift inhibition and rail-to-rail outputs. The first output stage provides more AC feedback, while the second output stage provides more DC feedback for high output voltages.

Abstract: A differential amplifier includes an input stage (13) and an output stage (100) including an output transistor (M11) having a source coupled to a supply voltage (VDD), a gate coupled to a terminal (14) of the input stage, and a drain coupled to an output conductor (22). A recovery circuit (1A) is coupled between the supply voltage and the gate of the output transistor for limiting the voltage on the gate of the output transistor in response to the output voltage be within a predetermined range of the supply voltage and includes a recovery transistor (M4) with a source coupled to the output conductor and a drain coupled to the gate of the output transistor and a common-gate amplifier (29A) having a built-in offset a first input coupled to the output conductor, a second input coupled to the supply voltage, and an output coupled to the gate of the recovery transistor.

Abstract: A source follower circuit receives, at its gate, an input signal and outputs an input current that is in accordance with the input signal. A current transfer circuit maintains constant the sum of the input current and an output current that is to be applied to a first node. A push-pull circuit includes a first transistor that directly receives, at its gate, the input signal and a second transistor having its gate connected to the first node. The voltage gain of the source follower circuit that receives the input signal is equal to or less than 1, so that the gain of the gate voltage of the second transistor to the input signal can be reduced. The difference in voltage gain between the first and second transistors can be reduced, so that it is possible to easily design a push-pull amplifier with a stable operation.

Abstract: An operational amplifier has a bias circuit, a differential amplifier, an output stage, and a feed forward circuit. The bias circuit provides a reference. The differential amplifier is coupled to a pair of input terminals and provides a differential output based on the first and second inputs. The output stage responds to the reference and to the differential output so as to supply a current to an output terminal. The feed forward circuit responds to the differential output in order to increase and decrease current to the output terminal. As a result, the feed forward circuit extends the dynamic range of the operational amplifier.

Abstract: A differential amplifier includes an input stage (13) and an output stage (100) including an output transistor (M11) having a source coupled to a supply voltage (VDD), a gate coupled to a terminal (14) of the input stage, and a drain coupled to an output conductor (22). A recovery circuit (1A) is coupled between the supply voltage and the gate of the output transistor for limiting the voltage on the gate of the output transistor in response to the output voltage be within a predetermined range of the supply voltage and includes a recovery transistor (M4) with a source coupled to the output conductor and a drain coupled to the gate of the output transistor and a common-gate amplifier (29A) having a built-in offset a first input coupled to the output conductor, a second input coupled to the supply voltage, and an output coupled to the gate of the recovery transistor.

Abstract: A set of class AB output stages are cascaded to provide a class AB device circuit which utilizes relatively small transistors, low power, and virtually eliminates crossover distortion. The input may be powered by a voltage or a current source.

Abstract: A multi-stage differential amplifier with rail-to-rail input may utilize an output stage including first and second low-voltage rated transistors and first and second high-voltage transistors. The first low-voltage rated transistor and the first high-voltage rated transistor may be connected in series, and the second low-voltage rated transistor and the second high-voltage rated transistor may be connected in parallel. The low-voltage rated transistors are biased by signals provided by the input stage. In this way, the input stage controls the biasing of the low-voltage rated transistors in the output stage, thereby increasing the overall gain and speed of the amplifier system.

Abstract: An AB class buffer amplifier controls quiescent current. The AB class buffer amplifier includes a first current controller and a second current controller. The first current controller sources current to an output node in response to a first logic level of a first signal, and buffers and outputs an input voltage to the output node in response to a second logic level of the first signal. The second current controller sinks the current from the output node in response to a second logic level of a second signal, and buffers and outputs the input voltage to the output node in response to a first logic level of the second signal. The first and second signals are generated at the first logic levels if the input voltage is higher than the output voltage and at the second logic level if the input voltage is lower than the output voltage.

Abstract: The disclosure describes a phase-splitter/level shifter comprising a first MOS transistor has a drain coupled to the first output node and a source coupled to a feedback node through a source resistor and a gate. A second MOS transistor has a drain coupled to a second output node and a source coupled to the feedback node through a source resistor and a gate. A first operational amplifier has a non-inverting input coupled to a single-ended input node, and an inverting input coupled to a second reference current source, an output coupled to the gate of the first MOS transistor. A second operational amplifier has a non-inverting input coupled to a single-ended input node, an inverting input coupled to a first reference current source, and an output coupled to the gate of the second MOS transistor. A variable resistor is coupled between the source of the first and second MOS transistor.

Abstract: The present invention provides an high beta, high speed operational amplifier output stage (100). The advantages of the operational amplifier output stage over conventional methods disclosed is up to &bgr;2 rather than a single beta. The present invention achieves this using an pre-driver sub-stage (122) having a plurality of translinear loops so that there is no net signal loss to the final sub-stage (123). The output of the disclosed operational amplifier output stage takes the form: &dgr;Io≈&bgr;n*&bgr;p*&dgr;Iin. When used with a localized feedback circuitry, speed performance is increased and bandwidth is extended.

Abstract: A differential amplifier comprises first and second differential amplifier circuits. The first differential amplifier circuit includes a first N-type transistor and a second N-type transistor for constituting a differential pair, and operates based on a first input voltage VIN1. The second differential amplifier circuit includes a first P-type transistor and a second P-type transistor making up a differential pair, and operates based on a second input voltage VIN2. There is also provided a third P-type transistor operable based on a first signal S1 coming from the first differential amplifier circuit and a third N-type transistor operable based on a second signal S2 from the second differential amplifier circuit, wherein a voltage between these third P- and N-type transistors becomes an output voltage VOUT.

Abstract: A turn-around stage is provided that accepts the full current swing from an input stage while maintaining a low quiescent current. The circuitry provides Class AB operation with quiescent currents that are significantly less than the maximum signal current so that overall power consumption is significantly reduced. Also, the amount of noise and offset contributions of the circuit are reduced by reducing the transconductances associated with transistors included in the turn-around stage.

Abstract: An output stage for an operational amplifier includes a dynamically activated CMOS drive circuit that is arranged to improve the drive characteristics of the operational amplifier. The output stage includes bipolar transistors that are arranged to clamp the signal swing at an intermediary node in the operational amplifier. The bipolar transistors activate respective portions of the CMOS drive circuit based on the signal drive at the intermediary node. The CMOS driver circuit includes a p-type field effect transistor that sources additional current into the output signal when active, and an n-type field effect transistor that sinks additional current from the output terminal when active. The output stage may include additional circuitry to ensure that parasitic capacitances associated with the gates of the p-type field effect transistor and the n-type field effect transistors are discharged at appropriate times such that power consumption is reduced and high-speed operation is enhanced.