Having Particular Biasing Means Patents (Class 330/285)
  • Patent number: 11277097
    Abstract: A power amplification system includes a Power Amplifier (PA) for amplifying an input RF signal. An adaptive bias circuit is configured to adaptively set a bias of the PA. The adaptive biasing circuit includes a gain expansion circuit, a gain compression circuit and a biasing circuit. The gain expansion circuit derives a gain-expansion control signal from the input RF signal. For a first sub-range of the input RF signal, the gain-expansion control signal has a larger dynamic range than the input RF signal. The gain compression circuit derives a gain-compression control signal from the input RF signal. For a second sub-range of the input RF signal having higher power levels than the first sub-range, the gain-compression control signal has a smaller dynamic range than the input RF signal. The biasing circuit sets the bias of the PA responsively to the gain-expansion control signal and the gain-compression control signal.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: March 15, 2022
    Assignee: MARVELL ASIA PTE LTD
    Inventors: Sai-Wang Tam, Alden C Wong, Ovidiu Carnu, Randy Tsang
  • Patent number: 11211703
    Abstract: A system for adjusting bias power provided to a radio-frequency amplifier to increase plurality of figures of merit based on sensed characteristics of the amplifier and/or characteristics of the input or output power.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: December 28, 2021
    Assignee: EPIRUS, INC.
    Inventors: Harry Bourne Marr, Jr., Denpol Kultran, Ryan Scott Ligon, Steven Deward Gray
  • Patent number: 11211955
    Abstract: Disclosed is a voltage protection circuit for preventing power amplifier burnout in an electronic device. The electronic device includes a power amplifier (PA) configured to amplify a transmission signal, a switch configured to set a path of a signal outputted from the PA, a bias control circuit configured to control the supply of a bias current driving the PA, and a voltage protection circuit configured to provide a main control signal for turning off the PA earlier than turning off the switch based on a battery voltage providing a driving power of the electronic device, and forward the main control signal to the bias control circuit, wherein, in response to receiving the main control signal instructing to turn off the PA from the voltage protection circuit, the bias control unit stops the supply of the bias current driving the PA.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: December 28, 2021
    Inventors: Hyunseok Choi, Jooseung Kim, Namjun Cho, Hyoseok Na
  • Patent number: 11196391
    Abstract: Embodiments of a temperature compensation circuit and a temperature compensated amplifier circuit are disclosed. In an embodiment, a temperature compensation circuit includes a bias reference circuit having serially connected transistor devices and a driver transistor device connected to the bias reference circuit. At least one of the serially connected transistor devices includes a resistor connected between two terminals of the at least one of the serially connected transistor devices. The driver transistor device is configured to generate a drive current based on a resistance value of the resistor.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: December 7, 2021
    Assignee: NXP USA, Inc.
    Inventors: Joseph Staudinger, Yu You, Donald Vernon Hayes
  • Patent number: 11184182
    Abstract: The invention relates to powering one or more devices, in particular in the context of Power-over-Ethernet (PoE). In an embodiment of the invention, it is proposed to equip each node (11) with a PD interface (22) that can signal multiples of the standard defined unity load (25 k? with tolerances) during the detection process and increase the load during a sequence of detection attempts. In that way, several nodes (11) can share one PSE outlet and determine the number of neighboring loads (11). At the same time, each node (11) will offer full functionality during “normal” stand-alone wiring. This powering concept can be combined with full or limited data communication capabilities.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: November 23, 2021
    Assignee: SIGNIFY HOLDING B.V.
    Inventors: Harald Josef Günther Radermacher, Matthias Wendt, Dave Willem Van Goor, Lennart Yseboodt
  • Patent number: 11133786
    Abstract: Disclosed are a radiofrequency power amplifier module having high linearity and power-added efficiency and an implementation method. The radiofrequency power amplifier module comprises a bias circuit, a linearization circuit, and a power amplifier circuit. The power amplifier circuit is connected to the linearization circuit. The linearization circuit is connected to the bias circuit. The bias circuit is connected to the power amplifier circuit. In the present invention, the linearization circuit is utilized to capture a radiofrequency signal inputted from a radiofrequency signal input end of the power amplifier circuit, the captured radiofrequency signal is fed back to the bias circuit, a corresponding bias current is generated by the bias circuit on the basis of the radiofrequency signal fed back, and the bias current is inputted to the power amplifier circuit, thus increasing the linearity and power-added efficiency of an output signal of the radiofrequency power amplifier.
    Type: Grant
    Filed: July 1, 2018
    Date of Patent: September 28, 2021
    Assignee: VANCHIP (TIANJIN) TECHNOLOGY CO., LTD.
    Inventors: Gang Chen, Yunfang Bai
  • Patent number: 11128265
    Abstract: A communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT) are provided. The disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. An amplifier includes a first transistor for amplifying the fundamental signal applied to a gate terminal, and a second transistor having a source terminal electrically connected to the drain terminal of the first transistor and a drain terminal electrically connected to a bias voltage. The current flowing through the second transistor may be determined based on the current flowing in the drain terminal of the first transistor.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: September 21, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youngchang Yoon, Kyuhwan An, Jihoon Kim, Sangho Lee
  • Patent number: 11095258
    Abstract: A second main electrode of a first transistor is connected to a first main electrode of a sixth transistor, a second main electrode of the sixth transistor is connected to a first main electrode of a fifth transistor at a first node, a second main electrode of the fifth transistor is connected to a second main electrode of a second transistor, a control electrode of the fifth transistor is connected to the second main electrode of the fifth transistor, a second main electrode of a third transistor is connected to a first main electrode of a fourth transistor at a second node, and a control electrode of the fourth transistor is connected to the control electrode of the fifth transistor. A gain control amplifier controls a voltage supplied to a control electrode of the sixth transistor such that the first node and the second node are equal in voltage.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: August 17, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Takayuki Nakai
  • Patent number: 11057003
    Abstract: The present disclosure relates to devices and methods for detecting and preventing occurrence of a saturation state in a power amplifier. A power amplifier module can include a power amplifier including a cascode transistor pair. The cascode transistor pair can include a first transistor and a second transistor. The power amplifier module can include a current comparator configured to compare a first base current of the first transistor and a second base current of the second transistor to obtain a comparison value. The power amplifier module can include a saturation controller configured to supply a reference signal to an impedance matching network based on the comparison value. The impedance matching network can be configured to modify a load impedance of a load line in electrical communication with the power amplifier based at least in part on the reference signal.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: July 6, 2021
    Assignee: Skyworks Solutions, Inc.
    Inventors: David Steven Ripley, Philip John Lehtola
  • Patent number: 11043922
    Abstract: An amplification circuit includes: a power supply terminal that is connected to a power supply; a first transistor that has a first source terminal, a first drain terminal, and a first gate terminal to which a high-frequency signal is inputted; a second transistor that has a second source terminal that is connected to the first drain terminal, a second drain terminal that outputs a high frequency signal, and a second gate terminal that is grounded; a capacitor that is serially arranged on a second path that connects the second gate terminal and the power supply terminal; and a switch that is serially arranged on a first path, which connects the second drain terminal and the power supply terminal, or the second path. The second drain terminal and the second gate terminal are connected to each other via the switch and the capacitor.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: June 22, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Daisuke Watanabe
  • Patent number: 11038469
    Abstract: A power amplification module includes a first transistor which amplifies and outputs a radio frequency signal input to its base; a current source which outputs a control current; a second transistor connected to an output of the current source, a first current from the control current input to its collector, a control voltage generation circuit connected to the output and which generates a control voltage according to a second current from the control current; a first FET, the drain being supplied with a supply voltage, the source being connected to the base of the first transistor, and the gate being supplied with the control voltage; and a second FET, the drain being supplied with the supply voltage, the source being connected to the base of the second transistor, and the gate being supplied with the control voltage.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: June 15, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kenichi Shimamoto, Satoshi Tanaka, Tadashi Matsuoka
  • Patent number: 11038466
    Abstract: A wideband envelope modulator comprises a direct current (DC)-to-DC switching converter connected in series with a linear amplitude modulator (LAM). The DC-DC switching converter includes a pulse-width modulator that generates a PWM signal with modulated pulse widths representing a time varying magnitude of an input envelope signal or a pulse-density modulator that generates a PDM signal with a modulated pulse density representing the time varying magnitude of the input envelope signal, a field-effect transistor (FET) driver stage that generates a PWM or PDM drive signal, a high-power output switching stage that is driven by the PWM or PDM drive signal, and an output energy storage network including a low-pass filter (LPF) of order greater than two that filters a switching voltage produced at an output switching node of the high-power output switching stage.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: June 15, 2021
    Assignee: Eridan Communications, Inc.
    Inventor: Waclaw Godycki
  • Patent number: 11031915
    Abstract: Disclosed are methods for biasing amplifiers and for manufacturing bias circuits bias for biasing amplifiers. A power amplifier bias circuit can include an emitter follower device and an emitter follower mirror device coupled to form a mirror configuration. The emitter follower device can be configured to provide a bias signal for a power amplifier at an output port. The power amplifier bias circuit can include a reference device configured to mirror an amplifying transistor of an amplifying device of the power amplifier. The emitter follower mirror device can be configured to provide a mirror bias signal to the reference device. A node between the emitter follower device and the emitter follower mirror device can have a voltage of approximately twice a base-emitter voltage (2Vbe) of the amplifying transistor.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: June 8, 2021
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventor: Aleksey A. Lyalin
  • Patent number: 11025216
    Abstract: In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: June 1, 2021
    Assignee: Texas Instruments Incorporated
    Inventor: Sudheer Prasad
  • Patent number: 11012040
    Abstract: Disclosed is an apparatus including a radio frequency amplifying circuit, a power supply circuit, and a bias generating circuit. The power supply circuit includes: a first power supply terminal coupled to a first ground terminal via a first capacitor and coupled to/decoupled from the radio frequency amplifying circuit through a first switch; and a second power supply terminal coupled to a second ground terminal via a second capacitor and coupled to/decoupled from the radio frequency amplifying circuit through a second switch, wherein the first capacitor and second capacitor are coupled to/decoupled from the radio frequency amplifying circuit through the first switch and second switch respectively, the supply voltages outputted from the two power supply terminals are different, and the two switches are not concurrently turned on. The radio frequency amplifying circuit operates according to a bias voltage provided by the bias generating circuit and one of the two supply voltages.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: May 18, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Yang-Tang Tsai, Po-Chih Wang, Ka-Un Chan
  • Patent number: 10979002
    Abstract: Certain aspects of the present disclosure provide methods and apparatus for current-limiting protection of an amplifier, such as a power amplifier in a radio frequency (RF) front-end. One example current-limiting circuit generally includes a node coupled to a current source, a plurality of current-sinking devices coupled to the node, one or more switches coupled between the node and at least one of the plurality of current-sinking devices, and a bias circuit having an input coupled to the node and an output for coupling to an input of the amplifier.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: April 13, 2021
    Assignee: QUALCOMM INCORPORATED
    Inventors: Jing-Hwa Chen, Jisun Ryu, Yan Kit Gary Hau, Yanjie Sun, Xinwei Wang, Xiangdong Zhang
  • Patent number: 10958223
    Abstract: There has been a problem that linearity is degraded in the conventional amplifier when the idle current is reduced in order to lower the power consumption. An amplifier of the present invention includes: a bias circuit to cause a bias current to flow; an amplifying element to amplify a signal by causing an output current corresponding to the bias current to flow; a bias current subtracting circuit to detect the signal and subtract, from the bias current, a current based on an amplitude of the signal detected; and a bias current adding circuit having an operation starting point higher than an operation starting point of the bias current subtracting circuit, and to detect the signal and add, to the bias current, a current based on an amplitude of the signal detected.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: March 23, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Tatsuya Hagiwara, Akihito Hirai, Eiji Taniguchi
  • Patent number: 10951173
    Abstract: Circuits, devices and methods related to amplification with active gain bypass. In some embodiments, an amplifier can include a first amplification path implemented to amplify a signal, and having a cascode arrangement of a first input transistor and a cascode transistor to provide a first gain for the signal when in a first mode. The amplifier can further include a second amplification path implemented to provide a second gain for the signal while bypassing at least a portion of the first amplification path when in a second mode. The second amplification path can include a cascode arrangement of a second input transistor and the cascode transistor shared with the first amplification path. The amplifier can further include a switch configured to allow routing of the signal through the first amplification path in the first mode or the second amplification path in the second mode.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: March 16, 2021
    Assignee: Skyworks Solutions, Inc.
    Inventors: David Richard Pehlke, John Chi-Shuen Leung
  • Patent number: 10944363
    Abstract: The present disclosure relates to a power amplifier circuit. The power amplifier circuit includes a voltage-controlled current source and a current mirror. The voltage-controlled current source is configured to receive a first voltage and to generate a first current. The current mirror is connected to the voltage-controlled current source and to generate a second current in response to the first current. The second current continuously changes from 0 mA to about 120 mA as the first voltage continuously changes from 0 V to about 1 V.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: March 9, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Jaw-Ming Ding
  • Patent number: 10903794
    Abstract: A power amplifier device includes a bias circuit to generate a startup current, which is based on an internal voltage and a startup voltage, during a startup time prior to a steady driving time point, and to generate a bias current, which is based on the internal voltage, after the steady driving time point, and a startup circuit to supply the bias circuit with the startup voltage during the startup time.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: January 26, 2021
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jong Ok Ha, Jeong Hoon Kim, Byeong Hak Jo, Shinichi Iizuka
  • Patent number: 10903797
    Abstract: A bias circuit for supplying a bias current to an RF power amplifier by using a field-effect transistor (FET) that is controlled by a logic control signal, such as a CMOS logic control signal, for turning on or turning off the bias current supplied to the RF power amplifier, wherein the bias current will be supplied to the RF power amplifier when the FET is on, and the bias current will not be supplied to the RF power amplifier when the FET is off.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: January 26, 2021
    Assignee: Rafael Microelectronics, Inc.
    Inventors: Chih-Wen Wu, Szu-Yao Chu
  • Patent number: 10892714
    Abstract: A power amplifier circuit includes a first transistor that amplifies an RF signal; a bias current source that supplies a bias current to a second terminal of the first transistor through a first current path; and an adjustment circuit that adjusts the bias current in accordance with a variable power-supply voltage supplied from a power-supply terminal. The adjustment circuit includes first to third resistors, and an adjustment transistor including a first terminal connected to the power-supply terminal through the first resistor, a second terminal connected to the bias current source through the second resistor, and a third terminal connected to the first current path through the third resistor. When the variable power-supply voltage is not less than a first voltage and not greater than a third voltage, the adjustment circuit increases a current that flows to the power-supply terminal through a second current path as the variable power-supply voltage decreases.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: January 12, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kenichi Shimamoto, Hisanori Namie
  • Patent number: 10873296
    Abstract: An amplifier device comprises an amplifying unit and a bias module. The amplifying unit has a first end coupled to a voltage source configured to receive a source voltage, a second end configured to receive an input signal, and a third end coupled to a first reference potential terminal configured to receive a first reference potential. The first end of the amplifying unit is configured to output an output signal amplified by the amplifying unit. The bias module is coupled to the second end of the amplifying unit, and configured to receive a voltage signal to provide a bias current to the amplifying unit. The voltage signal is a variable voltage. A supply current flowing into the amplifying unit and is adjusted in accordance with the voltage signal to stay within a predetermined range.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: December 22, 2020
    Assignee: RichWave Technology Corp.
    Inventors: Chih-Sheng Chen, Tien-Yun Peng, Hung-Chia Lo
  • Patent number: 10855235
    Abstract: A power amplifier circuit amplifies a radio-frequency signal in a transmit frequency band. The power amplifier circuit includes an amplifier, a bias circuit, and an impedance circuit. The amplifier amplifies power of a radio-frequency signal and outputs an amplified signal. The impedance circuit is connected between a signal input terminal of the amplifier and a bias-current output terminal of the bias circuit and has frequency characteristics in which attenuation is obtained in the transmit frequency band. The impedance circuit includes first and second impedance circuits. The first impedance circuit is connected to the signal input terminal. The second impedance circuit is connected between the first impedance circuit and the bias-current output terminal.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: December 1, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takayuki Tsutsui, Satoshi Tanaka, Yasuhisa Yamamoto
  • Patent number: 10855227
    Abstract: A distortion compensation circuit includes an amplifier circuit, a bias circuit, a wiring, and a capacitive element. The bias circuit applies a bias voltage to the amplifier circuit. The wiring connects the amplifier circuit and the bias circuit. The capacitive element is connected to the wiring to cancel at least part of parasitic inductance produced in the wiring. The amplifier circuit includes an input terminal, an amplifier, a first capacitor, a connection node, and first and second resistors. An input signal is inputted into the input terminal. The amplifier amplifies the input signal. The first capacitor is disposed on a path connecting the input terminal and the amplifier. The connection node is disposed between the bias circuit and the amplifier. The first resistor is disposed on a path connecting the input terminal and the connection node. The second resistor is connected between the amplifier and the connection node.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: December 1, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Tsuyoshi Takagi
  • Patent number: 10833636
    Abstract: A method for improving the linearity of a radio frequency power amplifier, a compensation circuit (307) for implementing the method, and a communications terminal with the compensation circuit (307). In the method, a compensation circuit (307) is connected between a base (a3) and a collector (b3) of a transistor of a common emitter amplifier (306), in order to neutralize the impact of a variation in capacitance between the base (a3) and the collector (b3) of the transistor (306) according to a radio frequency signal. No additional direct-current power consumption is needed, and degradation in performance of other radio frequency power amplifiers can be avoided. The corresponding compensation circuit (307) can be easily integrated with a main amplification circuit, without affecting other performance of the main amplification circuit, and provides high adjustability.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: November 10, 2020
    Assignee: SHANGHAI VANCHIP TECHNOLOGIES CO., LTD.
    Inventor: Yunfang Bai
  • Patent number: 10761580
    Abstract: In one embodiment, a processor includes: a plurality of cores; a first storage to store parameter information for a voltage regulator to couple to the processor via a voltage regulator interface; and a power controller to control power consumption of the processor. The power controller may determine a performance state for one or more cores of the processor and include a hardware logic to generate a message for the voltage regulator based at least in part on the parameter information, where this message is to cause the voltage regulator to output a voltage to enable the one or more cores to operate at the performance state. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventors: Anupama Suryanarayanan, Avinash N. Ananthakrishnan, Chinmay Ashok, Jeremy J. Shrall
  • Patent number: 10763805
    Abstract: The present invention concerns a programmable power amplifier comprising: an amplifier core transistor circuit connected to an amplifier output node; a switch connected to the amplifier core transistor circuit, the switch being configured to switch on and off the amplifier core transistor circuit; and a feedback circuit of the amplifier core transistor circuit. The feedback circuit comprises a digital-to-analog converter and an operational amplifier having a first input node configured to receive a first reference signal; a second input node connected to the digital-to-analog converter; and an output node for outputting an operational amplifier output signal and connected to the amplifier core transistor circuit for controlling the amount of current flowing in the amplifier core transistor circuit.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: September 1, 2020
    Assignee: EM Microelectronic-Marin S.A.
    Inventors: Robert R. Rotzoll, Kevin Scott Buescher
  • Patent number: 10763792
    Abstract: A multiple-stage amplifier includes a driver stage die and a final stage die. The driver stage die includes a first type of semiconductor substrate (e.g., a silicon substrate), a first transistor, and an integrated portion of an interstage impedance matching circuit. A control terminal of the first transistor is electrically coupled to an RF signal input terminal of the driver stage die, and the integrated portion of the interstage impedance matching circuit is electrically coupled between a current-carrying terminal of the first transistor and an RF signal output terminal of the driver stage die. The second die includes a III-V semiconductor substrate (e.g., a GaN substrate) and a second transistor. A connection, which is a non-integrated portion of the interstage impedance matching circuit, is electrically coupled between the RF signal output terminal of the driver stage die and an RF signal input terminal of the final stage die.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: September 1, 2020
    Assignee: NXP USA, Inc.
    Inventors: Joseph Gerard Schultz, Enver Krvavac, Olivier Lembeye, Cedric Cassan, Kevin Kim, Jeffrey Kevin Jones
  • Patent number: 10756675
    Abstract: A broadband power amplifier circuit is provided. The broadband power amplifier circuit includes an amplifier circuit configured to amplify a radio frequency (RF) signal to an output power based on a bias voltage and a supply voltage. Given that the output power of the RF signal may rise and fall from time to time, the broadband power amplifier circuit is configured to opportunistically increase or decrease the bias voltage in a defined future time (e.g., a future time slot or a future symbol duration) based on the output power in the defined future time. When necessary, the broadband power amplifier may be further configured to adjust the supply voltage and/or attenuate the RF signal based on the output power. As such, it may be possible to maintain class-A operation mode for the amplifier circuit. As a result, the amplifier circuit may maintain linearity and avoid memory effect with improved efficiency.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: August 25, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Dirk Robert Walter Leipold, Baker Scott, Toshiaki Moriuchi, George Maxim
  • Patent number: 10750454
    Abstract: A high-frequency signal processing apparatus and a wireless communication apparatus can achieve a decrease in power consumption. For example, when an indicated power level to a high-frequency power amplifier is equal to or greater than a second reference value, envelope tracking is performed by causing a source voltage control circuit to control a high-speed DCDC converter using a detection result of an envelope detecting circuit and causing a bias control circuit to indicate a fixed bias value. The source voltage control circuit and the bias control circuit indicate a source voltage and a bias value decreasing in proportion to a decrease in the indicated power level when the indicated power level is in a range of the second reference value to the first reference value, and indicate a fixed source voltage and a fixed bias value when the indicated power level is less than the first reference value.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: August 18, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Tanaka, Kiichiro Takenaka, Takayuki Tsutsui, Taizo Yamawaki, Shun Imai
  • Patent number: 10734952
    Abstract: A power amplifier module includes a power amplifier circuit and a control IC. The power amplifier circuit includes a bipolar transistor that amplifies power of an RF signal and outputs an amplified signal. The control IC includes an FET, which serves as a bias circuit that supplies a bias signal to the bipolar transistor. The FET is operable at a threshold voltage lower than that of the bipolar transistor, thereby making it possible to decrease the operating voltage of the power amplifier module.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: August 4, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shota Ishihara, Yasuhisa Yamamoto
  • Patent number: 10700645
    Abstract: Power amplification system with adaptive bias control. In some embodiments a power amplification system includes a power amplifier including a radio-frequency (RF) input terminal for receiving an RF signal, an RF output terminal for providing an amplified RF signal, a supply voltage terminal for receiving a power amplifier supply voltage to power the power amplifier, and one or more bias terminals for receiving one or more bias signals. The power amplification system also includes a bias controller configured to provide the one or more bias signals to the one or more bias terminals, at least one of the one or more bias signals being based on the power amplifier supply voltage.
    Type: Grant
    Filed: July 7, 2018
    Date of Patent: June 30, 2020
    Assignee: Skyworks Solutions, Inc.
    Inventors: Matthew Lee Banowetz, Philip H. Thompson
  • Patent number: 10693421
    Abstract: A power amplification module includes a first transistor which amplifies and outputs a radio frequency signal input to its base; a current source which outputs a control current; a second transistor connected to an output of the current source, a first current from the control current input to its collector, a control voltage generation circuit connected to the output and which generates a control voltage according to a second current from the control current; a first FET, the drain being supplied with a supply voltage, the source being connected to the base of the first transistor, and the gate being supplied with the control voltage; and a second FET, the drain being supplied with the supply voltage, the source being connected to the base of the second transistor, and the gate being supplied with the control voltage.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: June 23, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kenichi Shimamoto, Satoshi Tanaka, Tadashi Matsuoka
  • Patent number: 10680557
    Abstract: An apparatus, comprising an input transformer; a first differential transistor pair configured to receive a first back gate bias voltage; a second differential transistor pair configured to receive a second back gate bias voltage; a cross-coupled neutralization cap comprising PMOS or NMOS transistors and configured to receive a third back gate bias voltage; and an output transformer. A method of fixing at least one back gate bias voltage to impart a desired capacitance to the transistors of at least one of the first differential transistor pair, the second differential transistor pair, or the neutralization cap. The apparatus and method may provide a power amplifier having improved linearity and efficiency.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: June 9, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Shafiullah Syed, Abdellatif Bellaouar, Chi Zhang
  • Patent number: 10673388
    Abstract: A bias circuit for a bipolar RF amplifier is described. The bias circuit includes a current source coupled to a bias network. The bias network supplies a base current to the transistors in the amplifier circuit of the bipolar RF amplifier. The bias circuit includes a buffer coupled to the bias network and to the bipolar RF amplifier. The buffer provides additional base current to the amplifier circuit of bipolar RF amplifier and sinks avalanche current generated by the amplifier circuit of the bipolar RF amplifier.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: June 2, 2020
    Assignee: NXP B.V.
    Inventors: Mark Pieter Van Der Heijden, Gerben Willem De Jong, Xin Yang
  • Patent number: 10666211
    Abstract: A power amplifier circuit includes a bias circuit and an amplifier circuit. The bias circuit includes a first bias circuit to receive a reference voltage and an operation voltage and generate a first bias signal, a bias supply circuit to transmit the base bias signal to a base of a power amplifier, based on the first bias signal input from the first bias circuit, a switching control circuit to transmit a switching signal after a preset delay time based on a driving start signal, and a switching circuit connected between an output node of the first bias circuit and a ground, to operate in an ON state after the delay time in response to the switching signal to form a current path between the output node of the first bias circuit and the ground.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: May 26, 2020
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Bo Hyun Hwang, Dae Hee No, Jun Goo Won, Ki Joong Kim, Sung Hwan Park, Da Hye Park
  • Patent number: 10630247
    Abstract: A power amplifier apparatus, includes an envelope tracking (ET) current bias circuit configured to generate a first ET bias current by calculating a direct current DC, based on a reference voltage, and an ET current, based on an ET voltage, according to an envelope of an input signal; and a power amplifier circuit having a bipolar junction transistor supplied with the first ET bias current and a power voltage to amplify the input signal, wherein an average current of the first ET bias current is controlled to be substantially constant.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: April 21, 2020
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Byeong Hak Jo, Jong Ok Ha, Jeong Hoon Kim, Youn Suk Kim
  • Patent number: 10630251
    Abstract: A bias current circuit includes: an N-type MOSFET in which a gate terminal and a drain terminal are connected to a current source, and N-type MOSFETs in which respective drain terminals are connected to respective bias current output terminals and source terminals are grounded. The bias current circuit further includes: an N-type MOSFET in which one terminal type, either a drain terminal or a source terminal, is connected to the gate terminal of the N-type MOSFET, and the other terminal type is connected to the gate terminals of the N-type MOSFETs, and an N-type MOSFET in which a drain terminal is connected to the gate terminals of the N-type MOSFETs and a source terminal is grounded. A control signal, that is LOW when the bias current is supplied and is HIGH when the bias current is not supplied, is input to the gate terminal of the N-type MOSFET, and an inverse signal of the control signal is input to the gate terminal of the N-type MOSFET.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: April 21, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Miki Kagano, Tomokazu Ogomi
  • Patent number: 10620802
    Abstract: The present disclosure relates to a system and method for algorithmic modeling interface (“AMI”) model development. Embodiments may include enabling a selection from a plurality of templates associated with an advanced equalization algorithm at a graphical user interface. Embodiments may further include receiving a selection of at least one of the plurality of templates at the graphical user interface and displaying a selected template at the graphical user interface. Embodiments may also include allowing a user to edit one or more parameters associated with the selected template at the graphical user interface and generating an algorithmic modeling interface (“AMI”) model based upon, at least in part, the selected template and the one or more parameters.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: April 14, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ambrish Kant Varma, Kumar Chidhambara Keshavan, Delong Cai, Kenneth R. Willis, Bradford C. Griffin, Xuegang Zeng
  • Patent number: 10608595
    Abstract: Power amplifiers, amplifier systems, and related methods are disclosed herein. In one example embodiment, the amplifier system includes a bias controller that automatically sets a bias voltage of a power amplifier device by monitoring a reference device that is in a scaled relationship with the power amplifier device, and integrally is formed with the power amplifier device on a same semiconductor die. The bias controller can compare a voltage at an input to the reference device to a reference voltage, and then adjust a voltage at a control input of the reference device to a stabilized voltage that induces the reference device to drive the voltage at the input to the reference device equal to the reference voltage. Finally, the bias controller can transform, based on the scaled relationship, the stabilized voltage into a bias voltage applied to a control input of the power amplifier device.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: March 31, 2020
    Assignee: NXP USA, Inc.
    Inventors: Elie Maalouf, Joseph Staudinger, Don Hayes
  • Patent number: 10566937
    Abstract: A low noise amplifier may include a post distortion cancellation block coupled to the low noise amplifier. The post distortion cancellation block may include a diode, and phase-shift logic. The phase-shift logic may be coupled in series with the diode.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: February 18, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Mohammad Sadegh Mehrjoo, Chuan Wang, Yanming Xiao, Li-chung Chang, Kevin Hsi Huai Wang
  • Patent number: 10566943
    Abstract: Apparatus and methods for biasing of power amplifiers are disclosed. In one embodiment, a mobile device includes a transceiver that generates a radio frequency signal and a power amplifier enable signal, a power amplifier that provides amplification to the radio frequency signal and that is biased by a bias signal, and a bias circuit that receives the power amplifier enable signal and generates the bias signal. The bias circuit includes a gain correction circuit that generates a correction current in response to activation of the power amplifier enable signal, and a primary biasing circuit that generates the bias signal based on the correction current and the power amplifier enable signal.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: February 18, 2020
    Assignee: Skyworks Solutions, Inc.
    Inventors: Ping Li, Paul T. DiCarlo
  • Patent number: 10554175
    Abstract: Apparatus and methods for power amplifiers that can operate under a wide range of supply voltages are disclosed herein. In certain implementations, a method of adjusting a parameter of a power amplifier is provided. The method includes detecting a value of a supply voltage provided to the power amplifier. The method further includes selecting a first value from a plurality of values for a first parameter of the power amplifier based on the detected value of the supply voltage. The method further includes adjusting the first parameter of the power amplifier to the first value.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: February 4, 2020
    Assignee: Skyworks Solutions, Inc.
    Inventors: Grant Darcy Poulin, Samir Hammadi, Edward John Wemyss Whittaker
  • Patent number: 10547303
    Abstract: Disclosed herein are switching or other active FET configurations that implement a main-auxiliary branch design. Such designs include a circuit assembly for performing a switching function that includes a branch including a main path in series with an auxiliary path. The circuit assembly also includes a first gate bias network connected to the main path. The circuit assembly also includes a second gate bias network connected to the auxiliary path, the second gate bias network configured to improve linearity of the switching function.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: January 28, 2020
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Hailing Wang, Dylan Charles Bartle, Hanching Fuh, Jerod F. Mason, David Scott Whitefield, Paul T. DiCarlo
  • Patent number: 10547300
    Abstract: A driving device is provided, which drives on/off a main switching element to which a diode is anti-parallel connected, wherein the driving device includes a detection unit configured to detect a voltage between a drain terminal and a source terminal; a determination unit configured to output a determination signal indicating whether a free wheeling current is flowing from the source terminal to the drain terminal based on a detected voltage detected by the detection unit; and a drive control unit configured to perform control such that the main switching element is set in an on-state on condition that an on command signal for turning on the main switching element is input and on condition that the determination signal indicating that the free wheeling current is flowing is output.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: January 28, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kunio Matsubara, Tsuyoshi Nagano
  • Patent number: 10547307
    Abstract: A bias circuit providing different bias voltages depending on a power mode through a simple circuit, and a power amplifier having the same are provided. The bias circuit and the power amplifier include a bias setting unit configured to vary a voltage level of a control signal controlling a bias voltage according to an operation of a first transistor being switched-off in a high power mode and switched-on in a low power mode. A bias supplying unit includes a bias supplying transistor switched based on the control signal, to supply the bias voltage having a voltage level according to a switching operation of the bias supplying transistor.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: January 28, 2020
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jun Goo Won, Youn Suk Kim, Yoshiyuki Tonami, Ki Joong Kim
  • Patent number: 10530301
    Abstract: A switching system is connected to the power amplifier of an RF system. The switching system can switch the DC supply voltage to the power amplifier while handling the high DC current and the nanosecond switching speed requirements that are mandatory for most RF systems. The embodiments can rapidly control DC voltages but not interfere with the optimized operation of the RF transistor. The embodiments provide a desired sharp turn-on leading edge for an RF pulse while eliminating the extremely long and undesirable ramp down that typically occurs beyond the desired RF pulse period.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: January 7, 2020
    Inventor: Rick Smeltzer
  • Patent number: 10511377
    Abstract: A solid state power amplifier uses a Doherty power amplifier that can be implemented as a monolithic microwave integrated circuit. By adjusting the DC bias of the amplifying stages in each branch of the Doherty amplifier, the output power, linearity, and DC power can be adjusted to provide a specified output, where the specification for the output can include the maintaining of desired DC power and linearity. The Doherty power amplifier can be used in a satellite payload or other application utilizing solid state power amplifiers, while providing the proper amount of RF output power and DC power. A single amplifier can have its bias levels adjusted for different output levels, helping to minimize the number of designs that are required for a given satellite payload, reducing the variety of parts in a satellite payload.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: December 17, 2019
    Assignee: Space Systems/Loral, LLC
    Inventors: Seyed Tabatabaei, Jim Sowers, Ghislain Turgeon
  • Patent number: 10511271
    Abstract: The method and system for converging a 5th-generation (5G) communication system for supporting higher data rates beyond a 4th-generation (4G) system with a technology for internet of things (IoT) are provided. The method includes intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. The system includes a power amplification device capable of minimizing the effect of envelope impedance. The power amplification device may be incorporated in a terminal and a base station.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: December 17, 2019
    Assignees: Samsung Electronics Co., Ltd., POSTECH Academy-Industry Foundation
    Inventors: Jihoon Kim, Bumman Kim, Kyunghoon Moon, Seokwon Lee, Daechul Jeong, Byungjoon Park, Juho Son