Having Particular Biasing Means Patents (Class 330/285)
  • Patent number: 10419042
    Abstract: A bias circuit provides additional bias current for power amplifiers during data bursts to compensate for the gain droop caused by a rise in the power amplifier temperature during the data burst. A bias circuit includes a difference amplifier and switches coupled to the difference amplifier. The switches operate the bias circuit in a first mode when a transmit data burst is detected and operate the bias circuit in a second mode after the bias circuit has operated in the first mode for a predetermined period of time. In the first mode, the bias circuit charges a storage capacitor and sets an output current to zero. In the second mode, the bias circuit outputs the output current that increases above the initial value of zero as the PA warms up, where the excursion of this increase of current is determined by a register. The switches disable the bias circuit when the transmit data burst ends.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: September 17, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventors: Edward John Wemyss Whittaker, Gordon Glen Rabjohn
  • Patent number: 10418949
    Abstract: A low noise amplifier and a radio frequency amplification method using the low noise amplifier are provided. The low noise amplifier includes gain stage circuits, the number of which is not less than that of RF signals to be amplified, and the gain stage circuit is configured to independently amplify the RF signal when being enabled; a plurality of amplification selection switching circuits, each of which is connected to one of the gain stage circuits and is configured to, according to the RF signal, control the gain stage circuit to be enabled or disabled; a plurality of driving circuits, each of which is connected to a respective one of the plurality of gain stage circuits and is configured to, when the gain stage circuit is enabled, receive at least one RF signal amplified by the gain stage circuit and output the amplified RF signal; and at least one load circuit.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: September 17, 2019
    Assignee: MAXSCEND MICROELECTRONICS COMPANY LIMITED
    Inventors: Wenyong Liu, Weijiang Wang
  • Patent number: 10396718
    Abstract: Provided is a bias control circuit that includes: a reference voltage circuit that generates a reference voltage; a resistor; a temperature dependent current generating circuit that generates a temperature dependent current, which changes depending on temperature, on the basis of the reference voltage and that supplies the temperature dependent current to one end of the resistor; a reference voltage buffer circuit that applies the reference voltage to the other end of the resistor; a constant current generating circuit that generates a constant current, which is for driving the reference voltage buffer circuit, on the basis of the reference voltage and that supplies the constant current to the other end of the resistor; and a bias generating circuit that generates a bias voltage or a bias current for a power amplification circuit on the basis of the voltage at the one end of the resistor.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: August 27, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoshiaki Harasawa, Fuminori Morisawa
  • Patent number: 10374557
    Abstract: A power amplifier apparatus, includes an envelope tracking (ET) current bias circuit configured to generate a first ET bias current by calculating a direct current DC, based on a reference voltage, and an ET current, based on an ET voltage, according to an envelope of an input signal; and a power amplifier circuit having a bipolar junction transistor supplied with the first ET bias current and a power voltage to amplify the input signal, wherein an average current of the first ET bias current is controlled to be substantially constant.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: August 6, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Byeong Hak Jo, Jong Ok Ha, Jeong Hoon Kim, Youn Suk Kim
  • Patent number: 10361667
    Abstract: Embodiments of the disclosure relate to a low noise amplifier (LNA) circuit. The LNA circuit includes an LNA configured to amplify a radio frequency (RF) input signal to generate an RF output signal. The LNA may be inherently nonlinear and, as a result, can create a harmonic distortion(s), such as second harmonic distortion (HD2), and/or an intermodulation distortion(s), such as second order intermodulation distortion (IMD2), in the RF output signal. In exemplary aspects discussed herein, a distortion amplifier(s) is provided in the LNA circuit to generate a distortion signal(s) to suppress the harmonic distortion(s) and/or the intermodulation distortion(s) in the RF output signal.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: July 23, 2019
    Assignee: Qorvo US, Inc.
    Inventors: George Maxim, Marcus Granger-Jones, Toshiaki Moriuchi, Dirk Robert Walter Leipold, Baker Scott
  • Patent number: 10312899
    Abstract: An apparatus includes an output transistor device configured to control an output voltage of an output node in response to a control signal and an input voltage. A current sensor is configured to sense an output current supplied from the output node. A feedback converter is configured to convert the sensed output current to a feedback signal that tracks the output voltage of the output node. The feedback converter is further configured to set a clamping threshold. A gate control circuit is configured to generate the control signal in response to the feedback signal. The gate control circuit is configured to clamp the output voltage of the output node via the control signal based on the clamping threshold.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: June 4, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Subrato Roy, Dattatreya Baragur Suryanarayana
  • Patent number: 10305430
    Abstract: A power control method and device for improving radio-frequency power amplifier (RF PA) switch spectrum, the method comprising the following steps: (a) detecting the gate voltage and drain voltage, or the gate voltage and supply voltage (vdd) of a pass element (105) to obtain the saturation information of the pass element (105); (b) if the saturation information indicates that the pass element (105) is about to leave the saturation working area, shunting the drain current of the pass element (105) to the error amplifier (102) to reduce the drain output voltage, thus reducing the variation of the output voltage, preventing the output voltage from quickly approaching the supply voltage (vdd), maintaining the saturation of the pass element (105), and improving the switch spectrum characteristics of RF PA.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: May 28, 2019
    Assignee: BEIJING VANCHIP TECHNOLOGIES CO., LTD.
    Inventor: Xida Liu
  • Patent number: 10291190
    Abstract: A power amplifier comprising a bipolar transistor connected in cascode with a field effect transistor (FET) such as a pseudomorphic high electron mobility transistor (PHEMT) device. The bipolar transistor has a common emitter and the FET a common gate. Advantageously, the bipolar transistor is a heterojunction bipolar transistor (HBT); and the HBT and the FET may be integrated on a single die. Illustrative materials for the HBT and FET are Gallium Nitride, Indium Phosphide, or Gallium Arsenide/Indium Gallium Phosphide.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: May 14, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventor: Thomas William Arell
  • Patent number: 10291191
    Abstract: The present disclosure relates to a radio frequency (RF) communications system including an RF power amplifier (PA), a bias circuit, and a protection circuit. The RF PA has an amplifier control terminal and a power supply terminal, the bias circuit is coupled to the amplifier control terminal, and the protection circuit is coupled between the bias circuit and the power supply terminal. Herein, the protection circuit is configured to reduce a current through the power supply terminal using the bias circuit via the amplifier control terminal when the RF PA is in an operation mode and a magnitude of a voltage at the power supply terminal exceeds a protection threshold. Further, the protection circuit is configured to be open and does not allow a current to pass through when the RF PA is in a standby mode.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: May 14, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Douglas Andrew Teeter, Nick Marcoux, Ming Ji
  • Patent number: 10284150
    Abstract: A power amplification module includes: a first transistor that amplifies a first radio frequency signal and outputs a second radio frequency signal; a second transistor that amplifies the second radio frequency signal and outputs a third radio frequency signal; and first and second bias circuits that supply first and second bias currents to bases of the first and second transistors. The first bias circuit includes a third transistor that outputs the first bias current from its emitter or source, a capacitor that is input with the first radio frequency signal and connected to the base of the first transistor, a first resistor connected between the emitter or source of the third transistor and the base of the first transistor, a second resistor connected between the capacitor and the emitter or source of the third transistor, and a third resistor connected between the capacitor and the base of the first transistor.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: May 7, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kazuo Watanabe, Satoshi Tanaka, Kazuhito Nakai, Takayuki Tsutsui
  • Patent number: 10263566
    Abstract: An amplifier having a Radio Frequency (RF) power level detector circuit for producing a control signal in accordance with a power level of an RF input signal. The control signal indicates whether the power level of the input signal is within a predetermined range of power levels greater than zero. A bias circuit is fed by the control signal, for producing a fixed bias voltage at a gate electrode of a field effect transistor (FET) to establish a predetermined quiescent current for the FET when the control signal indicates the power level of the RF input signal is within the predetermined range of power levels and to reduce the bias voltage to reduce the predetermined quiescent current when the control signal indicates the power level of the RF input signal is below the predetermined range of power levels.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: April 16, 2019
    Assignee: Raytheon Company
    Inventors: Christopher M. Laighton, Alan J. Bielunis, Edward A. Watters
  • Patent number: 10256774
    Abstract: Devices and methods related to embedded sensors for dynamic error vector magnitude corrections. In some embodiments, a power amplifier (PA) can include a PA die and an amplification stage implemented on the PA die. The amplification stage can include an array of amplification transistors, with the array being configured to receive and amplify a radio-frequency (RF) signal. The PA can further include a sensor implemented on the PA die. The sensor can be positioned relative to the array of amplification transistors to allow sensing of an operating condition representative of at least some of the amplification transistors. The sensor can be substantially isolated from the RF signal.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: April 9, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventors: Anthony Francis Quaglietta, Mark M. Doherty, Lui Lam
  • Patent number: 10230344
    Abstract: An adjustable gain power amplifier, a gain adjustment method and a mobile terminal are disclosed. The adjustable gain power amplifier comprises an input matching circuit, a gain adjustment circuit, a biasing circuit, a main amplification circuit, and an output matching circuit; the input matching circuit is connected between an input end and the gain adjustment circuit; the gain adjustment circuit is connected between the input matching circuit and the input end of the main amplification circuit; the output end of the main amplification circuit is connected to the output matching circuit, a positive power source end thereof is connected to a power supply source, a negative power source end thereof is connected to the biasing circuit; the biasing circuit provides different biasing voltages for the main amplification circuit; and the gain adjustment circuit and the biasing circuit are respectively connected to a gain adjustment control voltage (Vctrl).
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: March 12, 2019
    Assignee: SHANGHAI VANCHIP TECHNOLOGIES CO., LTD.
    Inventor: Ji Chen
  • Patent number: 10224880
    Abstract: A power amplification circuit includes: a first output transistor that has a power supply voltage supplied to its collector or drain, has a common emitter or source, amplifies an input signal supplied to its base or gate and outputs a first amplified signal from its collector or drain; a first transistor that has the power supply voltage supplied to its collector or drain, has a first current supplied to its base or gate and supplies a first bias current to the base or gate of the first output transistor from its emitter or source; and a second transistor that has its collector or drain connected to the base or gate of the first transistor, has a second current supplied to its base or gate and supplies a second bias current to the base or gate of the first output transistor from its emitter or source.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: March 5, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Yuri Honda
  • Patent number: 10211783
    Abstract: A power amplification module includes a first transistor which amplifies and outputs a radio frequency signal input to its base; a current source which outputs a control current; a second transistor connected to an output of the current source, a first current from the control current input to its collector, a control voltage generation circuit connected to the output and which generates a control voltage according to a second current from the control current; a first FET, the drain being supplied with a supply voltage, the source being connected to the base of the first transistor, and the gate being supplied with the control voltage; and a second FET, the drain being supplied with the supply voltage, the source being connected to the base of the second transistor, and the gate being supplied with the control voltage.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: February 19, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kenichi Shimamoto, Satoshi Tanaka, Tadashi Matsuoka
  • Patent number: 10171044
    Abstract: A power amplification circuit includes: a first amplifier that is input with a first signal and outputs a second signal; a bias circuit that supplies a bias current or voltage to the first amplifier; and a control voltage generating circuit that generates a control voltage in accordance with the first signal. The bias circuit includes a first transistor that outputs the bias current or voltage, a second transistor provided between the emitter or source of the first transistor and ground, and a third transistor that is supplied with the control voltage and that supplies a first current or voltage to the second transistor. The value of the first current or voltage when the signal level is a first level is larger than the value of the first current or voltage when the signal level is a second level. The first level is higher than the second level.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: January 1, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Masatoshi Hase
  • Patent number: 10158327
    Abstract: An adaptive bias circuit for a power amplifier may include a terminal node coupled to the power amplifier. The adaptive bias circuit may also include a low impedance bias circuit coupled to the terminal node. The adaptive bias circuit may further include a high drive bias circuit coupled to the low impedance bias circuit through the terminal node. A separation device may be arranged between the low impedance bias circuit and the high drive bias circuit.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: December 18, 2018
    Assignee: QUALCOMM Incorporated
    Inventor: Woonyun Kim
  • Patent number: 10158333
    Abstract: Systems, circuits and methods related to dynamic error vector magnitude (DEVM) corrections. In some embodiments, a power amplifier (PA) system can include a PA circuit having a plurality of amplification stages, and a bias system in communication with the PA circuit and configured to provide bias signals to the amplification stages. The PA system can further include a first correction circuit configured to generate a correction current that results in an adjusted bias signal for a selected amplification stage, with the adjusted bias signal being configured to compensate for an error vector magnitude (EVM) during a dynamic mode of operation. The PA system can further include a second correction circuit configured to change the correction current based on an operating condition associated with the PA circuit.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: December 18, 2018
    Assignee: Skyworks Solutions, Inc.
    Inventors: Chun-Wen Paul Huang, Lui Lam, Mark M. Doherty
  • Patent number: 10153741
    Abstract: An average power tracking mode power amplifier is disclosed herein. The average power tracking mode power amplifier includes a Power Amplifier (PA), a first Direct Current (DC)-DC voltage converter, and a second DC-DC voltage converter. The PA includes a driver stage configured to be driven by first drive voltage and a main amplification stage configured to be driven by second drive voltage. The first DC-DC voltage converter generates the first drive voltage from power voltage so that the first drive voltage is equal to or higher than the power voltage, and applies the generated first drive voltage to the driver stage. The second DC-DC voltage converter generates the second drive voltage from the power voltage so that the second drive voltage is higher than the first drive voltage, and applies the generated second drive voltage to the main amplification stage.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: December 11, 2018
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Youngoo Yang, Won Seob Lim
  • Patent number: 10142087
    Abstract: Provided is a transmission/reception module that includes: a power amplifier that outputs a transmission signal to an input/output terminal; a low-noise amplifier that amplifies a reception signal input from the input/output terminal; a duplexer that isolates the transmission signal, which is output to the input/output terminal from the power amplifier via a transmission node and a common node, and the reception signal, which is input to the low-noise amplifier from the input/output terminal via the common node and a reception node, from each other; and a phase-shift circuit that is provided between an input node of the low-noise amplifier and the reception node of the duplexer, and that adjusts an impedance at the input node of the low-noise amplifier with respect to the transmission signal and the reception signal such that the gain of the transmission signal is smaller than the gain of the reception signal.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: November 27, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Takeshi Kogure
  • Patent number: 10141892
    Abstract: A bias circuit for supplying a bias current to a RF power amplifier by using at least two voltage reference circuits coupled between the base terminal of a bipolar transistor and a voltage supply for generating a bias current to the RF power amplifier, wherein each of the at least two voltage reference circuits respectively clamps to a reference voltage at a corresponding terminal node of the voltage reference circuit on a conductive path having a current flowing from the voltage supply to the base terminal of the bipolar transistor, wherein when the current flowing out of the voltage supply increases, the current flowing through each of the at least two voltage reference circuits will also increases, so that the variation range of the bias current to the RF power amplifier will be kept in a smaller range compared with the variation range of the current flowing out of the power supply, thereby increasing the linearity of the RF power amplifier.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: November 27, 2018
    Assignee: RAFAEL MICROELECTRONICS, INC.
    Inventor: Chih-Wen Wu
  • Patent number: 10135397
    Abstract: A boost circuit for use in a power amplifier includes a voltage-to-voltage generator, a voltage-to-current converter, and a differential current generator. The voltage-to-voltage generator is configured to generate a converting voltage according to a reference voltage, wherein the absolute value of the slope at the rising edge of the converting voltage is smaller than the absolute value of the slope at the rising edge of the reference voltage. The voltage-to-current converter is configured to generate first current according to the converting voltage, wherein the waveform of the first current corresponds to the waveform of the converting voltage. The differential current generator is configured to generator second current associated with the waveform of the reference voltage, thereby outputting operational current whose value is associated with the first current and the second current.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: November 20, 2018
    Assignee: RichWave Technology Corp.
    Inventor: Shun-Nan Tai
  • Patent number: 10116274
    Abstract: The present disclosure relates to a system for biasing a power amplifier. The system can include a first die that includes a power amplifier circuit and a passive component having an electrical property that depends on one or more conditions of the first die. Further, the system can include a second die including a bias signal generating circuit that is configured to generate a bias signal based at least in part on measurement of the electrical property of the passive component of the first die.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: October 30, 2018
    Assignee: Skyworks Solutions, Inc.
    Inventors: David Steven Ripley, Philip John Lehtola, Peter J. Zampardi, Jr., Hongxiao Shao, Tin Myint Ko, Matthew Thomas Ozalas
  • Patent number: 10090806
    Abstract: The power amplifier circuit includes a first amplifier that amplifies a first signal and outputs a second signal, a second amplifier that amplifies the second signal and outputs a third signal, a power supply terminal that receives supply of a power supply voltage that varies as a function of an amplitude of the first signal, a first power supply line that supplies the power supply voltage from the power supply terminal to the first amplifier, a second power supply line that supplies the power supply voltage from the power supply terminal to the second amplifier, and a first delay circuit provided in the second power supply line.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: October 2, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Tsuyoshi Sato, Hidetoshi Matsumoto
  • Patent number: 10084418
    Abstract: A power amplifier module includes a first amplifier that amplifies an input signal to generate a first amplified signal and outputs the first amplified signal, a second amplifier that amplifies the first amplified signal to generate a second amplified signal and outputs the second amplified signal, and a matching network disposed between an output terminal of the first amplifier and an input terminal of the second amplifier. The first amplifier is provided on a first chip, and the second amplifier is provided on a second chip. The matching network has an impedance transformation characteristic adjustable in accordance with a control signal.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: September 25, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Shingo Yanagihara
  • Patent number: 10056874
    Abstract: Temperature compensation circuits and methods for adjusting one or more circuit parameters of a power amplifier (PA) to maintain approximately constant Gain versus time during pulsed operation sufficient to substantially offset self-heating of the PA. Some embodiments compensate for PA Gain “droop” due to self-heating using a Sample and Hold (S&H) circuit. The S&H circuit samples and holds an initial temperature of the PA at commencement of a pulse. Thereafter, the S&H circuit generates a continuous measurement that corresponds to the temperature of the PA during the remainder of the pulse. A Gain Control signal is generated that is a function of the difference between the initial temperature and the operating temperature of the PA as the PA self-heats for the duration of the pulse. The Gain Control signal is applied to one or more adjustable or tunable circuits within a PA to offset the Gain droop of the PA.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: August 21, 2018
    Assignee: pSemi Corporation
    Inventors: Tero Tapio Ranta, Keith Bargroff, Christopher Murphy, Robert Mark Englekirk
  • Patent number: 10048717
    Abstract: A voltage regulation device includes a first transistor, a first bias current source, a bias resistor, a second transistor, a second bias current source, and a detection adjustment circuit. The first transistor is coupled to the first bias current source for outputting a reference voltage. The bias resistor is coupled to the first transistor for receiving a regulation current. The second transistor has a first terminal for receiving a system voltage, a second terminal for outputting an output voltage, and a control terminal for receiving the reference voltage. The second bias current source is coupled to the second terminal of the second transistor. The detection adjustment circuit is coupled to the first transistor and the second transistor. When the output voltage is too low, the detection adjustment circuit activates the compensation current source to increase the voltage at the control terminal of the second transistor.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: August 14, 2018
    Assignee: Powerchip Technology Corporation
    Inventor: Kuan-Min Chen
  • Patent number: 10038404
    Abstract: Techniques are provided for adapting a bias provided to a radio frequency (RF) power amplifier (PA), so as to achieve linear operation over a wide range of conditions. The techniques use open-loop temperature compensation based upon a sensed current during periods when the RF PA is active and inactive. A closed-loop control technique is enabled when the RF PA is inactive. The combined control techniques compensate for temperature variation as well as long-term drift of the semiconductor properties of the devices within the RF PA.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: July 31, 2018
    Assignee: Infineon Technologies AG
    Inventors: Pantelis Sarais, David Seebacher, Peter Singerl, Herwig Wappis
  • Patent number: 10038410
    Abstract: A power amplification circuit includes: a first amplification transistor, a first signal being input to a base or gate thereof and a second signal obtained by amplifying the first signal being output from a collector or drain thereof; and a first bias circuit that supplies a first bias current to the base or gate of the first amplification transistor. The first bias circuit includes a first transistor that outputs the first bias current from an emitter or source thereof, and a first control circuit that controls an electrical connection between the emitter or source of the first transistor and ground. The first control circuit includes a first resistance element and a first switch element, which are connected in series with each other. The first switch element is switched on in the case of a first power mode and is switched off in the case of a second power mode.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: July 31, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Kenichi Shimamoto
  • Patent number: 10033332
    Abstract: According to an embodiment, a high-frequency semiconductor amplifier circuit includes an input terminal and an output terminal. A gate of a first transistor is connected to the input terminal. A drain of the first transistor is connected to the output terminal. A second transistor is connected between a source of the first transistor and a reference potential terminal. A bias generation circuit has an input control signal terminal, a bias voltage terminal connected to the gate of the first transistor, a control voltage terminal connected to a gate of the second transistor, and an intermediate voltage terminal connected to the drain of the first transistor. The bias generation circuit supplies a control voltage, a bias voltage, and a first voltage according to the input control signal.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: July 24, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiki Seshita, Yasuhiko Kuriyama
  • Patent number: 10014830
    Abstract: The present invention presents a DC bias circuit including a first biasing circuit and a second biasing circuit. The first biasing circuit includes a first biasing transistor and a first biasing resistor for providing a first bias voltage to an output transistor of the mixer circuit. The first biasing transistor and the output transistor are the same type of transistor and have equal channel lengths. The second biasing circuit includes a second biasing transistor and a second biasing resistor for providing a second bias voltage to an input transistor of the common gate amplifier circuit. The second biasing transistor and the input transistor are the same type of transistor and have equal channel lengths. When the input transistor and the output transistor all operate in a saturation region, alternating current signals output from the mixer circuit is unrelated to a threshold voltage of the output transistor.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: July 3, 2018
    Assignee: Intel Corporation
    Inventors: Hsien-Ku Chen, Pei-Wei Chen
  • Patent number: 10008986
    Abstract: A power amplification apparatus which is a Doherty power amplification apparatus includes a main amplifier configured to amplify an input signal, and an auxiliary amplifier configured to amplify the input signal when a level of the input signal is higher than a predetermined level. The power amplification apparatus includes an auxiliary amplifier threshold value shift detector configured to detect a threshold value shift in the auxiliary amplifier; and an auxiliary amplifier bias voltage adjustment circuit configured to adjust a bias voltage of the auxiliary amplifier based on the detected threshold value shift in the auxiliary amplifier.
    Type: Grant
    Filed: February 5, 2017
    Date of Patent: June 26, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Masato Nishimori
  • Patent number: 10003308
    Abstract: Apparatus and methods for power amplifier biasing are disclosed herein. In certain implementations, a power amplifier system includes a power amplifier bias circuit and a power amplifier. The power amplifier bias circuit includes a reference current source that generates a reference current, a bipolar reference transistor, and a transimpedance amplifier that amplifies a difference between a collector current of the bipolar reference transistor and the reference current, and that provides a base bias voltage to a base of the bipolar reference transistor. The power amplifier generates a radio frequency output signal at an output based on amplifying a radio frequency input signal received at an input. The power amplifier includes a bipolar power amplifier transistor including a base biased by the base bias voltage such that the power amplifier has a substantially flat gain response versus time.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: June 19, 2018
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventor: Lui Lam
  • Patent number: 9973164
    Abstract: A power amplifier output power control circuit includes a first operational amplifier with a negative input terminal configured to receive a power control signal; a first PMOS transistor with a grid electrode connected to an output terminal of the first operational amplifier, a source electrode connected to an external power source, and a drain electrode grounded via a voltage dividing network; a power amplifier with a power end connected to the drain electrode of the first PMOS transistor, an input terminal configured to access to a signal to be amplified, and an output terminal configured to amplify the signal; and a current sampling circuit configured to produce sampling current after sampling current across the first PMOS transistor and providing a negative feedback signal for the positive input terminal of the first operational amplifier according to the sampling current such that total output power of the power amplifier keeps unchanged.
    Type: Grant
    Filed: December 25, 2017
    Date of Patent: May 15, 2018
    Assignee: LANSUS TECHNOLOGIES INC.
    Inventors: Hua Long, Liyang Zhang, Zhenjuan Cheng, Dongjie Tang, Qian Zhao
  • Patent number: 9966910
    Abstract: The present invention relates to a power control method of an amplifying module. The amplifying module comprises a control device and an amplifying device, wherein the control device is electrically connected to the amplifying device and provides a bias current and a supply voltage to the amplifying device. Further, the control device is able to adjust the supply voltage, the bias current or the bias voltage provided to the amplifying device according to the power mode of the amplifying device.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: May 8, 2018
    Assignee: Airoha Technology Corp.
    Inventor: Chun-Hung Ho
  • Patent number: 9948247
    Abstract: An RF amplifier comprising an input-transistor having an input-transistor-base terminal, an input-transistor-collector terminal and an input-transistor-emitter terminal; a degeneration-component connected between the input-transistor-emitter terminal and a ground terminal; and a protection-transistor having a protection-transistor-base terminal, a protection-transistor-collector terminal and a protection-transistor-emitter terminal. The input-transistor-base terminal is connected to the protection-transistor-emitter terminal, and the protection-transistor-base terminal is connected to the input-transistor-emitter.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: April 17, 2018
    Assignee: NXP B.V.
    Inventor: Gian Hoogzaad
  • Patent number: 9941843
    Abstract: An envelope tracking amplifier having stacked transistors is presented. The envelope tracking amplifier uses dynamic bias voltages at one or more gates of the stacked transistors in addition to a dynamic bias voltage at a drain of a transistor.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: April 10, 2018
    Assignee: pSemi Corporation
    Inventors: Dan William Nobbe, Jeffrey A. Dykstra, Chris Olson, James S. Cable
  • Patent number: 9935588
    Abstract: Circuits, devices and methods related to multi-mode power amplifiers. A power amplifier (PA) assembly can include a radio-frequency (RF) amplification path having a first stage and a second stage, with each stage including a transistor. The PA assembly can further include a biasing circuit having a first bias path between a supply node and the base of a corresponding transistor. The PA assembly can further include a linearizing circuit implemented as either or both of a second bias path and a coupling path relative to the first bias path. The second bias path can be configured to provide an additional base bias current to the base under a selected condition. The coupling path can be configured to improve linearity of the corresponding transistor operating in a first mode while allowing a ballast resistance to be sufficiently robust for the corresponding transistor operating in a second mode.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: April 3, 2018
    Assignee: Skyworks Solutions, Inc.
    Inventors: Jianxing Ni, Michael Lynn Gerard, Ramanan Bairavasubramanian, Dwayne Allen Rowland, Matthew Lee Banowetz
  • Patent number: 9935593
    Abstract: Power amplifier bias circuit. A power amplifier bias circuit can include an emitter follower device and an emitter follower mirror device coupled to form a mirror configuration. The emitter follower device can be configured to provide a bias signal for a power amplifier at an output port. The power amplifier bias circuit can include a reference device configured to mirror an amplifying device of the power amplifier. The emitter follower mirror device can be configured to provide a mirror bias signal to the reference device.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: April 3, 2018
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventor: Aleksey A. Lyalin
  • Patent number: 9899734
    Abstract: A front end circuit includes a variable matching circuit connected to a diplexer and a switch connector connected between an antenna port and the diplexer. The variable matching circuit selectively connects matching circuits to a signal path. When one of the matching circuits is connected, the impedance as viewed from the switch connector matches an impedance of a measurement circuit near a normalized impedance of 1 in a predetermined communication band, whereas when the other matching circuit is connected, the impedance viewed from the antenna port conjugate-matches the impedance of an antenna circuit in a predetermined communication band.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: February 20, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kengo Onaka, Hiroya Tanaka, Hidenori Obiya
  • Patent number: 9893687
    Abstract: A power amplifier die includes a semiconductor substrate, a power amplifier implemented on the semiconductor substrate, a radio-frequency input configured to receive a radio-frequency input signal having a radio-frequency component and a DC bias component, a bias circuit implemented on the semiconductor substrate, the bias circuit coupled to the power amplifier, and a bias tee circuit implemented on the semiconductor substrate, the bias tee circuit configured to receive the radio-frequency input signal and pass at least a portion of the DC component to the bias circuit and at least a portion of the radio-frequency component to the power amplifier.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: February 13, 2018
    Assignee: Skyworks Solutions, Inc.
    Inventor: Philip John Lehtola
  • Patent number: 9866186
    Abstract: An amplifier includes: a package which includes a pair of edge portions; an input terminal which is provided in the edge portion; output terminals which are provided in the edge portion; a first-stage FET chip which includes an input port directly connected to the input terminal by a bonding wire; a first-stage terminal which is provided in the edge portion and is directly connected to an output port of the first-stage FET chip by a bonding wire; a second-stage terminal which is provided in the edge portion; a second-stage FET chip which includes an output port directly connected to output terminals and by a bonding wire; and an impedance matching capacitor element of which one electrode is connected to the second-stage terminal and the input port of the second-stage FET chip.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: January 9, 2018
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Naoyuki Miyazawa
  • Patent number: 9859992
    Abstract: A multi-tier interference canceler includes a first canceler, a second canceler, and a third canceler. The first canceler samples radio frequency (RF) interference generated from a linear signal using a non-linear process. The RF interference includes linear interference and non-linear interference. The first canceler cancels the linear interference from the sampled RF interference based on the linear signal to produce a first non-linear interference sample. The second canceler receives an amplitude scaled, time-shifted version of the RF interference and cancels the linear interference from the received RF interference based on the linear signal to produce a second non-linear interference sample. The third canceler cancels the non-linear interference from the second non-linear interference sample using the first non-linear interference sample, to produce a receive signal that is substantially free of the non-linear interference and the linear interference.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: January 2, 2018
    Assignee: Harris Corporation
    Inventor: Gregory Deed Hogerheiden
  • Patent number: 9836073
    Abstract: The present invention provides a current source comprising a first bias current control element, the first bias current control element being configured to generate a first current if the control value is lower than a reference value and configured to generate a second current if the control value equal to or higher than the reference value. In addition or alternatively the bias current source comprises a second bias current control element, the second bias current control element being configured to generate a third current if the control value is lower than or equal to the reference value and configured to generate a fourth current if the control value is higher than the reference value. Furthermore, the present invention provides an integrated circuit and a method.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: December 5, 2017
    Assignee: NXP USA, Inc.
    Inventors: Gerhard Trauth, Emil Cozac, Yean Ling Teo
  • Patent number: 9813027
    Abstract: Devices and methods related to embedded sensors for dynamic error vector magnitude corrections. In some embodiments, a power amplifier (PA) can include a PA die and an amplification stage implemented on the PA die. The amplification stage can include an array of amplification transistors, with the array being configured to receive and amplify a radio-frequency (RF) signal. The PA can further include a sensor implemented on the PA die. The sensor can be positioned relative to the array of amplification transistors to allow sensing of an operating condition representative of at least some of the amplification transistors. The sensor can be substantially isolated from the RF signal.
    Type: Grant
    Filed: December 28, 2014
    Date of Patent: November 7, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventors: Anthony Francis Quaglietta, Mark M. Doherty, Lui Lam
  • Patent number: 9806674
    Abstract: A power amplifier circuit includes a first amplifier transistor and a bias circuit. The first amplifier transistor amplifies a first signal and outputs a second signal. The bias circuit supplies a bias voltage or a bias current to the first amplifier transistor. The first amplifier transistor includes plural unit transistors disposed in a substantially rectangular region. The bias circuit includes first and second bias transistors and first and second voltage supply circuits. The first and second bias transistors respectively supply first and second bias voltages or first and second bias currents to the bases of unit transistors of first and second groups. The first and second voltage supply circuits respectively supply first and second voltages to the bases of the first and second bias transistors. The first and second voltages are decreased in accordance with a temperature increase. The second voltage supply circuit is disposed within the substantially rectangular region.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: October 31, 2017
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Kenji Sasaki
  • Patent number: 9800216
    Abstract: Circuits and methods related to power amplifiers. In some implementations, a bias circuit includes a reference device connectable to receive a first electrical supply level, the reference device arranged to produce an electrical bias condition using the first electrical supply level, and the reference device connectable to provide the electrical bias condition to an amplifier device connectable to a second electrical supply level. The bias circuit also includes a differential amplifier connectable to receive the first electrical supply level, the differential amplifier having a first input connectable to a first node of the reference device and a second input connectable to receive a reference electrical level, the differential amplifier arranged to maintain a first electrical level on the first node of the reference device as a function of the reference electrical level.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: October 24, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventor: Anatoli Pukhovski
  • Patent number: 9800094
    Abstract: Disclosed are low power electronic devices configured to exploit the sub-threshold swing, unidirectional tunneling, and low-voltage operation of steep slope-tunnel tunnel field-effect transistors (TFET) to improve power-conversion efficiency and power-efficiency of electrical systems incorporating the TFET as an electrical component to perform energy harvesting, signal processing, and related operations. The devices include a HTFET-based rectifier having various topologies, a HTFET-based DC-DC charge pump converter, a HTFET-based amplifier having an amplifier circuit including a telescopic operational transconductance amplifier, and a HTFET-based SAR A/D converter having a HTFET-based transmission gate DFF. Any one of the devices may be used to generate a RF-powered system with improved power conversion efficiencies of power harvesters and power efficiencies of processing components within the system.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: October 24, 2017
    Assignee: The Penn State Research Foundation
    Inventors: Huichu Liu, Ramesh Vaddi, Vijaykrishnan Narayanan, Suman Datta, Moon Seok Kim, Xueqing Li, Alexandre Schmid, Mahsa Shoaran, Unsuk Heo
  • Patent number: 9793860
    Abstract: Radio frequency (RF) amplification devices are disclosed along with methods of providing power to an RF signal. In one embodiment, an RF amplification device includes an RF amplification circuit and a voltage regulation circuit. The RF amplification circuit includes a plurality of RF amplifier stages coupled in cascade. The voltage regulation circuit is coupled to provide a regulated voltage to a driver RF amplifier stage. The voltage regulation circuit is configured to generate the regulated voltage so that the maximum output power of the RF amplification circuit is provided approximately at a first power level while the supply voltage is above a threshold voltage level. The first power level should be within the physical capabilities of the RF amplification circuit, and thus, the RF amplification circuit is prevented from being damaged once the supply voltage is above the threshold voltage level.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: October 17, 2017
    Assignee: Qorvo US, Inc.
    Inventors: David Q. Ngo, Michael B. Thomas, Praveen Varma Nadimpalli
  • Patent number: 9787271
    Abstract: A feedback gate bias circuit for use in radio frequency amplifiers to more effectively control operation of LDFET, GaNFET, GaAsFET, and JFET type transistors used in such circuits. A transistor gate bias circuit that senses drain current and automatically adjusts or biases the gate voltage to maintain drain current independently of temperature, time, input drive, frequency, as well as from device to device variations. Additional circuits to provide temperature compensation, RF power monitoring and drain current control, RF output power leveler, high power gain block, and optional digital control of various functions. A gate bias circuit including a bias sequencer and negative voltage deriver for operation of N-channel depletion mode devices.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: October 10, 2017
    Assignee: EMHISER RESEARCH LIMITED
    Inventor: Lloyd L Lautzenhiser