Abstract: There has been a problem that linearity is degraded in the conventional amplifier when the idle current is reduced in order to lower the power consumption. An amplifier of the present invention includes: a bias circuit to cause a bias current to flow; an amplifying element to amplify a signal by causing an output current corresponding to the bias current to flow; a bias current subtracting circuit to detect the signal and subtract, from the bias current, a current based on an amplitude of the signal detected; and a bias current adding circuit having an operation starting point higher than an operation starting point of the bias current subtracting circuit, and to detect the signal and add, to the bias current, a current based on an amplitude of the signal detected.

Abstract: Circuits, devices and methods related to amplification with active gain bypass. In some embodiments, an amplifier can include a first amplification path implemented to amplify a signal, and having a cascode arrangement of a first input transistor and a cascode transistor to provide a first gain for the signal when in a first mode. The amplifier can further include a second amplification path implemented to provide a second gain for the signal while bypassing at least a portion of the first amplification path when in a second mode. The second amplification path can include a cascode arrangement of a second input transistor and the cascode transistor shared with the first amplification path. The amplifier can further include a switch configured to allow routing of the signal through the first amplification path in the first mode or the second amplification path in the second mode.

Abstract: The present disclosure relates to a power amplifier circuit. The power amplifier circuit includes a voltage-controlled current source and a current mirror. The voltage-controlled current source is configured to receive a first voltage and to generate a first current. The current mirror is connected to the voltage-controlled current source and to generate a second current in response to the first current. The second current continuously changes from 0 mA to about 120 mA as the first voltage continuously changes from 0 V to about 1 V.

Abstract: A power amplifier device includes a bias circuit to generate a startup current, which is based on an internal voltage and a startup voltage, during a startup time prior to a steady driving time point, and to generate a bias current, which is based on the internal voltage, after the steady driving time point, and a startup circuit to supply the bias circuit with the startup voltage during the startup time.

Abstract: A bias circuit for supplying a bias current to an RF power amplifier by using a field-effect transistor (FET) that is controlled by a logic control signal, such as a CMOS logic control signal, for turning on or turning off the bias current supplied to the RF power amplifier, wherein the bias current will be supplied to the RF power amplifier when the FET is on, and the bias current will not be supplied to the RF power amplifier when the FET is off.

Abstract: A power amplifier circuit includes a first transistor that amplifies an RF signal; a bias current source that supplies a bias current to a second terminal of the first transistor through a first current path; and an adjustment circuit that adjusts the bias current in accordance with a variable power-supply voltage supplied from a power-supply terminal. The adjustment circuit includes first to third resistors, and an adjustment transistor including a first terminal connected to the power-supply terminal through the first resistor, a second terminal connected to the bias current source through the second resistor, and a third terminal connected to the first current path through the third resistor. When the variable power-supply voltage is not less than a first voltage and not greater than a third voltage, the adjustment circuit increases a current that flows to the power-supply terminal through a second current path as the variable power-supply voltage decreases.

Abstract: An amplifier device comprises an amplifying unit and a bias module. The amplifying unit has a first end coupled to a voltage source configured to receive a source voltage, a second end configured to receive an input signal, and a third end coupled to a first reference potential terminal configured to receive a first reference potential. The first end of the amplifying unit is configured to output an output signal amplified by the amplifying unit. The bias module is coupled to the second end of the amplifying unit, and configured to receive a voltage signal to provide a bias current to the amplifying unit. The voltage signal is a variable voltage. A supply current flowing into the amplifying unit and is adjusted in accordance with the voltage signal to stay within a predetermined range.

Abstract: A power amplifier circuit amplifies a radio-frequency signal in a transmit frequency band. The power amplifier circuit includes an amplifier, a bias circuit, and an impedance circuit. The amplifier amplifies power of a radio-frequency signal and outputs an amplified signal. The impedance circuit is connected between a signal input terminal of the amplifier and a bias-current output terminal of the bias circuit and has frequency characteristics in which attenuation is obtained in the transmit frequency band. The impedance circuit includes first and second impedance circuits. The first impedance circuit is connected to the signal input terminal. The second impedance circuit is connected between the first impedance circuit and the bias-current output terminal.

Abstract: A distortion compensation circuit includes an amplifier circuit, a bias circuit, a wiring, and a capacitive element. The bias circuit applies a bias voltage to the amplifier circuit. The wiring connects the amplifier circuit and the bias circuit. The capacitive element is connected to the wiring to cancel at least part of parasitic inductance produced in the wiring. The amplifier circuit includes an input terminal, an amplifier, a first capacitor, a connection node, and first and second resistors. An input signal is inputted into the input terminal. The amplifier amplifies the input signal. The first capacitor is disposed on a path connecting the input terminal and the amplifier. The connection node is disposed between the bias circuit and the amplifier. The first resistor is disposed on a path connecting the input terminal and the connection node. The second resistor is connected between the amplifier and the connection node.

Abstract: A method for improving the linearity of a radio frequency power amplifier, a compensation circuit (307) for implementing the method, and a communications terminal with the compensation circuit (307). In the method, a compensation circuit (307) is connected between a base (a3) and a collector (b3) of a transistor of a common emitter amplifier (306), in order to neutralize the impact of a variation in capacitance between the base (a3) and the collector (b3) of the transistor (306) according to a radio frequency signal. No additional direct-current power consumption is needed, and degradation in performance of other radio frequency power amplifiers can be avoided. The corresponding compensation circuit (307) can be easily integrated with a main amplification circuit, without affecting other performance of the main amplification circuit, and provides high adjustability.

Abstract: The present invention concerns a programmable power amplifier comprising: an amplifier core transistor circuit connected to an amplifier output node; a switch connected to the amplifier core transistor circuit, the switch being configured to switch on and off the amplifier core transistor circuit; and a feedback circuit of the amplifier core transistor circuit. The feedback circuit comprises a digital-to-analog converter and an operational amplifier having a first input node configured to receive a first reference signal; a second input node connected to the digital-to-analog converter; and an output node for outputting an operational amplifier output signal and connected to the amplifier core transistor circuit for controlling the amount of current flowing in the amplifier core transistor circuit.

Abstract: In one embodiment, a processor includes: a plurality of cores; a first storage to store parameter information for a voltage regulator to couple to the processor via a voltage regulator interface; and a power controller to control power consumption of the processor. The power controller may determine a performance state for one or more cores of the processor and include a hardware logic to generate a message for the voltage regulator based at least in part on the parameter information, where this message is to cause the voltage regulator to output a voltage to enable the one or more cores to operate at the performance state. Other embodiments are described and claimed.

Abstract: A multiple-stage amplifier includes a driver stage die and a final stage die. The driver stage die includes a first type of semiconductor substrate (e.g., a silicon substrate), a first transistor, and an integrated portion of an interstage impedance matching circuit. A control terminal of the first transistor is electrically coupled to an RF signal input terminal of the driver stage die, and the integrated portion of the interstage impedance matching circuit is electrically coupled between a current-carrying terminal of the first transistor and an RF signal output terminal of the driver stage die. The second die includes a III-V semiconductor substrate (e.g., a GaN substrate) and a second transistor. A connection, which is a non-integrated portion of the interstage impedance matching circuit, is electrically coupled between the RF signal output terminal of the driver stage die and an RF signal input terminal of the final stage die.

Abstract: A broadband power amplifier circuit is provided. The broadband power amplifier circuit includes an amplifier circuit configured to amplify a radio frequency (RF) signal to an output power based on a bias voltage and a supply voltage. Given that the output power of the RF signal may rise and fall from time to time, the broadband power amplifier circuit is configured to opportunistically increase or decrease the bias voltage in a defined future time (e.g., a future time slot or a future symbol duration) based on the output power in the defined future time. When necessary, the broadband power amplifier may be further configured to adjust the supply voltage and/or attenuate the RF signal based on the output power. As such, it may be possible to maintain class-A operation mode for the amplifier circuit. As a result, the amplifier circuit may maintain linearity and avoid memory effect with improved efficiency.

Abstract: A high-frequency signal processing apparatus and a wireless communication apparatus can achieve a decrease in power consumption. For example, when an indicated power level to a high-frequency power amplifier is equal to or greater than a second reference value, envelope tracking is performed by causing a source voltage control circuit to control a high-speed DCDC converter using a detection result of an envelope detecting circuit and causing a bias control circuit to indicate a fixed bias value. The source voltage control circuit and the bias control circuit indicate a source voltage and a bias value decreasing in proportion to a decrease in the indicated power level when the indicated power level is in a range of the second reference value to the first reference value, and indicate a fixed source voltage and a fixed bias value when the indicated power level is less than the first reference value.

Abstract: A power amplifier module includes a power amplifier circuit and a control IC. The power amplifier circuit includes a bipolar transistor that amplifies power of an RF signal and outputs an amplified signal. The control IC includes an FET, which serves as a bias circuit that supplies a bias signal to the bipolar transistor. The FET is operable at a threshold voltage lower than that of the bipolar transistor, thereby making it possible to decrease the operating voltage of the power amplifier module.

Abstract: Power amplification system with adaptive bias control. In some embodiments a power amplification system includes a power amplifier including a radio-frequency (RF) input terminal for receiving an RF signal, an RF output terminal for providing an amplified RF signal, a supply voltage terminal for receiving a power amplifier supply voltage to power the power amplifier, and one or more bias terminals for receiving one or more bias signals. The power amplification system also includes a bias controller configured to provide the one or more bias signals to the one or more bias terminals, at least one of the one or more bias signals being based on the power amplifier supply voltage.

Abstract: A power amplification module includes a first transistor which amplifies and outputs a radio frequency signal input to its base; a current source which outputs a control current; a second transistor connected to an output of the current source, a first current from the control current input to its collector, a control voltage generation circuit connected to the output and which generates a control voltage according to a second current from the control current; a first FET, the drain being supplied with a supply voltage, the source being connected to the base of the first transistor, and the gate being supplied with the control voltage; and a second FET, the drain being supplied with the supply voltage, the source being connected to the base of the second transistor, and the gate being supplied with the control voltage.

Abstract: An apparatus, comprising an input transformer; a first differential transistor pair configured to receive a first back gate bias voltage; a second differential transistor pair configured to receive a second back gate bias voltage; a cross-coupled neutralization cap comprising PMOS or NMOS transistors and configured to receive a third back gate bias voltage; and an output transformer. A method of fixing at least one back gate bias voltage to impart a desired capacitance to the transistors of at least one of the first differential transistor pair, the second differential transistor pair, or the neutralization cap. The apparatus and method may provide a power amplifier having improved linearity and efficiency.

Abstract: A bias circuit for a bipolar RF amplifier is described. The bias circuit includes a current source coupled to a bias network. The bias network supplies a base current to the transistors in the amplifier circuit of the bipolar RF amplifier. The bias circuit includes a buffer coupled to the bias network and to the bipolar RF amplifier. The buffer provides additional base current to the amplifier circuit of bipolar RF amplifier and sinks avalanche current generated by the amplifier circuit of the bipolar RF amplifier.

Abstract: A power amplifier circuit includes a bias circuit and an amplifier circuit. The bias circuit includes a first bias circuit to receive a reference voltage and an operation voltage and generate a first bias signal, a bias supply circuit to transmit the base bias signal to a base of a power amplifier, based on the first bias signal input from the first bias circuit, a switching control circuit to transmit a switching signal after a preset delay time based on a driving start signal, and a switching circuit connected between an output node of the first bias circuit and a ground, to operate in an ON state after the delay time in response to the switching signal to form a current path between the output node of the first bias circuit and the ground.

Abstract: A power amplifier apparatus, includes an envelope tracking (ET) current bias circuit configured to generate a first ET bias current by calculating a direct current DC, based on a reference voltage, and an ET current, based on an ET voltage, according to an envelope of an input signal; and a power amplifier circuit having a bipolar junction transistor supplied with the first ET bias current and a power voltage to amplify the input signal, wherein an average current of the first ET bias current is controlled to be substantially constant.

Abstract: A bias current circuit includes: an N-type MOSFET in which a gate terminal and a drain terminal are connected to a current source, and N-type MOSFETs in which respective drain terminals are connected to respective bias current output terminals and source terminals are grounded. The bias current circuit further includes: an N-type MOSFET in which one terminal type, either a drain terminal or a source terminal, is connected to the gate terminal of the N-type MOSFET, and the other terminal type is connected to the gate terminals of the N-type MOSFETs, and an N-type MOSFET in which a drain terminal is connected to the gate terminals of the N-type MOSFETs and a source terminal is grounded. A control signal, that is LOW when the bias current is supplied and is HIGH when the bias current is not supplied, is input to the gate terminal of the N-type MOSFET, and an inverse signal of the control signal is input to the gate terminal of the N-type MOSFET.

Abstract: The present disclosure relates to a system and method for algorithmic modeling interface (“AMI”) model development. Embodiments may include enabling a selection from a plurality of templates associated with an advanced equalization algorithm at a graphical user interface. Embodiments may further include receiving a selection of at least one of the plurality of templates at the graphical user interface and displaying a selected template at the graphical user interface. Embodiments may also include allowing a user to edit one or more parameters associated with the selected template at the graphical user interface and generating an algorithmic modeling interface (“AMI”) model based upon, at least in part, the selected template and the one or more parameters.

Abstract: Power amplifiers, amplifier systems, and related methods are disclosed herein. In one example embodiment, the amplifier system includes a bias controller that automatically sets a bias voltage of a power amplifier device by monitoring a reference device that is in a scaled relationship with the power amplifier device, and integrally is formed with the power amplifier device on a same semiconductor die. The bias controller can compare a voltage at an input to the reference device to a reference voltage, and then adjust a voltage at a control input of the reference device to a stabilized voltage that induces the reference device to drive the voltage at the input to the reference device equal to the reference voltage. Finally, the bias controller can transform, based on the scaled relationship, the stabilized voltage into a bias voltage applied to a control input of the power amplifier device.

Abstract: A low noise amplifier may include a post distortion cancellation block coupled to the low noise amplifier. The post distortion cancellation block may include a diode, and phase-shift logic. The phase-shift logic may be coupled in series with the diode.

Abstract: Apparatus and methods for biasing of power amplifiers are disclosed. In one embodiment, a mobile device includes a transceiver that generates a radio frequency signal and a power amplifier enable signal, a power amplifier that provides amplification to the radio frequency signal and that is biased by a bias signal, and a bias circuit that receives the power amplifier enable signal and generates the bias signal. The bias circuit includes a gain correction circuit that generates a correction current in response to activation of the power amplifier enable signal, and a primary biasing circuit that generates the bias signal based on the correction current and the power amplifier enable signal.

Abstract: Apparatus and methods for power amplifiers that can operate under a wide range of supply voltages are disclosed herein. In certain implementations, a method of adjusting a parameter of a power amplifier is provided. The method includes detecting a value of a supply voltage provided to the power amplifier. The method further includes selecting a first value from a plurality of values for a first parameter of the power amplifier based on the detected value of the supply voltage. The method further includes adjusting the first parameter of the power amplifier to the first value.

Abstract: Disclosed herein are switching or other active FET configurations that implement a main-auxiliary branch design. Such designs include a circuit assembly for performing a switching function that includes a branch including a main path in series with an auxiliary path. The circuit assembly also includes a first gate bias network connected to the main path. The circuit assembly also includes a second gate bias network connected to the auxiliary path, the second gate bias network configured to improve linearity of the switching function.

Abstract: A driving device is provided, which drives on/off a main switching element to which a diode is anti-parallel connected, wherein the driving device includes a detection unit configured to detect a voltage between a drain terminal and a source terminal; a determination unit configured to output a determination signal indicating whether a free wheeling current is flowing from the source terminal to the drain terminal based on a detected voltage detected by the detection unit; and a drive control unit configured to perform control such that the main switching element is set in an on-state on condition that an on command signal for turning on the main switching element is input and on condition that the determination signal indicating that the free wheeling current is flowing is output.

Abstract: A bias circuit providing different bias voltages depending on a power mode through a simple circuit, and a power amplifier having the same are provided. The bias circuit and the power amplifier include a bias setting unit configured to vary a voltage level of a control signal controlling a bias voltage according to an operation of a first transistor being switched-off in a high power mode and switched-on in a low power mode. A bias supplying unit includes a bias supplying transistor switched based on the control signal, to supply the bias voltage having a voltage level according to a switching operation of the bias supplying transistor.

Abstract: A switching system is connected to the power amplifier of an RF system. The switching system can switch the DC supply voltage to the power amplifier while handling the high DC current and the nanosecond switching speed requirements that are mandatory for most RF systems. The embodiments can rapidly control DC voltages but not interfere with the optimized operation of the RF transistor. The embodiments provide a desired sharp turn-on leading edge for an RF pulse while eliminating the extremely long and undesirable ramp down that typically occurs beyond the desired RF pulse period.

Abstract: The method and system for converging a 5th-generation (5G) communication system for supporting higher data rates beyond a 4th-generation (4G) system with a technology for internet of things (IoT) are provided. The method includes intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. The system includes a power amplification device capable of minimizing the effect of envelope impedance. The power amplification device may be incorporated in a terminal and a base station.

Abstract: A solid state power amplifier uses a Doherty power amplifier that can be implemented as a monolithic microwave integrated circuit. By adjusting the DC bias of the amplifying stages in each branch of the Doherty amplifier, the output power, linearity, and DC power can be adjusted to provide a specified output, where the specification for the output can include the maintaining of desired DC power and linearity. The Doherty power amplifier can be used in a satellite payload or other application utilizing solid state power amplifiers, while providing the proper amount of RF output power and DC power. A single amplifier can have its bias levels adjusted for different output levels, helping to minimize the number of designs that are required for a given satellite payload, reducing the variety of parts in a satellite payload.

Abstract: A bias circuit and a power amplifier circuit are provided in the present disclosure. The bias circuit includes an output node, a power detecting circuit, a first constant voltage bias circuit, and a constant current bias circuit. The output node is configured to provide a bias signal to a power amplifier unit. The output node is further configured to receive an input signal of the power amplifier unit. The power detecting circuit is configured to detect a power of the input signal of the power amplifier unit to provide a first control signal. The first constant voltage bias circuit is configured to selectively provide a first signal to the output node according to the first control signal. The constant current bias circuit provides a second signal to the output node.

Abstract: This invention eliminates the need for “capacitor coupling” or “transformer coupling,” and the associated undesirable parasitic capacitance and inductance associated with these coupling techniques when designing high frequency (˜60 GHz) circuits. At this frequency, the distance between two adjacent stages needs to be minimized. A resonant circuit in series with the power or ground leads is used to isolate a biasing signal from a high frequency signal. The introduction of this resonant circuit allows a first stage to be “directly coupled” to a next stage using a metallic trace. The “direct coupling” technique passes both the high frequency signal and the biasing voltage to the next stage. The “direct coupling” approach overcomes the large die area usage when compared to either the “AC coupling” or “transformer coupling” approach since neither capacitors nor transformers are required to transfer the high frequency signals between stages.

Abstract: A power amplifier circuit includes a transistor, a bias current source, and an adjustment circuit. The transistor amplifies an RF signal when supplied with a variable power supply voltage. The bias current source supplies a bias current to the base of the transistor through a first current path. The adjustment circuit increases a current flowing from the bias current source to an input terminal of a matching circuit through a second current path as the variable power supply voltage decreases, and decreases the bias current flowing from the bias current source to the base of the transistor through the first current path as the current flowing from the bias current source to the input terminal through the second current path increases.

Abstract: A circuit having (A) a transistor; (B) a bias circuit for providing setting a bias current for the transistor, the bias current having a current level in accordance with a reference current fed to the bias circuit; and (C) a bias current level controller, comprising: (i) a plurality of switches, each one of the switches comprises: a MOS FET and a GaN FET connected in a cascode configuration; and (ii) current source circuitry, comprising a plurality of current sources, each one of the current sources being connected between a voltage source and a corresponding one of the plurality of switches, the current source circuit combining currents produced by the current source in response a binary control signal fed to a gate of the MOS FET, the combined current providing the reference current fed to the bias circuit.

Abstract: Dynamic error vector magnitude (EVM) compensation is accomplished for radio frequency (RF) power amplifiers (PAs) which experience EVM distortion from thermal settling. Thermal settling causes gain changes in the PAs, and systems, apparatuses, and methods of the present disclosure compensate for known thermal transients of PAs.

Abstract: A radiofrequency (RF) amplifier includes an input terminal, an output terminal, and a power supply and biasing stage having an output coupled to the input terminal. An amplification stage of the RF amplifier includes a first transistor having a control terminal coupled to the input terminal and a first conduction terminal coupled to the output terminal. The power supply and biasing stage is configured to generate a bias voltage at the control terminal of the first transistor to simultaneously regulate a power supply voltage of the amplification stage to a first voltage and a bias current of the amplification stage to a first current.

Abstract: A low noise amplifier and a radio frequency amplification method using the low noise amplifier are provided. The low noise amplifier includes gain stage circuits, the number of which is not less than that of RF signals to be amplified, and the gain stage circuit is configured to independently amplify the RF signal when being enabled; a plurality of amplification selection switching circuits, each of which is connected to one of the gain stage circuits and is configured to, according to the RF signal, control the gain stage circuit to be enabled or disabled; a plurality of driving circuits, each of which is connected to a respective one of the plurality of gain stage circuits and is configured to, when the gain stage circuit is enabled, receive at least one RF signal amplified by the gain stage circuit and output the amplified RF signal; and at least one load circuit.

Abstract: A bias circuit provides additional bias current for power amplifiers during data bursts to compensate for the gain droop caused by a rise in the power amplifier temperature during the data burst. A bias circuit includes a difference amplifier and switches coupled to the difference amplifier. The switches operate the bias circuit in a first mode when a transmit data burst is detected and operate the bias circuit in a second mode after the bias circuit has operated in the first mode for a predetermined period of time. In the first mode, the bias circuit charges a storage capacitor and sets an output current to zero. In the second mode, the bias circuit outputs the output current that increases above the initial value of zero as the PA warms up, where the excursion of this increase of current is determined by a register. The switches disable the bias circuit when the transmit data burst ends.

Abstract: Provided is a bias control circuit that includes: a reference voltage circuit that generates a reference voltage; a resistor; a temperature dependent current generating circuit that generates a temperature dependent current, which changes depending on temperature, on the basis of the reference voltage and that supplies the temperature dependent current to one end of the resistor; a reference voltage buffer circuit that applies the reference voltage to the other end of the resistor; a constant current generating circuit that generates a constant current, which is for driving the reference voltage buffer circuit, on the basis of the reference voltage and that supplies the constant current to the other end of the resistor; and a bias generating circuit that generates a bias voltage or a bias current for a power amplification circuit on the basis of the voltage at the one end of the resistor.

Abstract: A power amplifier apparatus, includes an envelope tracking (ET) current bias circuit configured to generate a first ET bias current by calculating a direct current DC, based on a reference voltage, and an ET current, based on an ET voltage, according to an envelope of an input signal; and a power amplifier circuit having a bipolar junction transistor supplied with the first ET bias current and a power voltage to amplify the input signal, wherein an average current of the first ET bias current is controlled to be substantially constant.

Abstract: Embodiments of the disclosure relate to a low noise amplifier (LNA) circuit. The LNA circuit includes an LNA configured to amplify a radio frequency (RF) input signal to generate an RF output signal. The LNA may be inherently nonlinear and, as a result, can create a harmonic distortion(s), such as second harmonic distortion (HD2), and/or an intermodulation distortion(s), such as second order intermodulation distortion (IMD2), in the RF output signal. In exemplary aspects discussed herein, a distortion amplifier(s) is provided in the LNA circuit to generate a distortion signal(s) to suppress the harmonic distortion(s) and/or the intermodulation distortion(s) in the RF output signal.

Abstract: An apparatus includes an output transistor device configured to control an output voltage of an output node in response to a control signal and an input voltage. A current sensor is configured to sense an output current supplied from the output node. A feedback converter is configured to convert the sensed output current to a feedback signal that tracks the output voltage of the output node. The feedback converter is further configured to set a clamping threshold. A gate control circuit is configured to generate the control signal in response to the feedback signal. The gate control circuit is configured to clamp the output voltage of the output node via the control signal based on the clamping threshold.

Abstract: A power control method and device for improving radio-frequency power amplifier (RF PA) switch spectrum, the method comprising the following steps: (a) detecting the gate voltage and drain voltage, or the gate voltage and supply voltage (vdd) of a pass element (105) to obtain the saturation information of the pass element (105); (b) if the saturation information indicates that the pass element (105) is about to leave the saturation working area, shunting the drain current of the pass element (105) to the error amplifier (102) to reduce the drain output voltage, thus reducing the variation of the output voltage, preventing the output voltage from quickly approaching the supply voltage (vdd), maintaining the saturation of the pass element (105), and improving the switch spectrum characteristics of RF PA.

Abstract: A power amplifier comprising a bipolar transistor connected in cascode with a field effect transistor (FET) such as a pseudomorphic high electron mobility transistor (PHEMT) device. The bipolar transistor has a common emitter and the FET a common gate. Advantageously, the bipolar transistor is a heterojunction bipolar transistor (HBT); and the HBT and the FET may be integrated on a single die. Illustrative materials for the HBT and FET are Gallium Nitride, Indium Phosphide, or Gallium Arsenide/Indium Gallium Phosphide.

Abstract: The present disclosure relates to a radio frequency (RF) communications system including an RF power amplifier (PA), a bias circuit, and a protection circuit. The RF PA has an amplifier control terminal and a power supply terminal, the bias circuit is coupled to the amplifier control terminal, and the protection circuit is coupled between the bias circuit and the power supply terminal. Herein, the protection circuit is configured to reduce a current through the power supply terminal using the bias circuit via the amplifier control terminal when the RF PA is in an operation mode and a magnitude of a voltage at the power supply terminal exceeds a protection threshold. Further, the protection circuit is configured to be open and does not allow a current to pass through when the RF PA is in a standby mode.

Abstract: A power amplification module includes: a first transistor that amplifies a first radio frequency signal and outputs a second radio frequency signal; a second transistor that amplifies the second radio frequency signal and outputs a third radio frequency signal; and first and second bias circuits that supply first and second bias currents to bases of the first and second transistors. The first bias circuit includes a third transistor that outputs the first bias current from its emitter or source, a capacitor that is input with the first radio frequency signal and connected to the base of the first transistor, a first resistor connected between the emitter or source of the third transistor and the base of the first transistor, a second resistor connected between the capacitor and the emitter or source of the third transistor, and a third resistor connected between the capacitor and the base of the first transistor.