Abstract: A power amplification circuit includes: a first output transistor that has a power supply voltage supplied to its collector or drain, has a common emitter or source, amplifies an input signal supplied to its base or gate and outputs a first amplified signal from its collector or drain; a first transistor that has the power supply voltage supplied to its collector or drain, has a first current supplied to its base or gate and supplies a first bias current to the base or gate of the first output transistor from its emitter or source; and a second transistor that has its collector or drain connected to the base or gate of the first transistor, has a second current supplied to its base or gate and supplies a second bias current to the base or gate of the first output transistor from its emitter or source.

Abstract: A power amplification module includes a first transistor which amplifies and outputs a radio frequency signal input to its base; a current source which outputs a control current; a second transistor connected to an output of the current source, a first current from the control current input to its collector, a control voltage generation circuit connected to the output and which generates a control voltage according to a second current from the control current; a first FET, the drain being supplied with a supply voltage, the source being connected to the base of the first transistor, and the gate being supplied with the control voltage; and a second FET, the drain being supplied with the supply voltage, the source being connected to the base of the second transistor, and the gate being supplied with the control voltage.

Abstract: A power amplification circuit includes: a first amplifier that is input with a first signal and outputs a second signal; a bias circuit that supplies a bias current or voltage to the first amplifier; and a control voltage generating circuit that generates a control voltage in accordance with the first signal. The bias circuit includes a first transistor that outputs the bias current or voltage, a second transistor provided between the emitter or source of the first transistor and ground, and a third transistor that is supplied with the control voltage and that supplies a first current or voltage to the second transistor. The value of the first current or voltage when the signal level is a first level is larger than the value of the first current or voltage when the signal level is a second level. The first level is higher than the second level.

Abstract: An adaptive bias circuit for a power amplifier may include a terminal node coupled to the power amplifier. The adaptive bias circuit may also include a low impedance bias circuit coupled to the terminal node. The adaptive bias circuit may further include a high drive bias circuit coupled to the low impedance bias circuit through the terminal node. A separation device may be arranged between the low impedance bias circuit and the high drive bias circuit.

Abstract: Systems, circuits and methods related to dynamic error vector magnitude (DEVM) corrections. In some embodiments, a power amplifier (PA) system can include a PA circuit having a plurality of amplification stages, and a bias system in communication with the PA circuit and configured to provide bias signals to the amplification stages. The PA system can further include a first correction circuit configured to generate a correction current that results in an adjusted bias signal for a selected amplification stage, with the adjusted bias signal being configured to compensate for an error vector magnitude (EVM) during a dynamic mode of operation. The PA system can further include a second correction circuit configured to change the correction current based on an operating condition associated with the PA circuit.

Abstract: An average power tracking mode power amplifier is disclosed herein. The average power tracking mode power amplifier includes a Power Amplifier (PA), a first Direct Current (DC)-DC voltage converter, and a second DC-DC voltage converter. The PA includes a driver stage configured to be driven by first drive voltage and a main amplification stage configured to be driven by second drive voltage. The first DC-DC voltage converter generates the first drive voltage from power voltage so that the first drive voltage is equal to or higher than the power voltage, and applies the generated first drive voltage to the driver stage. The second DC-DC voltage converter generates the second drive voltage from the power voltage so that the second drive voltage is higher than the first drive voltage, and applies the generated second drive voltage to the main amplification stage.

Abstract: Provided is a transmission/reception module that includes: a power amplifier that outputs a transmission signal to an input/output terminal; a low-noise amplifier that amplifies a reception signal input from the input/output terminal; a duplexer that isolates the transmission signal, which is output to the input/output terminal from the power amplifier via a transmission node and a common node, and the reception signal, which is input to the low-noise amplifier from the input/output terminal via the common node and a reception node, from each other; and a phase-shift circuit that is provided between an input node of the low-noise amplifier and the reception node of the duplexer, and that adjusts an impedance at the input node of the low-noise amplifier with respect to the transmission signal and the reception signal such that the gain of the transmission signal is smaller than the gain of the reception signal.

Abstract: A bias circuit for supplying a bias current to a RF power amplifier by using at least two voltage reference circuits coupled between the base terminal of a bipolar transistor and a voltage supply for generating a bias current to the RF power amplifier, wherein each of the at least two voltage reference circuits respectively clamps to a reference voltage at a corresponding terminal node of the voltage reference circuit on a conductive path having a current flowing from the voltage supply to the base terminal of the bipolar transistor, wherein when the current flowing out of the voltage supply increases, the current flowing through each of the at least two voltage reference circuits will also increases, so that the variation range of the bias current to the RF power amplifier will be kept in a smaller range compared with the variation range of the current flowing out of the power supply, thereby increasing the linearity of the RF power amplifier.

Abstract: A boost circuit for use in a power amplifier includes a voltage-to-voltage generator, a voltage-to-current converter, and a differential current generator. The voltage-to-voltage generator is configured to generate a converting voltage according to a reference voltage, wherein the absolute value of the slope at the rising edge of the converting voltage is smaller than the absolute value of the slope at the rising edge of the reference voltage. The voltage-to-current converter is configured to generate first current according to the converting voltage, wherein the waveform of the first current corresponds to the waveform of the converting voltage. The differential current generator is configured to generator second current associated with the waveform of the reference voltage, thereby outputting operational current whose value is associated with the first current and the second current.

Abstract: The present disclosure relates to a system for biasing a power amplifier. The system can include a first die that includes a power amplifier circuit and a passive component having an electrical property that depends on one or more conditions of the first die. Further, the system can include a second die including a bias signal generating circuit that is configured to generate a bias signal based at least in part on measurement of the electrical property of the passive component of the first die.

Abstract: The power amplifier circuit includes a first amplifier that amplifies a first signal and outputs a second signal, a second amplifier that amplifies the second signal and outputs a third signal, a power supply terminal that receives supply of a power supply voltage that varies as a function of an amplitude of the first signal, a first power supply line that supplies the power supply voltage from the power supply terminal to the first amplifier, a second power supply line that supplies the power supply voltage from the power supply terminal to the second amplifier, and a first delay circuit provided in the second power supply line.

Abstract: A power amplifier module includes a first amplifier that amplifies an input signal to generate a first amplified signal and outputs the first amplified signal, a second amplifier that amplifies the first amplified signal to generate a second amplified signal and outputs the second amplified signal, and a matching network disposed between an output terminal of the first amplifier and an input terminal of the second amplifier. The first amplifier is provided on a first chip, and the second amplifier is provided on a second chip. The matching network has an impedance transformation characteristic adjustable in accordance with a control signal.

Abstract: Temperature compensation circuits and methods for adjusting one or more circuit parameters of a power amplifier (PA) to maintain approximately constant Gain versus time during pulsed operation sufficient to substantially offset self-heating of the PA. Some embodiments compensate for PA Gain “droop” due to self-heating using a Sample and Hold (S&H) circuit. The S&H circuit samples and holds an initial temperature of the PA at commencement of a pulse. Thereafter, the S&H circuit generates a continuous measurement that corresponds to the temperature of the PA during the remainder of the pulse. A Gain Control signal is generated that is a function of the difference between the initial temperature and the operating temperature of the PA as the PA self-heats for the duration of the pulse. The Gain Control signal is applied to one or more adjustable or tunable circuits within a PA to offset the Gain droop of the PA.

Abstract: A voltage regulation device includes a first transistor, a first bias current source, a bias resistor, a second transistor, a second bias current source, and a detection adjustment circuit. The first transistor is coupled to the first bias current source for outputting a reference voltage. The bias resistor is coupled to the first transistor for receiving a regulation current. The second transistor has a first terminal for receiving a system voltage, a second terminal for outputting an output voltage, and a control terminal for receiving the reference voltage. The second bias current source is coupled to the second terminal of the second transistor. The detection adjustment circuit is coupled to the first transistor and the second transistor. When the output voltage is too low, the detection adjustment circuit activates the compensation current source to increase the voltage at the control terminal of the second transistor.

Abstract: A power amplification circuit includes: a first amplification transistor, a first signal being input to a base or gate thereof and a second signal obtained by amplifying the first signal being output from a collector or drain thereof; and a first bias circuit that supplies a first bias current to the base or gate of the first amplification transistor. The first bias circuit includes a first transistor that outputs the first bias current from an emitter or source thereof, and a first control circuit that controls an electrical connection between the emitter or source of the first transistor and ground. The first control circuit includes a first resistance element and a first switch element, which are connected in series with each other. The first switch element is switched on in the case of a first power mode and is switched off in the case of a second power mode.

Abstract: Techniques are provided for adapting a bias provided to a radio frequency (RF) power amplifier (PA), so as to achieve linear operation over a wide range of conditions. The techniques use open-loop temperature compensation based upon a sensed current during periods when the RF PA is active and inactive. A closed-loop control technique is enabled when the RF PA is inactive. The combined control techniques compensate for temperature variation as well as long-term drift of the semiconductor properties of the devices within the RF PA.

Abstract: According to an embodiment, a high-frequency semiconductor amplifier circuit includes an input terminal and an output terminal. A gate of a first transistor is connected to the input terminal. A drain of the first transistor is connected to the output terminal. A second transistor is connected between a source of the first transistor and a reference potential terminal. A bias generation circuit has an input control signal terminal, a bias voltage terminal connected to the gate of the first transistor, a control voltage terminal connected to a gate of the second transistor, and an intermediate voltage terminal connected to the drain of the first transistor. The bias generation circuit supplies a control voltage, a bias voltage, and a first voltage according to the input control signal.

Abstract: The present invention presents a DC bias circuit including a first biasing circuit and a second biasing circuit. The first biasing circuit includes a first biasing transistor and a first biasing resistor for providing a first bias voltage to an output transistor of the mixer circuit. The first biasing transistor and the output transistor are the same type of transistor and have equal channel lengths. The second biasing circuit includes a second biasing transistor and a second biasing resistor for providing a second bias voltage to an input transistor of the common gate amplifier circuit. The second biasing transistor and the input transistor are the same type of transistor and have equal channel lengths. When the input transistor and the output transistor all operate in a saturation region, alternating current signals output from the mixer circuit is unrelated to a threshold voltage of the output transistor.

Abstract: A power amplification apparatus which is a Doherty power amplification apparatus includes a main amplifier configured to amplify an input signal, and an auxiliary amplifier configured to amplify the input signal when a level of the input signal is higher than a predetermined level. The power amplification apparatus includes an auxiliary amplifier threshold value shift detector configured to detect a threshold value shift in the auxiliary amplifier; and an auxiliary amplifier bias voltage adjustment circuit configured to adjust a bias voltage of the auxiliary amplifier based on the detected threshold value shift in the auxiliary amplifier.

Abstract: Apparatus and methods for power amplifier biasing are disclosed herein. In certain implementations, a power amplifier system includes a power amplifier bias circuit and a power amplifier. The power amplifier bias circuit includes a reference current source that generates a reference current, a bipolar reference transistor, and a transimpedance amplifier that amplifies a difference between a collector current of the bipolar reference transistor and the reference current, and that provides a base bias voltage to a base of the bipolar reference transistor. The power amplifier generates a radio frequency output signal at an output based on amplifying a radio frequency input signal received at an input. The power amplifier includes a bipolar power amplifier transistor including a base biased by the base bias voltage such that the power amplifier has a substantially flat gain response versus time.

Abstract: A power amplifier output power control circuit includes a first operational amplifier with a negative input terminal configured to receive a power control signal; a first PMOS transistor with a grid electrode connected to an output terminal of the first operational amplifier, a source electrode connected to an external power source, and a drain electrode grounded via a voltage dividing network; a power amplifier with a power end connected to the drain electrode of the first PMOS transistor, an input terminal configured to access to a signal to be amplified, and an output terminal configured to amplify the signal; and a current sampling circuit configured to produce sampling current after sampling current across the first PMOS transistor and providing a negative feedback signal for the positive input terminal of the first operational amplifier according to the sampling current such that total output power of the power amplifier keeps unchanged.

Abstract: The present invention relates to a power control method of an amplifying module. The amplifying module comprises a control device and an amplifying device, wherein the control device is electrically connected to the amplifying device and provides a bias current and a supply voltage to the amplifying device. Further, the control device is able to adjust the supply voltage, the bias current or the bias voltage provided to the amplifying device according to the power mode of the amplifying device.

Abstract: An RF amplifier comprising an input-transistor having an input-transistor-base terminal, an input-transistor-collector terminal and an input-transistor-emitter terminal; a degeneration-component connected between the input-transistor-emitter terminal and a ground terminal; and a protection-transistor having a protection-transistor-base terminal, a protection-transistor-collector terminal and a protection-transistor-emitter terminal. The input-transistor-base terminal is connected to the protection-transistor-emitter terminal, and the protection-transistor-base terminal is connected to the input-transistor-emitter.

Abstract: An envelope tracking amplifier having stacked transistors is presented. The envelope tracking amplifier uses dynamic bias voltages at one or more gates of the stacked transistors in addition to a dynamic bias voltage at a drain of a transistor.

Abstract: Circuits, devices and methods related to multi-mode power amplifiers. A power amplifier (PA) assembly can include a radio-frequency (RF) amplification path having a first stage and a second stage, with each stage including a transistor. The PA assembly can further include a biasing circuit having a first bias path between a supply node and the base of a corresponding transistor. The PA assembly can further include a linearizing circuit implemented as either or both of a second bias path and a coupling path relative to the first bias path. The second bias path can be configured to provide an additional base bias current to the base under a selected condition. The coupling path can be configured to improve linearity of the corresponding transistor operating in a first mode while allowing a ballast resistance to be sufficiently robust for the corresponding transistor operating in a second mode.

Abstract: Power amplifier bias circuit. A power amplifier bias circuit can include an emitter follower device and an emitter follower mirror device coupled to form a mirror configuration. The emitter follower device can be configured to provide a bias signal for a power amplifier at an output port. The power amplifier bias circuit can include a reference device configured to mirror an amplifying device of the power amplifier. The emitter follower mirror device can be configured to provide a mirror bias signal to the reference device.

Abstract: A front end circuit includes a variable matching circuit connected to a diplexer and a switch connector connected between an antenna port and the diplexer. The variable matching circuit selectively connects matching circuits to a signal path. When one of the matching circuits is connected, the impedance as viewed from the switch connector matches an impedance of a measurement circuit near a normalized impedance of 1 in a predetermined communication band, whereas when the other matching circuit is connected, the impedance viewed from the antenna port conjugate-matches the impedance of an antenna circuit in a predetermined communication band.

Abstract: A power amplifier die includes a semiconductor substrate, a power amplifier implemented on the semiconductor substrate, a radio-frequency input configured to receive a radio-frequency input signal having a radio-frequency component and a DC bias component, a bias circuit implemented on the semiconductor substrate, the bias circuit coupled to the power amplifier, and a bias tee circuit implemented on the semiconductor substrate, the bias tee circuit configured to receive the radio-frequency input signal and pass at least a portion of the DC component to the bias circuit and at least a portion of the radio-frequency component to the power amplifier.

Abstract: An amplifier includes: a package which includes a pair of edge portions; an input terminal which is provided in the edge portion; output terminals which are provided in the edge portion; a first-stage FET chip which includes an input port directly connected to the input terminal by a bonding wire; a first-stage terminal which is provided in the edge portion and is directly connected to an output port of the first-stage FET chip by a bonding wire; a second-stage terminal which is provided in the edge portion; a second-stage FET chip which includes an output port directly connected to output terminals and by a bonding wire; and an impedance matching capacitor element of which one electrode is connected to the second-stage terminal and the input port of the second-stage FET chip.

Abstract: A multi-tier interference canceler includes a first canceler, a second canceler, and a third canceler. The first canceler samples radio frequency (RF) interference generated from a linear signal using a non-linear process. The RF interference includes linear interference and non-linear interference. The first canceler cancels the linear interference from the sampled RF interference based on the linear signal to produce a first non-linear interference sample. The second canceler receives an amplitude scaled, time-shifted version of the RF interference and cancels the linear interference from the received RF interference based on the linear signal to produce a second non-linear interference sample. The third canceler cancels the non-linear interference from the second non-linear interference sample using the first non-linear interference sample, to produce a receive signal that is substantially free of the non-linear interference and the linear interference.

Abstract: The present invention provides a current source comprising a first bias current control element, the first bias current control element being configured to generate a first current if the control value is lower than a reference value and configured to generate a second current if the control value equal to or higher than the reference value. In addition or alternatively the bias current source comprises a second bias current control element, the second bias current control element being configured to generate a third current if the control value is lower than or equal to the reference value and configured to generate a fourth current if the control value is higher than the reference value. Furthermore, the present invention provides an integrated circuit and a method.

Abstract: Devices and methods related to embedded sensors for dynamic error vector magnitude corrections. In some embodiments, a power amplifier (PA) can include a PA die and an amplification stage implemented on the PA die. The amplification stage can include an array of amplification transistors, with the array being configured to receive and amplify a radio-frequency (RF) signal. The PA can further include a sensor implemented on the PA die. The sensor can be positioned relative to the array of amplification transistors to allow sensing of an operating condition representative of at least some of the amplification transistors. The sensor can be substantially isolated from the RF signal.

Abstract: A power amplifier circuit includes a first amplifier transistor and a bias circuit. The first amplifier transistor amplifies a first signal and outputs a second signal. The bias circuit supplies a bias voltage or a bias current to the first amplifier transistor. The first amplifier transistor includes plural unit transistors disposed in a substantially rectangular region. The bias circuit includes first and second bias transistors and first and second voltage supply circuits. The first and second bias transistors respectively supply first and second bias voltages or first and second bias currents to the bases of unit transistors of first and second groups. The first and second voltage supply circuits respectively supply first and second voltages to the bases of the first and second bias transistors. The first and second voltages are decreased in accordance with a temperature increase. The second voltage supply circuit is disposed within the substantially rectangular region.

Abstract: Circuits and methods related to power amplifiers. In some implementations, a bias circuit includes a reference device connectable to receive a first electrical supply level, the reference device arranged to produce an electrical bias condition using the first electrical supply level, and the reference device connectable to provide the electrical bias condition to an amplifier device connectable to a second electrical supply level. The bias circuit also includes a differential amplifier connectable to receive the first electrical supply level, the differential amplifier having a first input connectable to a first node of the reference device and a second input connectable to receive a reference electrical level, the differential amplifier arranged to maintain a first electrical level on the first node of the reference device as a function of the reference electrical level.

Abstract: Disclosed are low power electronic devices configured to exploit the sub-threshold swing, unidirectional tunneling, and low-voltage operation of steep slope-tunnel tunnel field-effect transistors (TFET) to improve power-conversion efficiency and power-efficiency of electrical systems incorporating the TFET as an electrical component to perform energy harvesting, signal processing, and related operations. The devices include a HTFET-based rectifier having various topologies, a HTFET-based DC-DC charge pump converter, a HTFET-based amplifier having an amplifier circuit including a telescopic operational transconductance amplifier, and a HTFET-based SAR A/D converter having a HTFET-based transmission gate DFF. Any one of the devices may be used to generate a RF-powered system with improved power conversion efficiencies of power harvesters and power efficiencies of processing components within the system.

Abstract: Radio frequency (RF) amplification devices are disclosed along with methods of providing power to an RF signal. In one embodiment, an RF amplification device includes an RF amplification circuit and a voltage regulation circuit. The RF amplification circuit includes a plurality of RF amplifier stages coupled in cascade. The voltage regulation circuit is coupled to provide a regulated voltage to a driver RF amplifier stage. The voltage regulation circuit is configured to generate the regulated voltage so that the maximum output power of the RF amplification circuit is provided approximately at a first power level while the supply voltage is above a threshold voltage level. The first power level should be within the physical capabilities of the RF amplification circuit, and thus, the RF amplification circuit is prevented from being damaged once the supply voltage is above the threshold voltage level.

Abstract: A feedback gate bias circuit for use in radio frequency amplifiers to more effectively control operation of LDFET, GaNFET, GaAsFET, and JFET type transistors used in such circuits. A transistor gate bias circuit that senses drain current and automatically adjusts or biases the gate voltage to maintain drain current independently of temperature, time, input drive, frequency, as well as from device to device variations. Additional circuits to provide temperature compensation, RF power monitoring and drain current control, RF output power leveler, high power gain block, and optional digital control of various functions. A gate bias circuit including a bias sequencer and negative voltage deriver for operation of N-channel depletion mode devices.

Abstract: A power amplification circuit includes: a first output transistor that has a power supply voltage supplied to its collector or drain, has a common emitter or source, amplifies an input signal supplied to its base or gate and outputs a first amplified signal from its collector or drain; a first transistor that has the power supply voltage supplied to its collector or drain, has a first current supplied to its base or gate and supplies a first bias current to the base or gate of the first output transistor from its emitter or source; and a second transistor that has its collector or drain connected to the base or gate of the first transistor, has a second current supplied to its base or gate and supplies a second bias current to the base or gate of the first output transistor from its emitter or source.

Abstract: A power amplification circuit includes: a first amplification transistor, a first signal being input to a base or gate thereof and a second signal obtained by amplifying the first signal being output from a collector or drain thereof; and a first bias circuit that supplies a first bias current to the base or gate of the first amplification transistor. The first bias circuit includes a first transistor that outputs the first bias current from an emitter or source thereof, and a first control circuit that controls an electrical connection between the emitter or source of the first transistor and ground. The first control circuit includes a first resistance element and a first switch element, which are connected in series with each other. The first switch element is switched on in the case of a first power mode and is switched off in the case of a second power mode.

Abstract: A power amplification circuit includes: a first amplifier that is input with a first signal and outputs a second signal; a bias circuit that supplies a bias current or voltage to the first amplifier; and a control voltage generating circuit that generates a control voltage in accordance with the first signal. The bias circuit includes a first transistor that outputs the bias current or voltage, a second transistor provided between the emitter or source of the first transistor and ground, and a third transistor that is supplied with the control voltage and that supplies a first current or voltage to the second transistor. The value of the first current or voltage when the signal level is a first level is larger than the value of the first current or voltage when the signal level is a second level. The first level is higher than the second level.

Abstract: Apparatus and methods for biasing a power amplifier are disclosed. In one embodiment, a method of biasing a power amplifier includes shaping an enable signal using a time-dependent signal generator to generate a control current, amplifying the control current using a current amplifier to generate a correction current, and generating a bias current for a power amplifier using a primary biasing circuit. The primary biasing circuit is configured to use the correction current to correct for a variation in gain of the power amplifier when the power amplifier is enabled.

Abstract: Provided is a power amplification module that includes: a first transistor, a first signal being inputted to a base thereof; a second transistor, the first signal being inputted to a base thereof and a collector thereof being connected to a collector of the first transistor; a first resistor, a first bias current being supplied to one end thereof and another end thereof being connected to the base of the first transistor; a second resistor, one end thereof being connected to the one end of the first resistor and another end thereof being connected to the base of the second transistor; and a third resistor, a second bias current being supplied to one end thereof and another end thereof being connected to the base of the second transistor.

Abstract: Current mirror bias circuit with voltage adjustment. A biasing system can include an input configured to receive an input current and an output configured to provide an output current. The biasing system can include a first transistor having a first base coupled to the input and a first collector coupled to a supply voltage. The biasing system can further include a second transistor having a second base coupled to the output, a second collector coupled to the input, and a second emitter coupled to a ground voltage. The biasing system can include a voltage adjustment component having a voltage adjustment input coupled to a first emitter of the first transistor and a voltage adjustment output coupled to the output. The voltage adjustment component can be configured to reduce a voltage from the voltage adjustment input to the voltage adjustment output substantially independent of a magnitude of a current through the voltage adjustment component.

Abstract: Systems, circuits and methods related to dynamic error vector magnitude (DEVM) corrections. In some embodiments, a power amplifier (PA) system can include a PA circuit having a plurality of amplification stages, and a bias system in communication with the PA circuit and configured to provide bias signals to the amplification stages. The PA system can further include a first correction circuit configured to generate a correction current that results in an adjusted bias signal for a selected amplification stage, with the adjusted bias signal being configured to compensate for an error vector magnitude (EVM) during a dynamic mode of operation. The PA system can further include a second correction circuit configured to change the correction current based on an operating condition associated with the PA circuit.

Abstract: A transmitter and method are provided for processing a transmission signal. The transmitter includes an FEM that switches a plurality of band signals for a first and second communication scheme, wherein the band signals for the first communication scheme include a first HB signal, a second HB signal, a first LB signal, and a second LB signal, and the band signals for the second communication scheme include a third LB and a third HB signal; a first PAM including a first power amplifier that amplifies the third HB signal, a second power amplifier that amplifies the first HB signal, and a third power amplifier that amplifies the first LB signal; and a second PAM including a fourth power amplifier that amplifies the third LB signal, a fifth power amplifier that amplifies the second HB signal, and a sixth power amplifier that amplifies the second LB signal.

Abstract: A wireless communication apparatus and a method for improving specific absorption ration thereof are provided. The method includes following steps. A first signal quality parameter of a first antenna and a second signal quality parameter of a second antenna are obtained. A first amplifier character parameter of a power amplifier while the power amplifier is connected to the first antenna is predicted, and a second amplifier character parameter of the power amplifier while the power amplifier is connected to the second antenna is predicted. The first antenna or the second antenna is selected to transmit a RF transmission signal according to the first amplifier character parameter, the first signal quality parameter, the second amplifier character parameter and the second signal quality parameter.

Abstract: A gate pulsing gate ladder circuit includes a series connected resistor ladder with bond pads connected to the resistor ladder between adjacent resistors. An electrical node is positioned between a first and second resistor of the resistor ladder. The electrical node is electrically connected to a gate electrode of a field effect transistor (FET). A power supply produces a constant power voltage that is applied to a pre-selected bond pad to produce a desired bias voltage at the gate electrode of the FET. A selectable gate enable voltage source is connected to an and of the resistor ladder at the first resistor and is configured to produce a first and second voltage level that when combined with the constant power voltage produces a voltage level that causes the FET to be in a conducting state or non-conducting state, respectively.

Abstract: Feedback and impedance circuits, devices and methods for broadband radio-frequency (RF) amplifiers. An RF amplifier architecture can include an amplifier having a first field-effect transistor (FET) and a second FET arranged in a cascode configuration. The gate of the first FET can be configured to receive an RF signal, the drain of the first FET can be coupled to the source of the second FET, and the drain of the second FET can be configured to output an amplified RF signal. The RF amplifier architecture can further include a first feedback circuit implemented between the drain of the second FET and the gate of the second FET to provide gain control, and a second feedback circuit implemented between the drain of the second FET and the gate of the first FET to provide an increase in a frequency range having a desirable range of gain.

Abstract: A high-frequency amplifier circuit (10) includes a high-frequency amplifier (101) and a bias circuit (20). The bias circuit (20) includes bias control elements (102, 103). An emitter of the bias control element (102) is connected to a base of the amplifier (101) via a resistor (201). An emitter of the bias control element (103) is connected to a collector of a switch element (104) via a resistor (203). The switch element (104) is a common emitter. A resistor (204) is connected between the emitter of the bias control element (102) and the emitter of the bias control element (103). A control voltage (VCTL) is applied to bases of the bias control elements (102, 103). A bias current adjustment voltage (VLIN) corresponding to an operation mode is applied to a base of the switch element (104).

Abstract: A transmit circuit includes an envelope tracker configured to determine an envelope of a transmit signal and provide bias information based on the determined envelope of the transmit signal. The transmit circuit further includes a power amplifier configured to generate an RF output signal based on the transmit signal, a bias provider configured to provide a bias for the power amplifier based on the bias information, and an impedance determinator configured to determine a measure of a load impedance of a load coupled to an output of the power amplifier. The envelope tracker is configured to adapt the bias information based on the measure of the load impedance.