Abstract: A current mirror circuit and method of generating an output current at an output node which is proportional to an input current applied to an input node. The circuit operates to receive the input current and develops a reference voltage. The reference voltage is converted to a reference current which is proportional to the input current and is applied to a high impedance node. A feedback network is coupled to said high impedance node and includes an output device driven by the high impedance node and which provides the output current to the output node. The feedback network is operable for forcing current generated by said feedback network to the high impedance node to be equal to the reference current.

Abstract: An output driver (100) for driving an external impedance load (160) comprising an output stage (110) and an impedance element (120). An input signal to the output stage (110) is controlled to provide an output signal that then drives the external impedance load (160).The output stage (110) comprises an input controller (112) that couples to a current generator (114) and a current replicator (116). A voltage reference source (150) determines a quiescent output current level of the current generator (114). The impedance element (120) comprises a current modulating resistor (230) that couples a two polarity voltage supply (130) to the output stage (110).Operations of the output driver (100) depends on the external load impedance (160). For a high external impedance load, the output driver (100) functions as a simple voltage follower.

Abstract: According to the invention, a circuit arrangement includes at least two bipolar transistors, each having a base electrode, an emitter electrode and a collector electrode. The two transistors are connected together at their base electrodes and the base electrodes are connected to an auxiliary voltage. The collector electrodes are arranged to be first and second outputs of the circuit arrangement. An emitter resistor is connected to the emitter electrode of each transistor. Each emitter resistor is a pinch resistor having a gate electrode for controlling a resistance value of the respective emitter resistor. The gate electrodes of the respective pinch resistors are configured to be first and second inputs of the circuit arrangement.

Abstract: A reflected plate amplifier (RPA) for use with electronic audio equipment. The RPA comprises an input circuit for receiving an input signal, a vacuum tube, a plate current reflector, and an output circuit for delivering an output signal. The vacuum tube has a control grid coupled to the input circuit for receiving the input signal, and a plate for delivering a plate current responsive to the input signal. The plate current reflector is a transistor having an input terminal coupled to the plate of the vacuum tube for receiving the plate current, and an output terminal for delivering a reflected current which is responsive to the plate current of the vacuum tube and therefore responsive to the input signal, while the plate current reflector holds the plate voltage of the vacuum tube substantially constant for a wide range of the plate current of the vacuum tube.

Abstract: A TC controlled RF signal detecting circuitry (211) used in the output power control circuit of a TDMA RF signal power amplifier includes positive coefficient current source (303) producing current I+ having a positive TC, negative coefficient current source (305) producing current I- having a negative TC, and current mirror (301) for summing currents I+ and I- to produce substantially identical compensated mirror currents Im1 and Im2. Anti-clamping current mirror (309) mirrors current Im2 to produce compensated currents Ia1 and Ia2, which are applied to and bias a Schottky diode coupled in series to a resistor network in each leg of diode detector (311). Each leg of diode detector (311) has a positive TC, which is substantially offset by the negative TC of compensated currents Ia1 and Ia2.

Abstract: A simple high speed precision transconductance amplifier circuit having a low offset. The circuit uses as an input stage two substantially identical transistors of a first conductivity type connected in series so as to have the same current there through, neglecting base currents. A second stage uses two substantially identical transistors of a second conductivity type connected in series, with the output of the amplifier being a current mirrored from the second stage. The offset is maintained low by maintaining the V.sub.BE of the transistors in the two stages substantially identical by connecting together the base and collector of one of the transistors in one stage and coupling the resulting V.sub.BE of the transistor so coupled to one of the transistors of opposite conductivity type in the other stage. Various embodiments and variations are disclosed.

Abstract: Current output terminals of first and second current mirror circuits are connected. An input terminal of a third current mirror circuit is connected to a node of the current output terminals of the first and second current mirror circuits. A load circuit is connected between a current output terminal of the third current mirror circuit and a first voltage. An output terminal is connected to the load circuit. First and second currents to be compared with each other are supplied to current input terminal of the first and second current mirror circuits.

Abstract: A current source including a first transistor and a second transistor with their bases connected together, a resistor connected to the emitter of the first transistor, a third transistor with its base connected to the collector of the second transistor, and an amplifying unit. The amplifying unit has its input end connected to the collector of the third transistor and is further provided with a plurality of output portions with output resistors. The plurality of output portions of the amplifying unit are connected to the collectors of the first transistor, second transistor and third transistor, respectively. The base current of the third transistor is set to make the collector currents of the first transistor and second transistor substantially equal.

Abstract: In order to minimize signal influences on the reference potential in a rail-to-rail amplifier arrangement this arrangement comprises a first differential amplifier which comprises a first and a second transistor whose emitters are coupled to a reference potential via a common first resistor, the collector of the first transistor forming the output node of the amplifier arrangement, a second differential amplifier to whose input side the input signal of the amplifier arrangement is applied, whose output side is coupled to the base of the first transistor of the first differential amplifier, and having an inverting input coupled to the output node of the amplifier arrangement, a first current mirror circuit having an input transistor to which a reference current is applied, having an output transistor which is formed by the second transistor of the first differential amplifier, and having the emitter side of both transistors coupled to a reference potential, and a second current mirror circuit to whose input si

Abstract: A triple cascoded mirror active load includes three transistors (20), (26) and (28) in a first leg and three transistors (22), (30) and (34) in an output leg connected to an output node (18). The first leg receives a current on an input node (14) on the drain of transistor (20). Transistor (20) has the gate thereof connected to the drain of transistor (26) with the gates of transistors (24) and (30) connected together and to a bias voltage. Transistor (20) is mirrored to transistor (22) by connecting the gates thereof together. Similarly, the gates of transistors (28) and (34) are connected together and also to the node (14). In this manner, the node (14) receives a low impedance on the input thereto, whereas the gate of transistor (22) sees a high impedance thereto and with only two transistors, transistors 26 and 28, disposed in a loop as a ratioed cascoded configuration.

Abstract: A cascode amplifier circuit including an input mirroring transistor (401) that generates a first output current (403) in response to the input signal. A diode connected transistor (404) generates a control bias proportional to the first output current. A cascode connected transistor output stage (405) includes a common source transistor (406) coupled to the input signal and the input mirroring transistor (401) for establishing an output current (407) in the cascode connected transistor output stage. A common gate transistor (408) is coupled to the diode connected transistor (404) and the common source transistor (406) for isolating the common source transistor (406) from any change in an output voltage present at an output terminal (409) of the common gate transistor (408) while operating to control the output currently(407) in response to the control bias.

Abstract: The amplifier uses transistors such as (metal oxide semiconductor field effect transistors) MOSFET transistors in a current mirror configuration. The MOSFET transistors are easy to package as surface mount devices. The output power of the amplifier is controlled by controlling the bias current flowing through the amplifier stage. Additionally, the amplifier has low sensitivity to the variations of the bias current to the control signal threshold. These characteristics make the amplifier ideal for use in a radio transmitter, such as a radiotelephone.

Abstract: The CMOS high-voltage sensor circuit has a voltage reference including, for example, of four N-channel MOS transistors; one pass-gate P-channel transistor; one current-mirror P-channel MOS transistor; and a conventional high-voltage sensor including, for example, of two P-channel MOS transistors and one N-channel MOS transistor. The sensor circuit of this invention generates a high-voltage signal at the output if the input voltage is greater than both the reference voltage plus two P-channel threshold voltages and the supply voltage Vcc plus two P-channel threshold voltages. The power-up or power-down sequence may be in any order without adversely affecting the operation of the circuit of this invention.

Abstract: A semiconductor integrated circuit comprises a semiconductor chip, a power supply terminal provided on the semiconductor chip for receiving a voltage from an external power supply source, an internal circuit provided on the semiconductor chip, a power supply circuit provided on the semiconductor chip for transforming an external power supply voltage received from the power supply terminal for supplying a source voltage resulting from the voltage transformation to the internal circuit, and a control circuit provided on the semiconductor chip for controlling the power supply circuit, wherein the control circuit includes external power supply voltage detecting means and/or temperature detecting means and responds to the signal from the external power supply voltage detecting means and/or the temperature detecting means by changing the power supply voltage to the internal circuit to thereby maintain the operating speed of the internal circuit to be constant.

Abstract: An active filter circuit has a filter circuit main part including a first conductance amplifier and a second conductance amplifier in which conductances are each proportional to currents or voltages of control input signals; a first signal generation circuit for generating a current or voltage which corresponds to a first signal; a second signal generation circuit for generating a current or voltage which corresponds to a second signal; a third signal generation circuit for generating a current or voltage which corresponds to a third signal; a first control signal generation circuit for generating a first control signal in accordance with a multiplication of the first signal and a fourth signal which is a ratio of the second signal to the third signal and supplying the multiplication signal to the first conductance amplifier; and second control signal generation circuit for generating a second control signal in accordance with a multiplication of the first signal and a fifth signal which is inverse ratio of t

Abstract: A current minor amplifier (CMA) includes first, second, third and fourth field effect transistors (FETs), all of the same conductivity type. The first and second FETs are in nested cascode connection in the CMA input stage, and the third and fourth FETs are in nested cascode connection in the CMA output stage. The drains of the second and fourth FETs respectively connect to the CMA input terminal and to the CMA output terminal, and the sources of the first and third FETs connect to the CMA common terminal. The potential at the CMA input terminal is applied to an interconnection of the gate electrodes of the first, second, third and fourth FETs to regulate current conduction through their channels, thereby to implement CMA operation.

Abstract: A circuit for measuring current flowing along a line including a resistance has two transistors with their emitters connected to the line on opposite sides of the resistance and with their collectors connected to a zero voltage rail via respective resistors. The bases of the transistors are connected together so that one transistor controls current flow through the second. The voltage across the resistor connected to the second transistor is representative of current flow in the line.

Abstract: Accordingly, an integrated control circuit is provided that allows for a central current reference circuit that supplies a reference current signal that employ a zero temperature coefficient. This current reference signal can be proportionally mirrored to a variety of output drivers to allow for a driving of peripheral systems with exact current requirements. Due to the fact that the reference current will not exhibit substantial variation with respect to temperature, the variability in the current supplies to the output drivers is small. As such, the output drivers can be designed to minimize the waste of current and power dissipation in the integrated system. Said output driver circuit (38) provides an output current to a load through an output pin. A output current mirror formed of a plurality of bipolar transistors (180, 188, and 194) provides the output current responsive to a control signal T1.

Abstract: A push-pull output stage for electronic integrated circuits includes two NPN transistors (Q1, Q2) connected in series between two supply terminals. The output (S) is the junction point of the transistors. A third NPN transistor (Q3) has its base and its collector connected respectively to the base and to the collector of Q1. Two current flow arms (R1, Q4 and R2, Q5) are formed, one to establish a current depending on the potential of the emitter of Q3 and the other to establish a current depending on the potential of the emitter of Q1. The arms are mounted in a current mirror arrangement, the second arm tending to copy the current of the first arm; the current mirror generating a current output (S2) representing a difference between the current set up in the second arm and the current copied from the first arm. This current output is used to control the conduction of the second transistor (Q2).

Abstract: A monolithic bipolar current mirror circuit having linear mirror-gain over four orders of current magnitude independent of device-beta (even if .beta..fwdarw.1). A third bipolar feedback transistor coupled to a unipolar buffer transistor provides voltage feedback to eliminate input loading and thereby eliminate the dependence of mirror-gain on device current-gain. The bipolar current mirror circuit can be frequency compensated and can be implemented using either PNP or NPN devices in BiCmos integrated circuit technology.

Abstract: An integrated circuit comprising a cascode current mirror and a bias stage for biassing the cascode current mirror, the cascode current mirror comprising, between an input terminal (11) and a supply voltage terminal (14), a first cascoded MOS transistor (21) and a first cascode MOS transistor (22) and, between an output terminal (12) and the supply voltage terminal (14), a second cascoded MOS transistor (23) and a second cascode MOS transistor (24).

Abstract: The present invention concerns a current amplifier which is formed by a transistor, with a view to preventing oversaturation of the transistor. The transistor saturation preventing circuit, according to the invention, includes a second transistor (Q.sub.2) which constitutes a current mirror circuit with respect to a first transistor (Q.sub.1) forming the current amplifier, a saturation detecting element (R.sub.1) connected to the second transistor (Q.sub.2) to detect saturation of the first transistor (Q.sub.1), and a current feedback element (D.sub.1), so as to decrease the base current of the first transistor (Q.sub.1).

Abstract: A wideband amplifier circuit provides high current gain and a wide bandwidth by employing only npn transistors, which have better high-frequency characteristics than those of pnp transistors, in the signal path. Wideband current amplification is achieved using npn transistors in a current-mirror configuration, with base-emitter voltage matching to permit the current gain to be easily set as a function of transistor area. The wideband amplifier circuit can also be used in a differential wideband amplifier configuration to obtain a combination of high current gain, wide bandwidth and wide output swing not obtainable with conventional differential amplifiers.

Abstract: A multi-output integrated circuit amplifier (500) consists of a first primary current mirror (510), and a plurality of secondary current mirrors (520). The first primary current mirror (510) implemented in a single substrate and having a first primary input (511). The first primary current mirror (510) generates a plurality of first inverted primary current outputs in response to a first current signal coupled to the first primary input (511). The plurality of secondary current mirrors are implemented in the same single substrate and each has a secondary input coupled to a unique one of the plurality of primary current outputs of the first primary current mirror (510), each of said plurality of secondary current mirrors (520) having a gain, and each of said plurality of secondary current mirrors (520) generating an inverted secondary current output signal, the magnitude of which is determined substantially by the unique one of the plurality of primary current outputs coupled thereto and the gain thereof.

Abstract: Frequency synthesizer employing a current mirror circuit having a control branch which includes a transistor (T1) which is supplied by a control current source (S) operating in the switch mode. An improved decay time of the current mirror circuit is obtained by providing an additional transistor (TA) in parallel with the transistor (T1), having a fixed base bias voltage such that transistor (TA) is practically cut off when the control current source (S) supplies a nominal current and starts conducting when the control current is switched off. If the additional transistor (TA) is bipolar it is provided with an anti-saturation device, for example, a Schottky diode (18). It may, however, be a field effect transistor.

Abstract: A normally non-conducting control device whose turn-on threshold decreases with increasing temperature is supplied with a control voltage which increases with temperature for causing a more rapid increase in the conduction of the control device when a predetermined temperature is exceeded.

Abstract: A self-biased cascode current mirror includes a current mirror (60), and a cascode bias generator (50). The cascode bias generator (50) includes a resistor (51) to provide a bias voltage for the current mirror (60). The current mirror (60) includes cascode transistor (64) and two mirror transistors (62, 63). The bias voltage is approximately equal to a minimum saturation voltage of the cascode transistor (64) plus a gate-source voltage of the transistor (63) of the current mirror (60). The self-biased cascode current mirror (60) has a high output impedance and high voltage swing while providing low power consumption and requiring a small layout area.

Abstract: A power amplifier is provided, wherein the output of a first transistor supplied with an input signal at the base thereof is supplied to the base of a second transistor, a current proportional to a collector current of the second transistor is supplied to the emitter of the first transistor by a current mirror circuit, a third transistor is provided for outputting an emitter current in accordance with a base-to-emitter voltage of the second transistor, and emitter currents of the second and third transistors, in accordance with an emitter potential level of the first transistor, is used as an output current. This configuration allows non-linear portions in the transistor characteristics to be cancelled by each other, thereby providing a power amplifier which presents a good linearity.

Abstract: A constant current generation circuit includes a current mirror circuit having an input PMOS transistor connected in the form of a diode connected in series to a constant current source. With a constant current I.sub.0 of the constant current source, a drain voltage V.sub.2 of the input PMOS transistor is set to a value near to the threshold voltage of the input PMOS transistor. A gate of the input PMOS transistor is connected to a gate of output PMOS transistor having its drain connected to an emitter of a PNP transistor, which has its base biased with an appropriate voltage. With this arrangement, a drain voltage V.sub.1 of the output PMOS transistor can be made equal to the drain voltage V.sub.2 of the input PMOS transistor, and therefore, the input current I.sub.0 flowing through the input PMOS transistor can be made equal to an output current I.sub.1 flowing through the output PMOS transistor.

Abstract: The disclosure relates to amplifiers using emitter follower type transistors and, more particularly, to means for the biasing of these emitter followers. The amplifier includes a follower transistor, a biasing circuit injecting a base biasing current into the base of the follower transistor, a current generator connecting the emitter of the follower transistor to a supply potential. According to one characteristic, the biasing circuit includes, firstly, a transistor called an image transistor, the emitter of which is connected to the emitter of the follower transistor and, secondly, a current injector for the injection, into the base of the follower transistor, of a current constituting a replica of the base current of the image transistor. One of the advantages of this arrangement is that it can be used to obtain the biasing circuit with transistors that are all of a same type, NPN or PNP, as the follower transistor.

Abstract: ECL to TTL converter circuits are shown having current mirror loads which produce the required differential to single-ended conversion. Saturation is avoided in the current mirror by connecting a resistor between the collector and base the output transistor.

Abstract: A circuit arrangement for converting a voltage drop (.DELTA.U) tapped from a test object from a predetermined input voltage range to a desired output voltage range includes a current mirror circuit fed by a constant current source (14) and comprising an input transistor (T1) and an output transistor (T2). The constant current source (14) lies in the collector line of the input transistor (T1) whilst in the collector line of the output transistor (T2) at least one diode (D1) lies which is traversed by a current having a value which is equal to the value of the current furnished by the constant current source (14). Lying in parallel with the series circuit of the output transistor (T2) and the diode (D1) is an identically configured circuit branch having a further transistor (T3) and at least one diode (D2) lying in the collector line thereof.

Abstract: A transistor circuit is provided which generates a collector current through an output transistor which is equal to the base current of a selected transistor in the circuit. This generated base current can be utilized in a variety of applications. Once such application is its use in an accurate cascode current mirror having an output current which is a predetermined multiple of an input current.

Abstract: A differential circuit having a predefined voltage gain of the order of unity and with a high linearity includes a differential pair of input transistors fed by a DC current source (S) each through an emitter resistor having a resistance value R. A number p of forward biased junctions and a control branch of a current mirror are inserted in the emitter path of each of the input transistors to the current source. The output branch of each current mirror feeds a respective output resistor in series with a number k of forward biased junctions. A voltage gain of k/2(2+p) is obtained when the value of the output resistors is selected to be equal to k.R/(2+p). At the same time, compensation is provided for the linearity errors of the input transistors.

Abstract: A circuit apparatus suitable for use as a basic building block of very small geometry integrated circuits (on the order of 1 micron and smaller) comprising (i) a current mirror circuit with a cascode output, comprising a first transistor and a second transistor connected in series, the first transistor coupled between a ground and the second transistor, and (ii) a single stage gain loop comprising a transresistance amplifier coupled between a control input of the second transistor and the series connection of the first and second transistors, wherein the circuit apparatus provides an output with high impedance output and with maximum swing capability.

Abstract: The present invention relates to a switchable MOS current mirror having an input and an output current branch (1, 2), a plurality of first and second MOS-field-effect transistors, and a circuit section containing a third and a fourth MOS field effect transistor (Q3, Q4). The gate electrodes of the first MOS field-effect transistors are connected respectively to a gate electrode of a second MOS field-effect transistor and to the respective drain electrodes of the first MOS field-effect transistors. The gate electrode of the third and the gate electrode of the fourth MOS field-effect transistor are connected to a control terminal (S) and to the operating voltage (Vb) respectively.

Abstract: An amplifier is operated with a low power source voltage and has a reference voltage of 1.25 V or less. The temperature characteristic of the amplifier is controllable. The amplifier comprises substantially similar circuits and constants on its left and right sides under a condition that a voltage source is not connected to an input terminal, except that a diode-connected transistor is provided. Paying attention to the left-side circuit, the circuit which has the diode-coupled transistor having a forward voltage and resistors 22 and 23, is expressed by an equivalent circuit by the (Ho)-Thevenin theorem.

Abstract: A speakerphone with a varying gain current mirror circuit is provided. The varying gain current mirror circuit is within the DC control loop of the speakerphone such that by varying the gain of the current mirror circuit, the attenuation range of the speakerphone is correspondingly varied.

Abstract: A current mirror circuit is modified to supply bias current to the input transistor that varies in accordance with variations in the base-emitter voltages of the input and output transistors, and in accordance with the variations in collector voltage of the output transistor. The bias current variations are controlled by a pair of complementary conductivity type transistors that are closely coupled in manner similar to the coupling of the input and output transistors with associated bias supplies and unity gain amplifier connected to alter bias conditions in accordance with variations in the base-emitter voltage and the collector voltage of the output transistor.

Abstract: The present invention is an improved current mirror circuit. This improved current mirror circuit includes first and second transistors of the same conductivity type and have bases connected together. The first transistor is connected between a first supply terminal and an input terminal. The second transistor is connected between a first supply terminal and an output terminal. Included is a feedback circuit for providing a voltage feedback between the input terminal and the bases of the first and second transistors. Also included is a bias circuit for providing a bias current to the feedback circuit that is based on the input current.

Abstract: The disclosure relates to current mirrors in which a high level of copying error may arise out of the collapse of the gain of the transistors. The mirror includes, in its output arm, a "Darlington" type amplifier subjected to feedback by a buffered mirror. The error gets cancelled for a gain .beta.=1. A second Darlington amplifier mounted symmetrically with the first Darlington enables the V.sub.CE values of the transistors to be balanced. The disclosed device can be applied to current mirrors when the transistors are low-gain transistors (.perspectiveto.1).

Abstract: A non-linear current mirror amplifier includes a master diode-connected transistor in series with a resistor to provide a forward diode bias and a resistive drop. A slave transistor is forward biased by the forward diode bias and the resistive drop. A current splitter applies a fraction of an input current to the master diode-connected transistor.

Abstract: A voltage-follower circuit has an input biasing stage that generates an input stage bias current and a tracking bias current. An input stage generates an intermediate voltage signal and sources an input current in response to an input voltage signal and the input stage bias current. An output biasing stage generates an output bias current. An output biasing stage generates an output voltage signal and sinks a portion of the input bias current in response to the intermediate voltage signal and the output bias current. A cancellation stage sinks substantially all of the input current in response to the tracking bias current. A cascode stage isolates the input biasing stage from the input stage and the cancellation stage. A compensation stage sinks a portion of the tracking bias current which is substantially equivalent to the portion of the input bias current sunk by the output stage.

Abstract: A power-on-reset circuit includes a plurality of MOS transistors and a first depletion type N-channel MOS transistor connected in series to an input terminal of a current mirror circuit. A capacitor is connected between the input terminal and a voltage supply terminal. A second depletion type N-channel MOS transistor having a low current driving capacity is connected to an output terminal of the current mirror circuit. The degree of integration can be increased by constituting an integrating circuit with depletion type N-channel MOS transistors in place of a resistor. In addition, the voltage supply voltage is compared to the sum of the threshold voltage of the plurality of MOS transistors. This makes it possible to initialize the internal circuit positively even if the rise time of the voltage supply voltage becomes larger than the time constant of the integrating circuit.

Abstract: A power amplifier supplies substantial load currents that must be accurately monitored to provide feedback so that the load currents can be properly controlled. A sense current is generated from a load current that is scaled such that the sense current is an accurate representation of the load current but having a substantially smaller magnitude. The scaled sense current is generated by coupling a power sense resistor to a pilot sense resistor by a voltage follower. The power sense resistor is in series with the load current and develops a load voltage thereacross. A sense voltage, being substantially equal to the load voltage is impressed at the pilot sense resistor by the voltage follower. The pilot sense resistor is some predetermined ratio of the power sense resistor so that absolute values are not critical. The sense current flowing through the pilot sense resistor is therefore scaled according to the ratios of the power and pilot sense resistors.

Abstract: An amplifier in which a current mirror circuit 53 is formed of a transistor Q25 on the input side and a transistor Q26 on the output side. The base-emitter junction area of the transistor Q26 is set to be N (N>1) times as large as that of the transistor Q25. A parallel circuit of a resistor R25 and a capacitor C25 is connected between the base of the transistor Q25 and its bias point Q27. A resistor R26 is connected between the base of the transistor Q26 and the bias point Q27. The resistance value of the resistor R25 is set to be virtually N times as large as the resistance value of the resistor R26. When an input current i25 is supplied to the transistor Q25, an output current i26, which is N times as large as the input current, is obtained from the transistor Q26 on the output side, whereas the output current i26 is held lower than N times of the input current i25 when the frequency of the input current is high.

Abstract: A current mirror circuit has first through fourth transistors. The first and second transistors are of a first conductivity type and have their emitters connected to a power source and their bases commonly connected. The third transistor is of the first conductivity type and has its collector connected to a reference potential, its emitter connected to the bases of the first and second transistors, and its base connected to a collector of the first transistor. The fourth transistor is of the first conductivity type and has its emitter connected to a collector of the second transistor. A control device controls a base of the fourth transistor by an output current which changes in accordance with a current flowing in the collector of the first transistor.

Abstract: A BICMOS sense amplifier for content addressable memory circuits which combines the low power dissipation and high noise immunity of CMOS devices while maintaining the high drive capability and switching speed associated with bipolar devices. A combination of an RS latch at the output of a bipolar sense amplifier storing this output, and a clamping device at the base of the bipolar sensing amplifier shorting the base to ground, bring the bipolar device out of saturation after each sensing cycle to improve the switching speed. A biasing network is designed to bring the base of the bipolar sense amplifier up to a base-emitter turn-on voltage, while maintaining the output at a high level to improve voltage sensitivity and switching speed. Current mirrors are used in the biasing network to optimize performance over temperature and process variations.

Abstract: A circuit and method for buffering a high output impedance voltage generator circuit to a low input impedance load circuit is described. Two emitter-follower stages are used with a load current feedback configuration so that the base to emitter voltages of all four transistors maintain a fixed relationship and therefore the output voltage presented to the load maintains a fixed relationship to the input voltage presented to the buffer amplifier circuit.

Abstract: The design of a current-to-voltage converter with a uniform transfer function in its feedback loop (12) is proposed. It employs a very large, double-shielded measuring resistance (13) and a two-stage setup to perform a fully linear I/V conversion with a conversion factor of 10.sup.10 V/A and a bandwidth of 1 MHz. With the low noise level attained, and with the bandwidth and conversion factor mentioned, it will be possible to monitor events involving as few as 300 electrons. The current-to-voltage converter comprises a differential input amplifier (8), a current source (11) for supplying said differential amplifier (8), at least one operational amplifier (10, 14), and a high-valued measuring resistance (13) the voltage drop across which is being taken as a measure of the current to be detected. The measuring resistance (13) is arranged in a feedback loop (12) associated with said differential amplifier (8).