Having Compensation For Interelectrode Impedance Patents (Class 330/292)
  • Patent number: 10298190
    Abstract: A method for phased array tapering includes setting a gain at a phase-invariant variable gain amplifier in each of a plurality of front-ends of a phased array transceiver to perform tapering of beam pattern side lobes. A resistance in the phase-invariant variable gain amplifier is set to provide a phase shift that is independent of gain.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: May 21, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John F. Bulzacchelli, Bodhisatwa Sadhu, Alberto Valdes Garcia
  • Patent number: 10027289
    Abstract: An amplifier includes an input terminal for receiving an input signal, an output terminal for outputting an output signal, a first transistor, a second transistor having a first terminal coupled to a second terminal of the first transistor, a third transistor having a first terminal coupled to a second terminal of the second transistor, a capacitor coupled between a control terminal and a second terminal of the third transistor, a bias circuit coupled to the first terminal of the third transistor for providing a bias voltage to the third transistor, a fourth transistor having a first terminal coupled to the input terminal and a second terminal coupled to the output terminal for providing a bypass path, and a fifth transistor having a first terminal coupled to the first terminal of the first transistor and a second terminal coupled to the output terminal.
    Type: Grant
    Filed: March 26, 2017
    Date of Patent: July 17, 2018
    Assignee: RichWave Technology Corp.
    Inventors: Chih-Sheng Chen, Chang-Yi Chen
  • Patent number: 9917555
    Abstract: An amplifier includes an input node, an output node, a transistor and a transformer. The input node is configured to receive a first signal. The output node is configured to output an amplified first signal. The transistor includes a first terminal, a second terminal and a third terminal. The first terminal is coupled to the input node and a first supply voltage source. The second terminal is coupled to a second supply voltage source and the output node. The third terminal is coupled to a reference node. The transformer is coupled to the first terminal and the third terminal. The transistor is configured to operate in a sub-threshold region and a near-triode region.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: March 13, 2018
    Assignee: TWAIWAN SEMICONDUCTOR MANUFACTORING COMPANY, LTD.
    Inventors: Jun-De Jin, Chi-Hsien Lin, Ho-Hsiang Chen, Hsien-Yuan Liao, Ying-Ta Lu
  • Patent number: 9698729
    Abstract: A CMOS cascode amplifier comprises a cascode circuit comprising a plurality of branches in parallel, each branch comprising a first transistor and a second switchable transistor connected in series forming a cascode pair, wherein the cascode circuit is configured to amplify an input signal. The CMOS cascode amplifier further comprises a bias circuit configured to bias the cascode circuit by providing a bias signal to the first transistor in each of the plurality of the branches in the cascode circuit. In addition, the CMOS cascode amplifier comprises a switching control circuit configured to control a quiescent current in the cascode circuit based on selectively activating the plurality of branches by providing a switching control signal that switches on the second switchable transistor in the one or more activated branches.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: July 4, 2017
    Assignee: Infineon Technologies AG
    Inventor: Winfried Bakalski
  • Patent number: 9501075
    Abstract: A low-dropout voltage regulator includes a power transistor configured to receive an input voltage and to provide a regulated output voltage at an output voltage node. The power transistor includes a control electrode configured to receive a driver signal. A reference circuit is configured to generate a reference voltage. A feedback network is coupled to the power transistor and is configured to provide a first feedback signal and a second feedback signal. The first feedback signal represents the output voltage and the second feedback signal represents an output voltage gradient. An error amplifier is configured to receive the reference voltage and the first feedback signal representing the output voltage. The error amplifier is configured to generate the driver signal dependent on the reference voltage and the first feedback signal. The error amplifier includes an output stage that is biased with a bias current responsive to the second feedback signal.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: November 22, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Giovanni Bisson, Marco Flaibani, Marco Piselli
  • Patent number: 9494959
    Abstract: A current source for quickly adjusting an output current includes a constant current generation module, coupled to a control node, for generating a predefined current flowing through the control node in order to determine a voltage of the control node; a capacitor, coupled to an output terminal of the current source; a current variation detection module, coupled between the control node and the capacitor, for generating a variation on the voltage of the control node via the capacitor when the output terminal of the current source receives an instant current variation; and a trans-conductance amplifier, coupled between the control node and the output terminal, for changing a magnitude of the output current of the output terminal when the variation on the voltage of the control node is generated.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: November 15, 2016
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Min-Hung Hu, Chiu-Huang Huang, Chen-Tsung Wu, Chun-Wei Huang, Pin-Han Su
  • Patent number: 9484879
    Abstract: An apparatus, which includes a first electronic device, a first nonlinear capacitance compensation circuit, and a capacitance compensation control circuit, is disclosed. The first electronic device has a first nonlinear capacitance and is coupled to the first nonlinear capacitance compensation circuit, which has a first compensation capacitance and receives a first compensation control signal. The capacitance compensation control circuit adjusts the first compensation capacitance using the first compensation control signal to at least partially linearize the first nonlinear capacitance.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: November 1, 2016
    Assignee: Qorvo US, Inc.
    Inventors: Baker Scott, George Maxim, Dirk Robert Walter Leipold, Christian Rye Iversen, Eric K. Bolton, Daniel Charles Kerr
  • Patent number: 9310455
    Abstract: A probe system for registering a differential input signal has a first input network, which is supplied with a first component of the differential input signal in order to generate a first intermediate signal, and a second input network which is supplied with a second component of the differential input signal in order to generate a second intermediate signal. A differential amplifier for the amplification of the difference between the intermediate signals is arranged in the signal flow direction downstream of the input networks. At least one compensation network is used to compensate the influence of the input networks and is arranged at the output end of the differential amplifier or in a feedback path connecting an output to an input of the differential amplifier.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: April 12, 2016
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventors: Martin Peschke, Cédric Bonnet
  • Patent number: 9300260
    Abstract: This disclosure relates generally to radio frequency (RF) amplification devices and methods of operating the same. In one embodiment, an RF amplification device includes an RF amplification circuit and a stabilizing transformer network. The RF amplification circuit defines an RF signal path and is configured to amplify an RF signal propagating in the RF signal path. The stabilizing transformer network is operably associated with the RF signal path defined by the RF amplification circuit. Furthermore, the stabilizing transformer network is configured to reduce parasitic coupling along the RF signal path of the RF amplification circuit as the RF signal propagates in the RF signal path. In this manner, the stabilizing transformer network allows for inexpensive components to be used to reduce parasitic coupling while allowing for smaller distances along the RF signal path.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: March 29, 2016
    Assignee: RF Micro Devices, Inc.
    Inventors: George Maxim, Baker Scott, Ming Tsai, Alireza Shirvani
  • Patent number: 9276468
    Abstract: In one aspect, a current source is provided to limit noise and offset. In one embodiment, a source transistor is provided, with current sourced at the drain. A feedback network runs from the source node to the gate. The feedback network produces voltage gain by a transconductance, such as a transistor. Appropriate capacitors are also provided, and two pairs of switches are disposed to provide offset cancellation by toggling between gain and clamp modes in the switched capacitor architecture.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: March 1, 2016
    Assignee: ANALOG DEVICES, INC.
    Inventors: William T. Boles, Michael R. Elliott
  • Patent number: 9231525
    Abstract: Systems and techniques are disclosed for configuring a circuit containing a two-stage amplifier including a first stage containing at least a differential amplifier, a second stage containing at least a transistor, and a sensing circuit configured to provide a gate voltage to a compensation component. The compensation component may be configured to connect the first stage and the second stage and to generate a lead-lag compensation. The compensation component may contain a compensation capacitor and a variable compensation resistive component in series connection with the compensation capacitor.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: January 5, 2016
    Assignee: Google Inc.
    Inventor: Arnold Feldman
  • Patent number: 9112453
    Abstract: An operational amplifier circuit including a main circuit, a compensation capacitor, a power circuit, and a set of switches is disclosed. The main circuit has an output terminal. The compensation capacitor has a first end connected to an internal node of the main circuit and a second end connected to the output terminal of the main circuit. The power circuit provides a current or a voltage as predetermined. The set of switches connects the power circuit to the compensation capacitor. When the main circuit is not in an output state, the set of switches is switched to allow the power circuit to provide the current or voltage to the compensation capacitor. When the main circuit is in the output state, the set of switches is switched to disconnect the power circuit from the compensation capacitor and allow the main circuit to return to an output circuit state and operate normally.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: August 18, 2015
    Assignee: Novatek Microelectronics Corp.
    Inventors: Pei-Ye Wang, Ji-Ting Chen
  • Patent number: 9112462
    Abstract: A variable-gain current conveyor-based instrumentation amplifier without introducing distortion. An exemplary variable-gain instrumentation amplifier includes a first dual-output transconductance amplifier (DOTA) (i.e., current conveyor) that receives a first input voltage, a second DOTA that receives a second input voltage, a first resistive element connected between the first and second DOTA, an amplifier connected to the second DOTA at an inverting input, and a second resistive element that connects the second DOTA and the inverting input to an output of the amplifier. At least one of the resistive elements is a variable resistive element.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: August 18, 2015
    Assignee: Honeywell International Inc.
    Inventor: Paul M Werking
  • Patent number: 9106181
    Abstract: Linearity and power efficiency in a power amplifier circuit are enhanced. The power amplifier circuit includes a first transistor that amplifies a signal input to the base and that outputs the amplified signal from the collector and a first capacitor that is disposed between the base and the collector of the first transistor and that has voltage dependency of a capacitance value lower than that of a base-collector parasitic capacitance value of the first transistor.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: August 11, 2015
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Masahiro Ito, Kiichiro Takenaka, Satoshi Tanaka, Hidetoshi Matsumoto
  • Patent number: 9086710
    Abstract: A compensator circuit includes a first transconductance amplifier to convert an input voltage to a first output current. A second transconductance amplifier converts the input voltage to a second output current. A buffer includes an input and an output. The input of the buffer receives the second output current. A resistance is connected between an output of the first transconductance amplifier and an output of the buffer. A capacitance connected (i) between an output of the second transconductance amplifier and a terminal at a reference potential, and (ii) between the input of the buffer and the terminal. An output voltage of the compensator circuit is based on the first output current and is a voltage across the resistance, the buffer and the capacitance.
    Type: Grant
    Filed: February 5, 2013
    Date of Patent: July 21, 2015
    Assignee: MAXIM INTEGRATED PRODUCTS, INC.
    Inventors: Andrea Milanesi, Stefano Casula
  • Patent number: 9077310
    Abstract: A power combiner includes a primary winding and a secondary winding, wherein at least the primary winding comprises a center-tap; and a termination module operably coupled to the center-tapped primary winding and arranged to provide harmonic terminations on a plurality of frequencies. In addition, there is provided a radio frequency transmitter having a power combiner, where the power combiner includes a primary winding and a secondary winding, wherein at least the primary winding includes a center-tap; and a termination module operably coupled to the center-tapped primary winding and arranged to provide harmonic terminations on a plurality of frequencies.
    Type: Grant
    Filed: December 25, 2013
    Date of Patent: July 7, 2015
    Assignee: MEDIATEK INC.
    Inventor: Ming-Da Tsai
  • Patent number: 8963639
    Abstract: A three stage amplifier is provided and the three stage amplifier comprises a first gain stage, a second gain stage and a third gain stage wherein said first stage receives an amplifier input signal and said third gain stage outputs an amplifier output signal. The amplifier includes a feedback loop having a current buffer and a compensation capacitance provided from the output of said third gain stage to the output of the first gain stage. In addition, an active left half plane zero stage is embedded in said feedback loop for cancelling a parasitic pole of said feedback loop.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: February 24, 2015
    Assignee: University of Macau
    Inventors: Zushu Yan, Pui-In Mak, Man-Kay Law, Rui Paulo da Silva Martins
  • Patent number: 8907727
    Abstract: Embodiments are directed to capacitance compensation via a compensation device coupled to a gain device to compensate for a capacitance change occurring due to an input signal change, along with a controller coupled to the compensation device to receive the input signal and to control an amount of compensation based on the input signal. In some embodiments, banks may be formed of multiple compensation devices, where each of the banks has a different size and is coupled to receive a different set of bias voltages.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: December 9, 2014
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Anil Samavedam, David E. Bockelman, Vishnu Srinivasan, Eric Kimball
  • Patent number: 8890610
    Abstract: An operational amplifier (10) capable of driving a capacitive load (CLOAD) and/or a resistive load (RLOAD) includes a first gain stage (2) having an output coupled to a high impedance node (3) and a second gain stage (5) having an input coupled to the first high impedance node. A gain reduction resistor (RD) and an AC coupling capacitor (CD) are coupled in series between the high impedance node and a reference voltage. A Miller feedback capacitor (CM) is coupled between an output conductor (7) of the second gain stage and the high impedance node. The output of the second gain stage may be coupled to the high impedance node by a cascode transistor (MCASCODE).
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: November 18, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Steven G. Brantley, Vadim V. Ivanov
  • Publication number: 20140306764
    Abstract: Amplifier circuits and methods of cancelling the Miller effects in amplifiers are disclosed herein. An embodiment of an amplifier circuit includes an input and an output. An amplifier is connected between the input and the output of the circuit. A voltage source is connected to the output, wherein the voltage source output is one hundred eighty degrees out of phase with the voltage output by the amplifier, and wherein the voltage source cancels gain due to the Miller effect of a Miller capacitance between the input and output.
    Type: Application
    Filed: April 16, 2013
    Publication date: October 16, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Matthew David Rowley, Rajarshi Mukhopadhyay
  • Patent number: 8860391
    Abstract: A DC-DC converter converts an input voltage input from an input terminal to a predetermined voltage and outputs the converted voltage from an output terminal, the DC-DC converter including an output control transistor and an operation control circuit that has an error amplifying circuit, whereby the error amplifying circuit includes an output circuit configured to output an error voltage and include an output transistor of a source follower connection, a series circuit configured to include a resistor for phase compensation and a capacitor for phase compensation and be connected between a control electrode of the output circuit and a grounding voltage terminal, and an amplifying circuit configured to be positioned on a side more distant from a side outputting the error voltage relative to the output circuit in the error amplifying circuit, and include a voltage generating element as a load of the amplifying circuit.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: October 14, 2014
    Assignee: Ricoh Company, Ltd.
    Inventor: Ippei Noda
  • Patent number: 8787850
    Abstract: In one implementation, a power amplifier may include a gain device to receive an input signal and to output an amplified signal, and a compensation device coupled to the gain device to compensate for a change in a capacitance of the gain device occurring due to a change in the input signal. The power amplifier may be formed using a complementary metal oxide semiconductor (CMOS) process.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: July 22, 2014
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: David E. Bockelman, Vishnu Srinivasan
  • Patent number: 8773204
    Abstract: Techniques for reducing undesired source degeneration inductance are disclosed. In an exemplary design, an apparatus includes first and second connections. The first connection includes a first parasitic inductance acting as a source degeneration inductance of an amplifier. The second connection includes a second parasitic inductance magnetically coupled to the first parasitic inductance to reduce the source degeneration inductance of the amplifier. The amplifier (e.g., a single-ended power amplifier) may be coupled to circuit ground via the first connection. An impedance matching circuit may be coupled to the amplifier and may include a circuit component coupled to circuit ground via the second connection. The first connection may be located sufficiently close to (e.g., within a predetermined distance of) the second connection in order to obtain the desired magnetic coupling between the first and second parasitic inductances.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: July 8, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Jose Cabanillas, Calogero D Presti, Norman L Frederick, Jr.
  • Patent number: 8766726
    Abstract: An operational amplifier includes an operational amplifier circuit having at least one output node and an output stage coupled to the output node, the output stage containing an output and first MOS transistor employed in a common source amplifier mode, a frequency compensation capacitor coupled between the output of the output stage and the gate of the first transistor circuit by means of a second MOS transistor employed in a common gate amplifier mode. The other node of the capacitor and the output of the output stage are coupled to the amplifier output node with a resistor.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: July 1, 2014
    Assignee: LSI Corporation
    Inventor: Oleksiy Zabroda
  • Patent number: 8723604
    Abstract: Compensation methods and systems for voltage-feedback amplifiers provide improved dynamic performance (i.e., increased bandwidth and the elimination or alleviation of a slew limitation) at high gains by direct feedback of an AC signal (i.e., an intermediate voltage) to an amplifier input without being attenuated by feedback resistor network.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: May 13, 2014
    Assignee: Analog Devices, Inc.
    Inventor: Quan Wan
  • Patent number: 8669813
    Abstract: The present invention relates to a device for neutralization of a signal obtained by transposition to a high frequency of a useful signal supplied by a unit of equipment, the said equipment having a spurious capacitance Cparasite that varies over time. The device comprises a neutralization capacitance Cneut and means with adjustable gain G, together with means for feedback controlling the gain G in such a manner that, continuously, G×Cneut=Cparasite.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: March 11, 2014
    Assignee: Thales
    Inventor: Stéphane Bouyat
  • Patent number: 8669814
    Abstract: The invention relates to a device for neutralizing a signal obtained by modulating, on to a high frequency carrier, a useful signal delivered by a system comprising a parasitic capacitance Cp that varies over time, the device comprising a neutralizing capacitance Cn, means for providing an adjustable gain G, said means being equipped with a JFET field-effect transistor (J1) equipped with a gate first electrode and drain and source second electrodes, and a control loop for providing gain G so that G×Cn permanently equals Cp by controlling the voltage on the gate first electrode of the transistor (J1). The neutralizing capacitance Cn comprises a first capacitor Cneutro1 and a second capacitor Cneutro2 placed in parallel at the output of said means for providing gain G.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: March 11, 2014
    Assignee: Thales
    Inventor: Jean-Michel Muguet
  • Patent number: 8604879
    Abstract: An impedance-matched amplifier utilizing a feed-forward linearization technique involving multiple negative feedbacks and distortion compensation without active tail current sources reduces noise, distortion, power consumption and heat dissipation requirements and increases linearity, dynamic range, signal-to-noise-ratio, sensitivity and quality of service. Some differential amplifier embodiments of the invention consume less than 2 mA at 5 Volts or 10 mW power consumption per 1 mW in peak and sustained output IP3 performance above 40 dBm. In contrast, for an input signal frequency of 200 MHz, a 16 dB gain state-of-the-art differential amplifier consumes 100 mA at 5 Volts with a peak output IP3 of 36 dBm while an implementation of a 16 dB gain differential amplifier embodying the invention consumes 77.7 mA at 5 Volts with a peak output IP3 of 46 dBm and sustained at or above 40 dBm over a wide frequency range.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: December 10, 2013
    Assignee: Integrated Device Technology Inc.
    Inventors: Jean-Marc Mourant, Feng-Jung Huang, Ran Li, Chuying Mao
  • Patent number: 8587378
    Abstract: An analog pre-distortion linearizer having predetermined gain and phase characteristics as a function of input RF signal power is disclosed. The linearizer comprises a core circuit comprising an input terminal configured to receive an input RF signal; an output terminal configured to provide a processed version of that signal; a transistor having a gate, a drain, and a source; and a feedback circuit, presenting an impedance at the frequency of the RF signal, connected to the transistor. The gate is connected to the input terminal and the drain is connected to the output terminal. First and second dc bias voltages applied to the gate and drain respectively cause the transistor to operate at a quiescent bias point in a saturated region of the transistor I-V plane. The quiescent bias point and the impedance are selected such that the linearizer has the predetermined gain and phase characteristics.
    Type: Grant
    Filed: March 11, 2012
    Date of Patent: November 19, 2013
    Inventor: Chandra Khandavalli
  • Patent number: 8476975
    Abstract: An operational amplifying device comprises an input stage and an output stage. The input stage receives and processes an input voltage to output an amplified voltage. The output stage is electrically connected to the input stage in series. The output stage comprises a first switch and a second switch. The first switch is configured to turn on for transferring the amplified voltage. The second switch is connected in parallel with the first switch and is configured to turn on for transferring the amplified voltage. The second switch is turned off when the first switch is turned on such that the amplified voltage is transferred through the first switch to the first resistor array for gamma correction.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: July 2, 2013
    Assignee: Himax Technologies Limited
    Inventor: Zong-Fu Hsieh
  • Patent number: 8451060
    Abstract: An amplifier device including a gain stage, an output stage, at least one phase compensation circuit and at least one coupling suppression device is provided. The gain stage has at least one feedback node. The output stage is coupled to the gain stage and has an output node for outputting an output voltage. Each of the at least one phase compensation circuit is coupled between a corresponding one of the at least one feedback node and the output node. Each of the at least one coupling suppression device is coupled between a corresponding one of the at least one feedback node and a respective coupling node, and is spontaneously turned on in response to a change of a voltage level at the corresponding feedback node when the corresponding feedback node is coupled by noise, thereby suppressing the change of the voltage level at the corresponding feedback node.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: May 28, 2013
    Assignee: Novatek Microelectronics Corp.
    Inventors: Ji-Ting Chen, Roger Randolph Wang
  • Publication number: 20130127541
    Abstract: An analog pre-distortion linearizer having predetermined gain and phase characteristics as a function of input RF signal power is disclosed. The linearizer comprises a core circuit comprising an input terminal configured to receive an input RF signal; an output terminal configured to provide a processed version of that signal; a transistor having a gate, a drain, and a source; and a feedback circuit, presenting an impedance at the frequency of the RF signal, connected to the transistor. The gate is connected to the input terminal and the drain is connected to the output terminal. First and second dc bias voltages applied to the gate and drain respectively cause the transistor to operate at a quiescent bias point in a saturated region of the transistor I-V plane. The quiescent bias point and the impedance are selected such that the linearizer has the predetermined gain and phase characteristics.
    Type: Application
    Filed: March 11, 2012
    Publication date: May 23, 2013
    Inventor: Chandra Khandavalli
  • Patent number: 8432226
    Abstract: An amplifier circuit has an input stage, a current mirror stage, and an output stage. The output stage has a transistor for which a non-linear and/or linear Miller capacitance exists across the transistor. A capacitive element, referred to herein as a “negative Miller capacitor,” is coupled between an input node of the current mirror stage and the transistor's collector or drain causing the current flowing through the negative Miller capacitor to be inverted, supplying the current taken by the usual Miller capacitance of the output stage. Thus, the negative Miller capacitor cancels the usual Miller capacitance across the transistor of the output stage, and such cancellation occurs without significantly increasing the amplifier's input power and costs. In some embodiments, both linear and non-linear components of the usual Miller capacitor are cancelled.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: April 30, 2013
    Assignee: ADTRAN, Inc.
    Inventor: Daniel M. Joffe
  • Patent number: 8395448
    Abstract: An amplifier circuit includes a first amplifier stage having a first output node; a second amplifier stage having a second output node; and a compensation block electrically coupled between the first and second output nodes. The compensation block has a compensation capacitor electrically coupled to the first node and electrically connectable to the second node, and has an impedance electrically connectable to the compensation capacitor. The compensation capacitor is electrically coupled via a switch to the impedance such that the compensation capacitor can contribute a zero to shunt branch formed by the compensation capacitor and impedance when the compensation capacitor is disconnected from the second node.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: March 12, 2013
    Assignee: Analog Devices, Inc.
    Inventors: Evgueni Ivanov, Arthur Kalb
  • Patent number: 8354887
    Abstract: In accordance with the teachings described herein, systems and methods are provided for charge compensation. A system may include an operational transconductance amplifier including an input terminal and an output terminal, a transistor network, and a capacitive circuit. The transistor network may be coupled in a feedback loop between the input terminal and the output terminal. The capacitive circuit may be configured to compensate a charge built on a parasitic capacitance of the transistor network during operation.
    Type: Grant
    Filed: May 17, 2011
    Date of Patent: January 15, 2013
    Assignee: Marvell International Ltd.
    Inventors: Hao Zhou, Yonghua Song, Jie Jiang, Tao Shui
  • Patent number: 8344808
    Abstract: Embodiments are directed to capacitance compensation via a compensation device coupled to a gain device to compensate for a capacitance change occurring due to an input signal change, along with a controller coupled to the compensation device to receive the input signal and to control an amount of compensation based on the input signal. In some embodiments, banks may be formed of multiple compensation devices, where each of the banks has a different size and is coupled to receive a different set of bias voltages.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: January 1, 2013
    Assignee: Javelin Semiconductor, Inc.
    Inventors: Anil Samavedam, David E. Bockelman, Vishnu Srinivasan, Eric Kimball
  • Publication number: 20120313711
    Abstract: The invention relates to a device for neutralizing a signal obtained by modulating, on to a high frequency carrier, a useful signal delivered by a system comprising a parasitic capacitance Cp that varies over time, the device comprising a neutralizing capacitance Cn, means for providing an adjustable gain G, said means being equipped with a JFET field-effect transistor (J1) equipped with a gate first electrode and drain and source second electrodes, and a control loop for providing gain G so that G×Cn permanently equals Cp by controlling the voltage on the gate first electrode of the transistor (J1). The neutralizing capacitance Cn comprises a first capacitor Cneutro1 and a second capacitor Cneutro2 placed in parallel at the output of said means for providing gain G.
    Type: Application
    Filed: June 7, 2012
    Publication date: December 13, 2012
    Applicant: THALES
    Inventor: Jean-Michel Muguet
  • Patent number: 8242840
    Abstract: A capacitive sensor amplifier circuit comprising: a capacitive sensor; a bias voltage supply connected across the capacitive sensor via a bias resistor; an operational amplifier having an input connected to the capacitive sensor; and a feedback capacitor connected between the input and an output of the amplifier, the input and output being of the same sign.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: August 14, 2012
    Assignee: NXP B.V.
    Inventor: Robert Hendrikus Margaretha Van Veldhoven
  • Patent number: 8193865
    Abstract: An output circuit includes an analog amplifier circuit including a differential amplifier stage configured to receive an input voltage, and first to nth output systems (n is a natural number more than 1); first to nth output nodes; an output pad; and first to nth electrostatic protection resistances. An ith output system (i is a natural number between 2 and n) of the first to nth output systems includes an ith PMOS transistor having a drain connected with the ith output node of the first to nth output nodes and a gate connected with a first output of the differential amplifier stage; and an ith NMOS transistor having a drain connected with the ith output node and a gate connected with a second output of the differential amplifier stage. The first to nth electrostatic protection resistances are respectively connected between the first to nth output nodes and the output pad.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: June 5, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Kouichi Nishimura
  • Patent number: 8174321
    Abstract: An amplifier circuit includes a first amplifier stage having a first output node; a second amplifier stage having a second output node; and a compensation block electrically coupled between the first and second output nodes. The compensation block has a compensation capacitor electrically coupled to the first node and electrically connectable to the second node, and has an impedance electrically connectable to the compensation capacitor. The compensation capacitor is electrically coupled via a switch to the impedance such that the compensation capacitor can contribute a zero to shunt branch formed by the compensation capacitor and impedance when the compensation capacitor is disconnected from the second node.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: May 8, 2012
    Assignee: Analog Devices, Inc.
    Inventors: Evgueni Ivanov, Arthur Kalb
  • Patent number: 8149054
    Abstract: An operational amplifier includes a differential amplifier input stage that supplies an operating current to a differential pair, the differential amplifier input stage including a first transistor having a first polarity, a push-pull amplifier output stage that includes a second transistor having the first polarity, and a third transistor having a second polarity, the second transistor and the third transistor being connected in series, and a capacitive element that connects a gate of the first transistor and a gate of the second transistor.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: April 3, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Masaki Shibuya
  • Patent number: 8081150
    Abstract: Provided is an output buffer for a source driver of an LCD with a high slew rate, and a method of controlling the output buffer. The output buffer, which outputs a source line driving signal for driving a source line of the LCD, includes: an amplifier section amplifying an analog image signal; an output section outputting the source line driving signal in response to a signal amplified by the amplifier section; and a slew rate controller section, setting a capacitance of a capacitor section to a first capacitance, during a first charge sharing period in which the source line is precharged to a first precharge voltage, setting the capacitance of the capacitor section to a second capacitance smaller than the first capacitance during a second charge sharing period in which the source line driving signal is supplied to the source line, and setting the capacitance of the capacitor section to the first capacitance while the source line driving signal is maintained after the second charge sharing period.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: December 20, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chang-Ho An
  • Patent number: 8072267
    Abstract: The present disclosure relates to phase margin modification in operational transconductance amplifiers.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: December 6, 2011
    Assignee: Infineon Technologies AG
    Inventor: Jose Luis Ceballos
  • Patent number: 8058931
    Abstract: An apparatus for an improved operational amplifier. The disclosed improved operational amplifier comprises an operational amplifier, a first feedback circuit, and one or more secondary feedback circuits. The operational amplifier include a plurality of serially coupled gain stages and is configured so that an output of each gain stage drives an input of a next gain stage and an output of a last gain stage drives a load external to the improved operational amplifier. The first feedback circuit is coupled between an output of a designated gain stage and an output of a previous gain stage to provide a first feedback to the previous gain stage. Each secondary feedback circuit provides an additional feedback to the output of the previous gain stage.
    Type: Grant
    Filed: April 27, 2010
    Date of Patent: November 15, 2011
    Assignee: Linear Technology Corporation
    Inventor: Ping Zhou
  • Patent number: 8058928
    Abstract: The present invention includes operational amplifier for an active pixel sensor that detects optical energy and generates an analog output that is proportional to the optical energy. The active pixel sensor operates in a number of different modes including: signal integration mode, the reset integration mode, column reset mode, and column signal readout mode. Each mode causes the operational amplifier to see a different output load. Accordingly, the operational amplifier includes a variable feedback circuit to provide compensation that provides sufficient amplifier stability for each operating mode of the active pixel sensor. For instance, the operational amplifier includes a bank of feedback capacitors, one or more of which are selected based on the operating mode to provide sufficient phase margin for stability, but also considering gain and bandwidth requirements of the operating mode.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: November 15, 2011
    Assignee: Broadcom Corporation
    Inventor: Esin Terzioglu
  • Patent number: 8054134
    Abstract: A coupling isolation method for preventing a load signal from coupling into an operational amplifier is disclosed. The coupling isolation method includes generating a system signal before the operational amplifier outputs a computation result, switching off a Miller compensation signal path of the operational amplifier at a first time point according to the system signal, and electrically connecting an output end of the operational amplifier and a load at a second time point according to the system signal to output the computation result.
    Type: Grant
    Filed: April 14, 2010
    Date of Patent: November 8, 2011
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Ju-Lin Huang, Chia-Wei Su, Po-Yu Tseng
  • Patent number: 8035450
    Abstract: An operational amplifier having a first amplification stage with an input terminal to receive a signal to be amplified, and a first output terminal, and a second amplification stage having a first input terminal connected to the first output terminal, and an output terminal to provide the amplified signal. The first and second amplification stages define, between the input terminal and the output terminal, a signal transfer function having first and second poles. The amplifier further includes a decoupling stage having a further input terminal connected to the first stage input terminal, and a further output terminal connected to the second stage output terminal. The decoupling stage is so arranged as to introduce at least one zero in the operational amplifier transfer function.
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: October 11, 2011
    Assignee: ST-Ericsson SA
    Inventors: Andrea Barbieri, Sergio Pernici, Germano Nicollini
  • Patent number: 7986188
    Abstract: A circuit includes a differential amplifier unit that receives an input signal at a non-inverting input thereof, a constant current source, a load circuit, an output transistor that receives an output of the differential amplifier unit as an input and drives a load circuit, a phase compensation circuit including a variable resistor and a capacitor connected in series between the input of the output transistor and a feedback path, an output current monitor circuit that detects an output current flowing through the output transistor, and a bias voltage generation circuit that varies a resistance value of the variable resistor in accordance with a result of the detection of the output current by the output current monitor circuit. A signal obtained by voltage dividing an output of the output transistor by resistors is supplied to an inverting input of the differential amplifier unit.
    Type: Grant
    Filed: April 2, 2010
    Date of Patent: July 26, 2011
    Assignee: Elpida Memory, Inc.
    Inventor: Atsushi Fujiwara
  • Patent number: 7986185
    Abstract: A rail-to-rail Miller compensation method without feed forward path includes forming a first compensation branch including a first amplifier, wherein an input of the first amplifier is electrically connected with an output of a second stage gain amplifier, the second stage gain amplifier is electrically connected the first stage gain amplifier in series forming an operational amplifier; and forming a second compensation branch including a second amplifier, wherein a dual relation is provided between an input stage of the first amplifier and that of the second amplifier, namely, if the input stage of the first amplifier is N-type, the input stage of the second amplifier is P-type, and vice versa. The present invention is capable of achieving the rail-to-rail output range without affecting the system stability. The N-type and P-type inputs are simultaneously applied to the input of the amplifier of the compensation branches.
    Type: Grant
    Filed: June 3, 2010
    Date of Patent: July 26, 2011
    Assignee: IPGoal Microelectronics (SiChuan) Co., Ltd.
    Inventor: Junwei Huang
  • Patent number: 7973605
    Abstract: A three-stage frequency-compensated operational amplifier includes a first-stage circuit, a second-stage circuit incorporated with a first compensation circuit, a third-stage circuit, and a second compensation circuit. The three-stage frequency-compensated operational amplifier functions as a two-stage operational amplifier at high frequencies, thereby capable of driving large capacitive loads with low power consumption.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: July 5, 2011
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventor: Uday Dasgupta