Abstract: An example apparatus can be a low voltage bandgap circuit that includes a bandgap core portion. The bandgap core portion includes an operational amplifier (op-amp). The op-amp includes a PMOS input and an NMOS input. Further, the op-amp is a folded cascode op-amp. The bandgap core portion further includes a first diode coupled to the op-amp. The bandgap core portion further includes a second diode coupled to the op-amp through a resistor.

Abstract: One example includes a device that is comprised of a pre-power amplifier, a power amplifier, a signal path, and a dynamic bias circuit. The pre-power amplifier amplifies an input signal and outputs a first amplified signal. The power amplifier receives the first amplified signal and amplifies the first amplified signal based on a dynamic bias signal to produce a second amplified signal at an output thereof. The signal path is coupled between an output of the pre-power amplifier and an input of the power amplifier. The dynamic bias circuit monitors the first amplified signal, generates the dynamic bias signal, and outputs the dynamic bias into the signal path.

Abstract: Described examples include Ethernet physical layer (PHY) interface integrated circuits with transmit interface circuitry for transmitting data to an Ethernet network through a magnetic interface, which includes a voltage mode first amplifier with an output that generates a first voltage signal from a supply voltage according to a data input signal. The transmit interface circuit also includes a feedforward second amplifier circuit with an output stage that operates in a first mode to generate a current signal from the supply voltage according to the first voltage signal and to provide the current signal to the first amplifier output to boost a peak voltage at the output above the supply voltage to facilitate support for higher peak signal voltage swings for 10Base-T applications while using 2.5 volt or other low voltage supply levels.

Abstract: A gate driver circuit drives a switching transistor. A variable current source generates a reference current configured to switch between a first current amount and a second current amount smaller than the first current amount. A current distribution circuit is configured to switch between a source enabled state in which a source current proportional to the reference current is sourced to a gate node of the switching transistor and a disabled state in which the source current is made equal to zero. A first transistor fixes the gate node of the switching transistor to a high voltage in an on-state of the first transistor. A second transistor fixes the gate node of the switching transistor to a low voltage in an on-state of the second transistor.

Abstract: An electronic device according to various embodiments of the disclosure includes a processor, a display panel that includes a plurality of pixels (the plurality of pixels include a first pixel and a second pixel), and a display driving circuit that drives the display panel and receives image data to be displayed through the display panel from the processor, and the display driving circuit is composed to identify output data of the first pixel and output data of the second pixel to display the image data, and, when the output data of the first pixel and the output data of the second pixel have more than a specified similarity, is composed to drive the first pixel and the second pixel by using a source amplifier specified in relation to the first pixel.

Abstract: Differential clamp circuits configured to recirculate the current in one clamp, either low-side clamp or high-side clamp, from one output of a differential signal to the other output of the differential signal are disclosed. Differential clamp circuits described herein may be particularly suitable for providing programmable clamps at differential outputs of an ADC driver and may be particularly beneficial to implement clamps that are symmetrical around an ADC's input common-mode voltage. Some differential clamp circuit described herein may advantageously present a smaller capacitive load at each output, thus reducing bandwidth degradation of the output stage. Furthermore, differential clamp circuits described herein may operate with only one control voltage, making it easier to limit the output excursions symmetrically around the default common-mode voltage.

Abstract: A pixel sensing device, an organic light emitting display device and a pixel compensation method thereof are disclosed. The pixel sensing device comprises a plurality of current integrators for sensing driving characteristics of pixels. Each current integrator comprises: an operational amplifier equipped with an inverting input terminal to which a first input voltage is applied according to a pixel current of the pixels, a non-inverting input terminal to which a second input voltage is applied according to the pixel current, and an output terminal through which an integral voltage corresponding to the pixel current is output; and a feedback capacitor connected between the inverting input terminal and the output terminal.

Abstract: An audio amplifier has an analog current source amplifier and a class D amplifier. The analog current source amplifier is active in a first mode to drive a speaker when an audio signal has smaller amplitude. The class D amplifier is active in a second mode to drive the speaker when the audio signal has larger amplitude. Other aspects are also described and claimed.

Abstract: A (pre) driver circuit includes first and second output terminals configured to be coupled to a power transistor. A differential stage has non-inverting and inverting inputs for receiving an input voltage. The input voltage is replicated as an output voltage across the first and second output terminals as a drive signal for the power transistor. The differential stage includes a differential transconductance amplifier in a voltage follower arrangement configured to provide continuous regulation of a voltage at the first output terminal with respect to the second output terminal.

Abstract: Provided is a compensation circuit for an operational amplifier including a primary pole. The compensation circuit includes: a control circuit; and a compensation capacitor including a first terminal connected to the primary pole, and a second terminal connected to an output terminal of the control circuit. The control circuit includes: a pull-up module including a control terminal connected to a second control signal terminal, an input terminal connected to an input power supply, and an output terminal connected to a first control node being the output terminal of the control circuit; a pull-down module including a control terminal connected to a first control signal terminal, and an output terminal connected to ground; and an input transistor including a control terminal connected to the primary pole, an input terminal connected to a first control node, and an output terminal connected to an input terminal of the pull-down module.

Abstract: A Miller compensation circuit includes: a differential amplifier having an inverse input end configured to receive an input signal; an output transistor having an output end connected to a positive input end of the differential amplifier, a first end connected to a first power supply, a second end connected to an output end of the differential amplifier, and a third end being a voltage output end and connected to the positive input end and a load; a Miller capacitor connected to the output end of the differential amplifier; a follower; and a current sampling circuit configured to sample a first current of the output transistor. The load is also connected to a second power supply.

Abstract: An exemplary improved ground for a power amplifier circuit may include structural separation of the drive amplifier and the power amplifier grounds and cut-off of the power amplifier induced feedback current to ensure stability under a wide-range of operating conditions. The exemplary power amplifier may include a first ground coupled to a first amplifier circuit, a second ground coupled to a second amplifier circuit separate from the first ground, and the first amplifier circuit generates a drive current for the second amplifier circuit.

Abstract: A small capacitance compensation network circuit, the first switch module (201) and the second switch (202) module are alternately switched between a switched-off state and a switched-on state, so that the compensation capacitor C3 is charged by the capacitor C1; and the third switch module (203) and the fourth switch module (204) are alternately switched between the switched-off state and the switched-on state, so that the compensation capacitor C3 is discharged to charge the capacitor C2, by controlling the alternate switch-on of the first switch module (201) and the second switch module (202), the third switch module (203) and the fourth switch module (204) causes the deviation of the capacitor C1 and the capacitor C2 to be processed and obtain the error signal.

Abstract: A method for phased array tapering includes setting a gain at a phase-invariant variable gain amplifier in each of a plurality of front-ends of a phased array transceiver to perform tapering of beam pattern side lobes. A resistance in the phase-invariant variable gain amplifier is set to provide a phase shift that is independent of gain.

Abstract: An amplifier includes an input terminal for receiving an input signal, an output terminal for outputting an output signal, a first transistor, a second transistor having a first terminal coupled to a second terminal of the first transistor, a third transistor having a first terminal coupled to a second terminal of the second transistor, a capacitor coupled between a control terminal and a second terminal of the third transistor, a bias circuit coupled to the first terminal of the third transistor for providing a bias voltage to the third transistor, a fourth transistor having a first terminal coupled to the input terminal and a second terminal coupled to the output terminal for providing a bypass path, and a fifth transistor having a first terminal coupled to the first terminal of the first transistor and a second terminal coupled to the output terminal.

Abstract: An amplifier includes an input node, an output node, a transistor and a transformer. The input node is configured to receive a first signal. The output node is configured to output an amplified first signal. The transistor includes a first terminal, a second terminal and a third terminal. The first terminal is coupled to the input node and a first supply voltage source. The second terminal is coupled to a second supply voltage source and the output node. The third terminal is coupled to a reference node. The transformer is coupled to the first terminal and the third terminal. The transistor is configured to operate in a sub-threshold region and a near-triode region.

Abstract: A CMOS cascode amplifier comprises a cascode circuit comprising a plurality of branches in parallel, each branch comprising a first transistor and a second switchable transistor connected in series forming a cascode pair, wherein the cascode circuit is configured to amplify an input signal. The CMOS cascode amplifier further comprises a bias circuit configured to bias the cascode circuit by providing a bias signal to the first transistor in each of the plurality of the branches in the cascode circuit. In addition, the CMOS cascode amplifier comprises a switching control circuit configured to control a quiescent current in the cascode circuit based on selectively activating the plurality of branches by providing a switching control signal that switches on the second switchable transistor in the one or more activated branches.

Abstract: A low-dropout voltage regulator includes a power transistor configured to receive an input voltage and to provide a regulated output voltage at an output voltage node. The power transistor includes a control electrode configured to receive a driver signal. A reference circuit is configured to generate a reference voltage. A feedback network is coupled to the power transistor and is configured to provide a first feedback signal and a second feedback signal. The first feedback signal represents the output voltage and the second feedback signal represents an output voltage gradient. An error amplifier is configured to receive the reference voltage and the first feedback signal representing the output voltage. The error amplifier is configured to generate the driver signal dependent on the reference voltage and the first feedback signal. The error amplifier includes an output stage that is biased with a bias current responsive to the second feedback signal.

Abstract: A current source for quickly adjusting an output current includes a constant current generation module, coupled to a control node, for generating a predefined current flowing through the control node in order to determine a voltage of the control node; a capacitor, coupled to an output terminal of the current source; a current variation detection module, coupled between the control node and the capacitor, for generating a variation on the voltage of the control node via the capacitor when the output terminal of the current source receives an instant current variation; and a trans-conductance amplifier, coupled between the control node and the output terminal, for changing a magnitude of the output current of the output terminal when the variation on the voltage of the control node is generated.

Abstract: An apparatus, which includes a first electronic device, a first nonlinear capacitance compensation circuit, and a capacitance compensation control circuit, is disclosed. The first electronic device has a first nonlinear capacitance and is coupled to the first nonlinear capacitance compensation circuit, which has a first compensation capacitance and receives a first compensation control signal. The capacitance compensation control circuit adjusts the first compensation capacitance using the first compensation control signal to at least partially linearize the first nonlinear capacitance.

Abstract: A probe system for registering a differential input signal has a first input network, which is supplied with a first component of the differential input signal in order to generate a first intermediate signal, and a second input network which is supplied with a second component of the differential input signal in order to generate a second intermediate signal. A differential amplifier for the amplification of the difference between the intermediate signals is arranged in the signal flow direction downstream of the input networks. At least one compensation network is used to compensate the influence of the input networks and is arranged at the output end of the differential amplifier or in a feedback path connecting an output to an input of the differential amplifier.

Abstract: This disclosure relates generally to radio frequency (RF) amplification devices and methods of operating the same. In one embodiment, an RF amplification device includes an RF amplification circuit and a stabilizing transformer network. The RF amplification circuit defines an RF signal path and is configured to amplify an RF signal propagating in the RF signal path. The stabilizing transformer network is operably associated with the RF signal path defined by the RF amplification circuit. Furthermore, the stabilizing transformer network is configured to reduce parasitic coupling along the RF signal path of the RF amplification circuit as the RF signal propagates in the RF signal path. In this manner, the stabilizing transformer network allows for inexpensive components to be used to reduce parasitic coupling while allowing for smaller distances along the RF signal path.

Abstract: In one aspect, a current source is provided to limit noise and offset. In one embodiment, a source transistor is provided, with current sourced at the drain. A feedback network runs from the source node to the gate. The feedback network produces voltage gain by a transconductance, such as a transistor. Appropriate capacitors are also provided, and two pairs of switches are disposed to provide offset cancellation by toggling between gain and clamp modes in the switched capacitor architecture.

Abstract: Systems and techniques are disclosed for configuring a circuit containing a two-stage amplifier including a first stage containing at least a differential amplifier, a second stage containing at least a transistor, and a sensing circuit configured to provide a gate voltage to a compensation component. The compensation component may be configured to connect the first stage and the second stage and to generate a lead-lag compensation. The compensation component may contain a compensation capacitor and a variable compensation resistive component in series connection with the compensation capacitor.

Abstract: A variable-gain current conveyor-based instrumentation amplifier without introducing distortion. An exemplary variable-gain instrumentation amplifier includes a first dual-output transconductance amplifier (DOTA) (i.e., current conveyor) that receives a first input voltage, a second DOTA that receives a second input voltage, a first resistive element connected between the first and second DOTA, an amplifier connected to the second DOTA at an inverting input, and a second resistive element that connects the second DOTA and the inverting input to an output of the amplifier. At least one of the resistive elements is a variable resistive element.

Abstract: An operational amplifier circuit including a main circuit, a compensation capacitor, a power circuit, and a set of switches is disclosed. The main circuit has an output terminal. The compensation capacitor has a first end connected to an internal node of the main circuit and a second end connected to the output terminal of the main circuit. The power circuit provides a current or a voltage as predetermined. The set of switches connects the power circuit to the compensation capacitor. When the main circuit is not in an output state, the set of switches is switched to allow the power circuit to provide the current or voltage to the compensation capacitor. When the main circuit is in the output state, the set of switches is switched to disconnect the power circuit from the compensation capacitor and allow the main circuit to return to an output circuit state and operate normally.

Abstract: Linearity and power efficiency in a power amplifier circuit are enhanced. The power amplifier circuit includes a first transistor that amplifies a signal input to the base and that outputs the amplified signal from the collector and a first capacitor that is disposed between the base and the collector of the first transistor and that has voltage dependency of a capacitance value lower than that of a base-collector parasitic capacitance value of the first transistor.

Abstract: A compensator circuit includes a first transconductance amplifier to convert an input voltage to a first output current. A second transconductance amplifier converts the input voltage to a second output current. A buffer includes an input and an output. The input of the buffer receives the second output current. A resistance is connected between an output of the first transconductance amplifier and an output of the buffer. A capacitance connected (i) between an output of the second transconductance amplifier and a terminal at a reference potential, and (ii) between the input of the buffer and the terminal. An output voltage of the compensator circuit is based on the first output current and is a voltage across the resistance, the buffer and the capacitance.

Abstract: A power combiner includes a primary winding and a secondary winding, wherein at least the primary winding comprises a center-tap; and a termination module operably coupled to the center-tapped primary winding and arranged to provide harmonic terminations on a plurality of frequencies. In addition, there is provided a radio frequency transmitter having a power combiner, where the power combiner includes a primary winding and a secondary winding, wherein at least the primary winding includes a center-tap; and a termination module operably coupled to the center-tapped primary winding and arranged to provide harmonic terminations on a plurality of frequencies.

Abstract: A three stage amplifier is provided and the three stage amplifier comprises a first gain stage, a second gain stage and a third gain stage wherein said first stage receives an amplifier input signal and said third gain stage outputs an amplifier output signal. The amplifier includes a feedback loop having a current buffer and a compensation capacitance provided from the output of said third gain stage to the output of the first gain stage. In addition, an active left half plane zero stage is embedded in said feedback loop for cancelling a parasitic pole of said feedback loop.

Abstract: Embodiments are directed to capacitance compensation via a compensation device coupled to a gain device to compensate for a capacitance change occurring due to an input signal change, along with a controller coupled to the compensation device to receive the input signal and to control an amount of compensation based on the input signal. In some embodiments, banks may be formed of multiple compensation devices, where each of the banks has a different size and is coupled to receive a different set of bias voltages.

Abstract: An operational amplifier (10) capable of driving a capacitive load (CLOAD) and/or a resistive load (RLOAD) includes a first gain stage (2) having an output coupled to a high impedance node (3) and a second gain stage (5) having an input coupled to the first high impedance node. A gain reduction resistor (RD) and an AC coupling capacitor (CD) are coupled in series between the high impedance node and a reference voltage. A Miller feedback capacitor (CM) is coupled between an output conductor (7) of the second gain stage and the high impedance node. The output of the second gain stage may be coupled to the high impedance node by a cascode transistor (MCASCODE).

Abstract: Amplifier circuits and methods of cancelling the Miller effects in amplifiers are disclosed herein. An embodiment of an amplifier circuit includes an input and an output. An amplifier is connected between the input and the output of the circuit. A voltage source is connected to the output, wherein the voltage source output is one hundred eighty degrees out of phase with the voltage output by the amplifier, and wherein the voltage source cancels gain due to the Miller effect of a Miller capacitance between the input and output.

Abstract: A DC-DC converter converts an input voltage input from an input terminal to a predetermined voltage and outputs the converted voltage from an output terminal, the DC-DC converter including an output control transistor and an operation control circuit that has an error amplifying circuit, whereby the error amplifying circuit includes an output circuit configured to output an error voltage and include an output transistor of a source follower connection, a series circuit configured to include a resistor for phase compensation and a capacitor for phase compensation and be connected between a control electrode of the output circuit and a grounding voltage terminal, and an amplifying circuit configured to be positioned on a side more distant from a side outputting the error voltage relative to the output circuit in the error amplifying circuit, and include a voltage generating element as a load of the amplifying circuit.

Abstract: In one implementation, a power amplifier may include a gain device to receive an input signal and to output an amplified signal, and a compensation device coupled to the gain device to compensate for a change in a capacitance of the gain device occurring due to a change in the input signal. The power amplifier may be formed using a complementary metal oxide semiconductor (CMOS) process.

Abstract: Techniques for reducing undesired source degeneration inductance are disclosed. In an exemplary design, an apparatus includes first and second connections. The first connection includes a first parasitic inductance acting as a source degeneration inductance of an amplifier. The second connection includes a second parasitic inductance magnetically coupled to the first parasitic inductance to reduce the source degeneration inductance of the amplifier. The amplifier (e.g., a single-ended power amplifier) may be coupled to circuit ground via the first connection. An impedance matching circuit may be coupled to the amplifier and may include a circuit component coupled to circuit ground via the second connection. The first connection may be located sufficiently close to (e.g., within a predetermined distance of) the second connection in order to obtain the desired magnetic coupling between the first and second parasitic inductances.

Abstract: An operational amplifier includes an operational amplifier circuit having at least one output node and an output stage coupled to the output node, the output stage containing an output and first MOS transistor employed in a common source amplifier mode, a frequency compensation capacitor coupled between the output of the output stage and the gate of the first transistor circuit by means of a second MOS transistor employed in a common gate amplifier mode. The other node of the capacitor and the output of the output stage are coupled to the amplifier output node with a resistor.

Abstract: Compensation methods and systems for voltage-feedback amplifiers provide improved dynamic performance (i.e., increased bandwidth and the elimination or alleviation of a slew limitation) at high gains by direct feedback of an AC signal (i.e., an intermediate voltage) to an amplifier input without being attenuated by feedback resistor network.

Abstract: The invention relates to a device for neutralizing a signal obtained by modulating, on to a high frequency carrier, a useful signal delivered by a system comprising a parasitic capacitance Cp that varies over time, the device comprising a neutralizing capacitance Cn, means for providing an adjustable gain G, said means being equipped with a JFET field-effect transistor (J1) equipped with a gate first electrode and drain and source second electrodes, and a control loop for providing gain G so that G×Cn permanently equals Cp by controlling the voltage on the gate first electrode of the transistor (J1). The neutralizing capacitance Cn comprises a first capacitor Cneutro1 and a second capacitor Cneutro2 placed in parallel at the output of said means for providing gain G.

Abstract: The present invention relates to a device for neutralization of a signal obtained by transposition to a high frequency of a useful signal supplied by a unit of equipment, the said equipment having a spurious capacitance Cparasite that varies over time. The device comprises a neutralization capacitance Cneut and means with adjustable gain G, together with means for feedback controlling the gain G in such a manner that, continuously, G×Cneut=Cparasite.

Abstract: An impedance-matched amplifier utilizing a feed-forward linearization technique involving multiple negative feedbacks and distortion compensation without active tail current sources reduces noise, distortion, power consumption and heat dissipation requirements and increases linearity, dynamic range, signal-to-noise-ratio, sensitivity and quality of service. Some differential amplifier embodiments of the invention consume less than 2 mA at 5 Volts or 10 mW power consumption per 1 mW in peak and sustained output IP3 performance above 40 dBm. In contrast, for an input signal frequency of 200 MHz, a 16 dB gain state-of-the-art differential amplifier consumes 100 mA at 5 Volts with a peak output IP3 of 36 dBm while an implementation of a 16 dB gain differential amplifier embodying the invention consumes 77.7 mA at 5 Volts with a peak output IP3 of 46 dBm and sustained at or above 40 dBm over a wide frequency range.

Abstract: An analog pre-distortion linearizer having predetermined gain and phase characteristics as a function of input RF signal power is disclosed. The linearizer comprises a core circuit comprising an input terminal configured to receive an input RF signal; an output terminal configured to provide a processed version of that signal; a transistor having a gate, a drain, and a source; and a feedback circuit, presenting an impedance at the frequency of the RF signal, connected to the transistor. The gate is connected to the input terminal and the drain is connected to the output terminal. First and second dc bias voltages applied to the gate and drain respectively cause the transistor to operate at a quiescent bias point in a saturated region of the transistor I-V plane. The quiescent bias point and the impedance are selected such that the linearizer has the predetermined gain and phase characteristics.

Abstract: An operational amplifying device comprises an input stage and an output stage. The input stage receives and processes an input voltage to output an amplified voltage. The output stage is electrically connected to the input stage in series. The output stage comprises a first switch and a second switch. The first switch is configured to turn on for transferring the amplified voltage. The second switch is connected in parallel with the first switch and is configured to turn on for transferring the amplified voltage. The second switch is turned off when the first switch is turned on such that the amplified voltage is transferred through the first switch to the first resistor array for gamma correction.

Abstract: An amplifier device including a gain stage, an output stage, at least one phase compensation circuit and at least one coupling suppression device is provided. The gain stage has at least one feedback node. The output stage is coupled to the gain stage and has an output node for outputting an output voltage. Each of the at least one phase compensation circuit is coupled between a corresponding one of the at least one feedback node and the output node. Each of the at least one coupling suppression device is coupled between a corresponding one of the at least one feedback node and a respective coupling node, and is spontaneously turned on in response to a change of a voltage level at the corresponding feedback node when the corresponding feedback node is coupled by noise, thereby suppressing the change of the voltage level at the corresponding feedback node.

Abstract: An analog pre-distortion linearizer having predetermined gain and phase characteristics as a function of input RF signal power is disclosed. The linearizer comprises a core circuit comprising an input terminal configured to receive an input RF signal; an output terminal configured to provide a processed version of that signal; a transistor having a gate, a drain, and a source; and a feedback circuit, presenting an impedance at the frequency of the RF signal, connected to the transistor. The gate is connected to the input terminal and the drain is connected to the output terminal. First and second dc bias voltages applied to the gate and drain respectively cause the transistor to operate at a quiescent bias point in a saturated region of the transistor I-V plane. The quiescent bias point and the impedance are selected such that the linearizer has the predetermined gain and phase characteristics.

Abstract: An amplifier circuit has an input stage, a current mirror stage, and an output stage. The output stage has a transistor for which a non-linear and/or linear Miller capacitance exists across the transistor. A capacitive element, referred to herein as a “negative Miller capacitor,” is coupled between an input node of the current mirror stage and the transistor's collector or drain causing the current flowing through the negative Miller capacitor to be inverted, supplying the current taken by the usual Miller capacitance of the output stage. Thus, the negative Miller capacitor cancels the usual Miller capacitance across the transistor of the output stage, and such cancellation occurs without significantly increasing the amplifier's input power and costs. In some embodiments, both linear and non-linear components of the usual Miller capacitor are cancelled.

Abstract: An amplifier circuit includes a first amplifier stage having a first output node; a second amplifier stage having a second output node; and a compensation block electrically coupled between the first and second output nodes. The compensation block has a compensation capacitor electrically coupled to the first node and electrically connectable to the second node, and has an impedance electrically connectable to the compensation capacitor. The compensation capacitor is electrically coupled via a switch to the impedance such that the compensation capacitor can contribute a zero to shunt branch formed by the compensation capacitor and impedance when the compensation capacitor is disconnected from the second node.

Abstract: In accordance with the teachings described herein, systems and methods are provided for charge compensation. A system may include an operational transconductance amplifier including an input terminal and an output terminal, a transistor network, and a capacitive circuit. The transistor network may be coupled in a feedback loop between the input terminal and the output terminal. The capacitive circuit may be configured to compensate a charge built on a parasitic capacitance of the transistor network during operation.

Abstract: Embodiments are directed to capacitance compensation via a compensation device coupled to a gain device to compensate for a capacitance change occurring due to an input signal change, along with a controller coupled to the compensation device to receive the input signal and to control an amount of compensation based on the input signal. In some embodiments, banks may be formed of multiple compensation devices, where each of the banks has a different size and is coupled to receive a different set of bias voltages.

Abstract: The invention relates to a device for neutralizing a signal obtained by modulating, on to a high frequency carrier, a useful signal delivered by a system comprising a parasitic capacitance Cp that varies over time, the device comprising a neutralizing capacitance Cn, means for providing an adjustable gain G, said means being equipped with a JFET field-effect transistor (J1) equipped with a gate first electrode and drain and source second electrodes, and a control loop for providing gain G so that G×Cn permanently equals Cp by controlling the voltage on the gate first electrode of the transistor (J1). The neutralizing capacitance Cn comprises a first capacitor Cneutro1 and a second capacitor Cneutro2 placed in parallel at the output of said means for providing gain G.