Abstract: Described are a circuit and system to provide an output signal in response to composite input signal comprising an AC signal component and a DC signal component. An amplifier provides an amplified voltage signal in response to a voltage representative of the composite signal. A filter may provide a filtered voltage signal having a magnitude that is representative of a magnitude of the DC signal component in response to the amplified voltage signal. A DC signal removal circuit may substantially remove at least a portion of the DC signal component from an input terminal in response filtered voltage signal.

Abstract: Voltage regulators use capacitors to compensate the voltage regulator and provide stable performance. Capacitors have an inherent equivalent series resistance (ESR) that changes over various operating conditions including signal frequency, operating temperature as well as others. An apparatus and method compensates for the low ESR of capacitors to increase the total equivalent series resistance of the capacitor. By providing an “on-chip” resistance between the capacitor and the circuit ground potential, minimum total ESR can be provided such that stable load regulation is achieved with capacitors that would otherwise be undesirable for such use. Increasing the value of the output capacitor's equivalent series resistance allows wider ranging values of capacitance to be used. The increased range of capacitance values allows capacitors of different material types to be used.

Abstract: A Miller-compensated amplifier circuit. The circuit includes an amplifier stage, and a compensation capacitor arranged in parallel with the amplifier stage. A current multiplier circuit path, adapted to multiply a current through the compensation capacitor, includes an inversion stage in the current multiplier circuit path. The inversion stage includes a first current mirror adapted to mirror a first current corresponding to a current through the compensation capacitor, to provide a second current, as well as a second current mirror adapted to mirror and invert the second current to provide a third current and to apply the third current to the amplifier stage. In this way, the circuit is Miller compensated by only a single capacitor that has its capacitance multiplied in accordance with current-mode multiplication.

Abstract: The present invention discloses a new family of switching amplifier classes called “class E/F amplifiers.” These amplifiers are generally characterized by their use of the zero-voltage-switching (ZVS) phase correction technique to eliminate of the loss normally associated with the inherent capacitance of the switching device as utilized in class-E amplifiers, together with a load network for improved voltage and current wave-shaping by presenting class-F−1 impedances at selected overtones and class-E impedances at the remaining overtones. The present invention discloses a several topologies and specific circuit implementations for achieving such performance.

Abstract: The gain-bandwidth (GBW) limitation problem inherent in all amplifiers is overcome to provide wideband amplifiers with specified characteristics for the transfer function. Parasitic capacitances of transistors are absorbed or incorporated into the design of the passive networks, which are inserted between the gain stages of the amplifier. The component values are determined based on conventional low-pass filter structures. A prototype CMOS transimpedance amplifier implemented using the developed technique achieves over 9 GHz bandwidth and 54 dB transimpedance gain from a 0.5 pF photo-diode capacitance.

Abstract: Techniques for performing frequency compensation of common-mode feedback loops for differential amplifiers are disclosed.

Abstract: A folded-cascode amplifier is arranged with a differential pair circuit, a current mirror circuit, and a cascode circuit. The differential pair is coupled to the current mirror circuit, while the cascode circuit is only coupled to one half of the current mirror circuit. A minimum number of transistors are employed such that overall speed is improved. An output stage with a compensation circuit may be coupled to an output of the cascode circuit. The cascode circuit is configured such that the compensation capacitor is driven with a current of approximately +/−2*I when slewing in the positive and negative directions.

Abstract: The invention relates to an amplifier circuit (20) and a method for reducing stray feedback, wherein an additional feedback compensation terminal is provided at the output of the amplifier circuit. A predetermined fraction of the output signal of the amplifier circuit is output at the feedback compensation terminal (RFB) so as to reduce the stray feedback of the output signal. The feedback compensation terminal (RFB) enables a reduction of the stray feedback by providing an additional stray feedback signal which is negatively added at the input of the amplifier circuit (20) to thereby reduce overall stray feedback. The gain may be adjusted once during manufacturing, or each time when operation of the device is initiated. The amplifier circuit (20) may be a transimpedance amplifier for use in a read head of a reproducing device for a record carrier.

Abstract: A Miller-compensated amplifier circuit. The circuit includes an amplifier stage, and a compensation capacitor arranged in parallel with the amplifier stage. A current multiplier circuit path, adapted to multiply a current through the compensation capacitor, includes an inversion stage in the current multiplier circuit path. In this way, the circuit is Miller compensated by only a single capacitor that has its capacitance multiplied in accordance with current-mode multiplication.

Abstract: The amplifier circuit includes at least one amplification branch having an input transistor, an output transistor, having a source terminal connected to the input terminal and a drain terminal connected to a first output terminal, and a gain raising stage, having an input and an output connected to the source terminal and, respectively, to a gate terminal of the output transistor. The amplifier circuit includes, moreover, a compensation capacitor connected between the gate terminal and the drain terminal of the output transistor.

Abstract: A low noise differential amplifier structure comprising a first amplifier provided with an output stage with a Miller capacitor having a first electrode and a second electrode connected to the input and the output of the output stage, respectively. A second amplifier is provided with an output stage with a Miller capacitor having a first electrode and a second electrode connected to the input and the output of the output stage, respectively. The structure is characterized in that it comprises: at least a first trimming capacitor having a first electrode connected to the first electrode of the first Miller capacitor; at least a second trimming capacitor having a first electrode connected to the first electrode of the second Miller capacitor; and a cascode stage having an input receiving the output common mode voltage and an output connected to the second electrode of the first and second trimming capacitors.

Abstract: A Miller de-compensation technique and circuit is provided for a differential input, differential output (DIDO) amplifier that facilitates increased differential mode bandwidth while maintaining common-mode and differential mode stability. An exemplary differential input, differential output (DIDO) amplifier comprises a pair of op amps having a compensation capacitance circuit. The compensation capacitance circuit is configured to distinguish between differential mode signals and common mode signals, and to reduce the effects of compensation capacitance during differential mode operation, but allow the effects of compensation capacitance to remain present during common mode operation. As a result, the amount of compensation capacitance can be configured such that common mode stability can be maintained without reducing differential mode bandwidth. The DIDO amplifier can be configured as a programmable gain amplifier or a fixed gain amplifier.

Abstract: Techniques for performing frequency compensation of common-mode feedback loops for differential amplifiers are disclosed.

Abstract: The present invention discloses a new family of switching amplifier classes called “class E/F amplifiers.” These amplifiers are generally characterized by their use of the zero-voltage-switching (ZVS) phase correction technique to eliminate of the loss normally associated with the inherent capacitance of the switching device as utilized in class-E amplifiers, together with a load network for improved voltage and current wave-shaping by presenting class-F−1 impedances at selected overtones and class-E impedances at the remaining overtones. The present invention discloses a several topologies and specific circuit implementations for achieving such performance.

Abstract: A wideband differential amplifier includes a first differential stage connected to a Miller stage allowing an open-loop gain increase. The Miller stage includes a current source and a resistive-capacitive network causing a feedback into the current source. The feedback includes a portion of a Miller stage output signal having a high frequency range to move a bias point of the current source within the high frequency range. Thus, a gain of the Miller stage significantly increases towards the bias point.

Abstract: An amplifier is configured to provide both common-mode and differential-mode compensation to ensure stability in telecommunications circuits or other circuits where both common mode and differential mode signal paths are provided. The amplifier includes two interconnected operational amplifiers AMPA and AMPB. Common mode compensation is provided by connecting one or more capacitors with a total value CCOMMON connected from a gain node at the input of an inverter in one of the amplifiers AMPA or AMPB to the output of the inverter in the other amplifier. Differential mode compensation can be provided by connecting a capacitor with value CCOMP at the gain node of each of the amplifiers AMPA or AMPB. Alternatively, both differential mode and Miller effect compensation can be provided by connecting one or more capacitors with total value CCOMP from the input to the output of components forming the inverter in each of the amplifiers AMPA and AMPB.

Abstract: Expansion of the bandwidth of a wideband CMOS data amplifier is accomplished using various combinations of shunt peaking, series peaking, and miller capacitance cancellation. These various combinations are employed in any of the amplifier input stage, in intermediate stages, or in the last stage.

Abstract: A pole and zero circuit for changing the position of a pole, or a zero, of an amplifier including a capacitor to change the position of the pole or zero for the amplifier, a first current path for the capacitor, a variable impedance device in the first current path to connect the capacitor to the amplifier, and a current source to control the impedance of the variable impedance device.

Abstract: A cascode amplifier integrated circuit (IC) with frequency compensation capability that possesses a tight overall variation in transient rise and fall time, is relatively small in size and has a relatively high RC series circuit breakdown voltage. The cascode amplifier IC includes an input bias terminal configured to receive a bias voltage Vb, a power supply input terminal configured to receive a power supply voltage Vcc, an input signal terminal configured to receive an input voltage signal Vin, and an output signal terminal. The cascode amplifier IC also includes a gain stage circuit, an output buffer stage circuit and a resistance-capacitance (RC) series circuit configured to provide frequency compensation during operation of the cascode amplifier IC. The RC series circuit has a peaking bipolar transistor configured to provide a bipolar junction peaking capacitance between the output signal terminal and the gain stage circuit.

Abstract: An output distortion correction amplifier system includes an input stage; a current mirror connected to the input stage; an output stage having its input connected to the input stage and a current mirror and its output connected to the input stage; a compensation impedance connected to the input of the output stage; and a distortion correction circuit for directly sensing the distortion voltage across the output stage and providing to the current mirror a current representative of the distortion voltage for delivering to the compensation impedance a correction current to develop a correction voltage at the input of the output stage to nullify the effect of the distortion voltage.

Abstract: Provided a method of reducing impedance variations in an electrical circuit structured and arranged for placement on an integrated circuit (IC) substrate. The method includes forming sets of parallel connected resistors, each set corresponding to one of the impedance devices on the IC. Each set also includes two or more parallel resistor paths, each resistor path including two or more cascaded resistors and has a total impedance value substantially equal to the predetermined impedance value of its corresponding impedance device. Finally, the method includes configuring the sets of parallel resistor paths to form an interdigital structure across the substrate when the electrical circuit is placed on the IC.

Abstract: To an existing class AB amplifier receiving at a gate of one of a NMOS or a PMOS type CMOS transistor an input signal, the gate of this CMOS transistor having a nonlinear gate capacitance with its switched operation, is added another, opposite-type, one of a NMOS or a PMOS type CMOS transistor that also receives at its gate the same input signal. The nonlinear gate capacitance of this other CMOS transistor is essentially opposite to the nonlinear gate capacitance of the existing CMOS transistor that receives the input signal within the class AB amplifier. This other transistor serves to compensate for the nonlinear gate capacitance of the existing CMOS transistor. Any nonlinearity due, in particular, to any nonlinear change in gate capacitance of a CMOS transistor that is used in particular within a class AB amplifier is thus substantially canceled.

Abstract: Band pass amplifiers and methods for driving the same are described. According to one embodiment, a frequency selective network is provided in a feedback loop. An analog-to-digital converter is coupled to the frequency selective network. A switching stage is coupled to the analog-to-digital converter for producing a continuous-time output signal. The switching stage includes at least one resonance circuit configured to resonate at a resonance frequency and thereby generate at least a portion of the continuous-time output signal. A continuous-time feedback path continuously senses and feeds back the continuous-time output signal to the frequency selective network.

Abstract: An operational amplifier having a low impedance input and a high current gain output. The operational amplifier comprises: 1) a first N-channel transistor having a source coupled to the low impedance input of the operational amplifier; 2) a first constant current source coupled between the source of the first N-channel transistor and ground; 3) a first amplifier stage having an input coupled to the first N-channel transistor source and an inverting output coupled to a gate of the first N-channel transistor; 4) a second amplifier stage having an input coupled to a drain of the first N-channel transistor and an output coupled to the high current gain output of the operational amplifier; and 5) an internal compensation capacitor coupled between the input and the output of the second amplifier stage.

Abstract: Expansion of the bandwidth of a wideband CMOS data amplifier is accomplished using various combinations of shunt peaking, series peaking, and miller capacitance cancellation. These various combinations are employed in any of the amplifier input stage, in intermediate stages, or in the last stage.

Abstract: A frequency compensation circuit includes a first and a second compensation capacitor for a frequency-compensated amplifier to which a chopped useful signal can be supplied. In a first clock phase, the useful signal is respectively supplied to the first compensation capacitor, and in a second clock phase the useful signal is respectively supplied to the second compensation capacitor. As a result, a stable, frequency-compensated amplifier is specified in which charge reversal in the frequency compensation capacitors or Miller capacitors is avoided, making possible a configuration with a small chip area. The principle is suited particularly to Hall sensors operated in chopped mode.

Abstract: A circuit for splitting poles between a first stage and a second inverting voltage-amplifier stage of an electronic circuit, comprises, in series between the output of the first stage and the output of the second stage, and in that order, a first capacitor, a second capacitor and a resistor. The circuit further comprises a voltage-divider bridge which is connected between a terminal delivering a substantially constant voltage and the output of the first stage. The output of the voltage-divider bridge is linked to the common node between the first capacitor and the second capacitor, in such a way that a first resistor of the voltage-divider bridge is connected in parallel with the first capacitor.

Abstract: A method to increase the bandwidth of a transimpedance amplifier using capactive feedback. The resultant amplifier maintains wide bandwidth, high linearity, low noise, and low input impedance independent of component variations. These characteristics greatly facilitate the economical measurement of small currents such as those arising from photodiodes and biological preparations.

Abstract: An output stage for an operational amplifier includes a dynamically activated CMOS drive circuit that is arranged to improve the drive characteristics of the operational amplifier. The output stage includes bipolar transistors that are arranged to clamp the signal swing at an intermediary node in the operational amplifier. The bipolar transistors activate respective portions of the CMOS drive circuit based on the signal drive at the intermediary node. The CMOS driver circuit includes a p-type field effect transistor that sources additional current into the output signal when active, and an n-type field effect transistor that sinks additional current from the output terminal when active. The output stage may include additional circuitry to ensure that parasitic capacitances associated with the gates of the p-type field effect transistor and the n-type field effect transistors are discharged at appropriate times such that power consumption is reduced and high-speed operation is enhanced.

Abstract: There is disclosed high-speed current-mirror circuitry and methods of operating the same. An exemplary impedance-peaking current mirror comprises a N-channel drive transistor and a N-channel mirror transistor. The N-channel drive transistor has a source coupled to ground, a drain coupled to a current source and a gate coupled to the drain via a series connection of a resistor and an inductor. The N-channel mirror transistor has a source coupled to ground, a gate coupled to the drain of the N-channel drive transistor, and a drain coupled to a positive power supply via an impedance load.

Abstract: An operational amplifier circuit includes a differential section, an output section having drive transistors PT15 and NT15, a voltage setting circuit which sets a programming voltage at a node N1, and a capacitance element C1. The programming voltage is set to the node N1, and then a change in voltage at an output node NQ1 of the differential section is transferred to the node N1 by the capacitance element C1. Switching elements SW1 and SW2 are turned off before the programming voltage is set to the node N1, and are turned on after the setting. A switching element SW4 is turned on and the node N1 is set to VSS, and subsequently the node N1 is set to the programming voltage (VDD−VTH) by turning on the switching element SW3. The programming voltage is set in a switching period between scan periods.

Abstract: An input distortion correction current-feedback amplifier system includes a current mirror; an input stage connected to the input of the current mirror; an output stage connected to the output of the current mirror; a feedback circuit connected from the output stage to the input stage; a compensation impedance connected to the output of the current mirror; and a distortion correction circuit for sensing the distortion voltage across the input stage and providing to the current mirror a current representative of the distortion voltage for delivering to the compensation impedance a correction current to develop a correction voltage at the input of the output stage to nullify the effect of the distortion voltage.

Abstract: A circuit for a variable gain amplifier is disclosed that uses two differential gain stages with independently adjustable bias currents. By changing the bias currents of the gain stages, the overall gain and phase of the amplifier can be adjusted over a wide range. Neither in-series nor in-parallel circuitry is required to implement or perform gain control. In addition to minimal part requirements for mechanization, the present invention features low power supply requirements while maintaining a wide operational bandwidth.

Abstract: A voltage buffer and follower includes a single ended output, a source follower, and a current feedback loop. The current feedback loop is coupled to the source follower and to the single ended output. When two voltage followers are used in a differential configuration, the voltage followers can become part of a high bandwidth gain cell. The high bandwidth gain cell includes a first and a second source follower circuit that are coupled to the first and the second current feedback loops, respectively. The first and the second source follower circuits are further coupled to a first and a second current mirror circuit, respectively. The first and second current mirror circuits are coupled to a load, which is coupled to a common-mode feedback circuit. The common-mode feedback circuit controls a constant current source that sinks mirrored direct currents that flow through the first and the second current mirror circuits.

Abstract: An amplifier with Miller-effect frequency compensation in which the Miller feedback capacitor is connected to an internal terminal of the amplifier having a low impedance, and shunt compensation circuitry is connected to an intermediate signal terminal that drives the output amplifier stage. The compensation circuitry, which includes serially coupled capacitive and resistive circuit elements, introduces a high frequency zero to cancel one of the high frequency complex poles introduced by the Miller feedback capacitor connection.

Abstract: An operational amplifier for a pipeline analog-to-digital converter (ADC). The operational amplifier includes a cascaded chain of differential amplifiers, each differential amplifier including resistive-averaged common mode feedback to produce a common mode voltage for the differential amplifier, a particular differential amplifier of the chain having the highest gain of the gains of the differential amplifiers. The operational amplifier has one or more feedback paths each including a compensation capacitor to compensate the operational amplifier.

Abstract: A cascode amplifier includes a cascode input stage that provides a first current in response to an input signal. A second current is also provided in response to the input signal, where the second current is a scaled and smaller version of the first current. The second current is low-pass filtered using parasitic capacitance present in a current mirror. A delayed mirrored current is applied to the emitters of the lower cascode transistor circuit to provide negative feedback. The current mirror amplifies the effect of the parasitic capacitance in the low-pass filter. An output node of the cascode amplifier has an associated parasitic capacitance. The parasitic capacitance at the output node in the cascode amplifier is compensated for by proper arrangement of the parasitic capacitance in the current mirror, such that the cascode amplifier is useful at higher frequencies. The improved cascode amplifier is suitable for monolithic integration.

Abstract: An operational amplifier (op-amp) having a stage in parallel, dummy stage (212), with a final output stage (208) coupled to an initial stage (206). The dummy stage provides a desired Miller capacitance to the initial stage to isolates noise coupling between the power supply (214) and the output (204) and to improve the stability of the op-amp. By providing the dummy stage, the total capacitance required to achieve the desired noise isolation and stability is reduced thereby reducing the area required to implement the op-amp on an integrated circuit die.

Abstract: A frequency compensation circuit includes a first and a second compensation capacitor for a frequency-compensated amplifier to which a chopped useful signal can be supplied. In a first clock phase, the useful signal is respectively supplied to the first compensation capacitor, and in a second clock phase the useful signal is respectively supplied to the second compensation capacitor. As a result, a stable, frequency-compensated amplifier is specified in which charge reversal in the frequency compensation capacitors or Miller capacitors is avoided, making possible a configuration with a small chip area. The principle is suited particularly to Hall sensors operated in chopped mode.

Abstract: A method and circuitry for implementing programmable gain. More particularly, embodiments of the present invention provide an amplifier circuit which can be used as a CDS-amp or an instrumentation amplifier. Included is a two-stage amplifier, each stage having a few as one transistor. A current source biases one stage of the two-stage amplifier. A load resistor network couples to the two-stage amplifier and is configured to set gain values for the two-stage amplifier.

Abstract: A high-frequency power amplifier capable of considerably improving the power amplification efficiency (&eegr;). This high-frequency power amplifier 10 comprises an amplifying element 11, an input-side matching circuit 12, and an output-side matching circuit 13, and further has a current absorbing unit 20. This current absorbing unit 20 absorbs the current of a higher-harmonic frequency current contained in a signal of a fundamental wave at which the amplifying element 11 operates. Preferably, this current absorbing unit 20 is comprised of an LC-series resonance circuit 21 having a higher-harmonic frequency as a resonance frequency, and thereby bypasses the above current to the earth.

Abstract: A transconductance amplifier and method for improving the phase response and linearity. A differential amplifier circuit receives differential signals for amplification on respective bases of input bipolar transistors. The transistors amplify a small signal received on the based connections to produce an amplified output current. The differential amplifier circuit is connected to load impedances which form a cascode transconductance amplifier output stage. Feedback transistors provide a feedback voltage from the emitters of each of the different bipolar transistors to the base, improving the linearity of the differential amplifier. Phase compensation is provided by cross coupling through first and second capacitors a portion of each individual differential signal component to the base connections of the differential amplifier input transistor.

Abstract: An embodiment of an amplifier circuit including a power supply node and an output node is adapted to provide, during operation, an output node voltage ranging to within 0.2 volts of a power supply voltage used during the operation. An embodiment of the circuit includes a differential first stage coupled to the power supply node and providing a pair of first stage outputs for coupling to a differential second stage. In a method of providing an output voltage near the power supply voltage of an amplifier, a first stage output voltage ranging to within a transistor turn-on voltage of the power supply voltage is produced. The first stage output voltage may further be coupled to a second stage of the amplifier, where the coupling may modulate a current flow through a first pair of cascaded transistors. An output node of the amplifier may be arranged between the pair of transistors and the power supply voltage node.

Abstract: A high gain amplifier includes a differential amplifier stage having a pair of transistors; first and second input circuits for providing input signals to the pair of transistors; transistor means arranged as a differential-to-single-ended converter driven by the differential amplifier stage to provide a single ended output signal; an intermediate gain stage having an input responsive to the single ended output signal; bias means for the differential amplifier, the bias means including circuit means for maintaining the currents through the pair of transistors in constant ratio independently of changes in load at the intermediate gain stage; and an inverting gain output stage driven by the intermediate gain stage and having an output for driving a load substantially from rail to rail. Also disclosed is a frequency compensation capacitor circuit connected between the input of the intermediate gain stage and the output of the inverting gain output stage.

Abstract: Constant GM models and GM-controlled current-isolated indirect-feedback instrumentation amplifiers. The constant GM models provide a transconductance that is proportional to the inverse of a resistance in the constant GM model circuits over a wide range of common mode and differential mode inputs. Current-isolated indirect-feedback instrumentation amplifiers using constant GM models to track the common mode and differential inputs of, and provide the tail currents for, the differential input pair in the transconductance amplifiers greatly enhance the instrumentation amplifier performance in numerous ways.

Abstract: A circuit (10) having multiple poles within an active frequency range employs a movable zero (66) to maintain stability in the circuit (10) under variable load conditions. A pole (62) created by a frequency compensation element (14) maintains a fixed frequency within the active frequency range of the circuit (10). In addition, a variable load impedance (36) coupled to the circuit (10) generates a load pole (64) within the active frequency range of the circuit (10) that changes frequency over time. As the load pole (64) changes frequency, the frequency of the movable zero (66) is adjusted to achieve an enhanced stability condition within the circuit (10). In one embodiment, the frequency of the movable zero (66) tracks the frequency of the load pole (64) as the load impedance (36) changes.

Abstract: A switched gain differential amplifier is provided which includes first and second differential transconductance amplifier stages and a disabled dummy differential transconductance amplifier stage. The first and second differential transconductance amplifier stages have respective differential inputs that are coupled in-phase to one another and respective differential outputs that are coupled in-phase to one another. At least one of the stages is selectively enabled. The disabled dummy differential transconductance amplifier stage has a differential input coupled in-phase to the differential inputs of the first and second differential transconductance amplifier stages and a differential output cross-coupled out-of-phase to the differential outputs of the first and second differential transconductance amplifier stages.

Abstract: A low-power operational amplifier comprises a differential input-stage and an output stage. The differential input-stage includes first and second differentially coupled input transistors each having base, emitter, and collector electrodes. A first current mirror circuit is coupled to the first and second input transistors and produces a first current which perturbs the current flowing through the first input transistor. The output stage is coupled to the differential input-stage and to the current mirror circuit and produces a second larger current which perturbs the current flowing through the second input transistor. The ratio of the emitter areas of the first and second input transistors are selected to substantially eliminate offset voltage caused by the difference between the first and second perturbing currents. This device is especially suited for low-power Class A bipolar operational amplifiers such as the type employed in low-power medical devices.

Abstract: An amplifier comprising an input stage (IPST) having a pair of inputs (INN,INI) for receiving a differential input signal (Vin) and a pair of outputs (CQ6,CQ7) for delivering a differential intermediate signal in response to the differential input signal (Vin); an intermediate stage (INTST) for converting the differential intermediate signal to a non-differential intermediate signal, which intermediate stage (INTST) comprises a current mirror (Q5,R5,Q4,R4) having an input branch (Q5,R5) and an output branch (Q4,R4) for receiving the differential intermediate signal; an output stage (OPST) having an input coupled to the output branch (Q4,R4) and having an output for delivering an output signal (Vout) to an output (OP) of the amplifier; and means for stabilizing the amplifier. The means for stabilizing the amplifier comprises a capacitor (CM2) coupled between the output (OP) of the amplifier and the input branch (Q5,R5), and provides a large bandwidth and low supply voltage amplifier.

Abstract: The amplifier output stage circuit includes: a translinear loop 30 having first and second input nodes Vin+ and Vin−; a first transistor Q7 coupled between a first output node of the translinear loop 30 and a first supply node V+; a first output transistor Q9 coupled between an output node 36 of the circuit and the first supply node V+, and having a base coupled to a base of the first transistor Q7; a second transistor Q10 coupled between a second output node of the translinear loop 30 and a second supply node V−; a second output transistor Q12 coupled between the output node 36 of the circuit and the second supply node V−, and having a base coupled to a base of the second transistor Q10.