Abstract: A high frequency amplifier is provided with: an input terminal receiving a high frequency signal; an output terminal; a three-terminal active element having a first terminal connected with the input terminal and a second terminal connected with the output terminal; a transmission line; and a capacitive structure. The three-terminal active element outputs an output signal from the output terminal in response to the high frequency signal. The transmission line and the capacitive structure are connected in series between the first and output terminals, and operate together as a series resonance circuit. The transmission line functions as an open stub at a series resonance frequency of the series resonance circuit.

Abstract: An embodiment of an amplifier includes an amplifier output node operable to provide an output signal, and an output stage. The output stage includes a drive buffer having an input node and an output node, a drive transistor, and a compensation capacitor. The drive transistor has a control node coupled to the output node of the drive buffer, a first drive node, and a second drive node coupled to the amplifier output node. And the compensation capacitor has a first node isolated from the control node of the drive transistor by the drive buffer, and has a second node coupled to the amplifier output node. By buffering the control node of the drive transistor, one may reduce the level of nonlinear current referred back to the amplifier input as a nonlinear offset voltage, and thus may reduce the level of nonlinear distortion that his nonlinear offset voltage generates at the amplifier output.

Abstract: This disclosure relates to load compensating multi-stage amplifier structures at an output of one of the amplifier stages.

Abstract: There is provided an amplifier circuit having a common-source amplifier, an output load connected to an output terminal of the common-source amplifier, a buffer circuit connected to the output terminal of the common-source amplifier, a feedback circuit connected between an output terminal of the buffer circuit and an input terminal of the common-source amplifier, and a control circuit for controlling an impedance of the feedback circuit in accordance with a gain of the common-source amplifier.

Abstract: A frequency compensation circuit internal to an integrated circuit which comprises a transconductance amplifier having a first input configured to receive a reference voltage, a second input configured to receive an input voltage and an input current, a first output configured to output a first output current and a second output configured to output a second output current; and a compensation circuit connected to said second output of said transconductance amplifier, wherein said first output is connected to said second input.

Abstract: A low noise, low power differential two-stage amplifier includes a first stage comprising a pair of electrical devices that sense an input signal difference across the pair of electrical devices; and a control feedback loop operatively connected to the first stage, wherein the first stage in combination with the control loop feedback is adapted to place an exact copy of the signal across a first pair of resistive components, wherein the first pair of resistive components are adapted to generate a differential signal current, wherein the control feedback loop is adapted to ensure that the differential signal current goes a second pair of resistive components to generate a voltage output. Preferably, the first and second pair of resistive components are in ratio to produce the exact copy of the signal with some gain at an output of the first stage.

Abstract: The frequency and transient responses of a CMOS differential amplifier are improved by employing one or more compensating capacitors. A compensating capacitor coupled to a differential input of the CMOS differential amplifier is used to inject current into the differential input, such that the net current flow through the gate-to-drain capacitance of a MOS input transistor approaches zero. Thus, the Miller effect with respect to that MOS input transistor is substantially reduced or eliminated, resulting in increased frequency and transient responses for the CMOS differential amplifier. In one embodiment, the CMOS differential amplifier is a CMOS current mirror differential amplifier.

Abstract: A method of compensating a monolithic integrated operational amplifier against process and temperature variations, such that the operational amplifier is suitable for use in an active filter, the method comprising a providing an amplifier having a first stage and an output stage, wherein the output stage drives an RC load, and wherein a compensation capacitor at an output of the first stage is selected so as to scale with the capacitance C of the RC load, and a transconductance of the first stage is a function of the resistance R of the RC load.

Abstract: An inductively degenerated low noise amplifier arrangement is shown having a transistor and a bonding pad connected to the input terminal of the transistor, wherein the bonding pad has parasitic capacitance, and wherein the bonding pad includes a metal layer connected to a second terminal of the transistor. In case of a field-effect transistor the second terminal may be the source and in case of a bipolar transistor the second terminal may be the emitter. The metal layer may be the ground plane of the bonding pad or an additional, intermediate layer.

Abstract: A class AB folded-cascode amplifier having improved gain-bandwidth product, comprises a differential input circuit including a differential transistor pair coupled to a source of tail current and responsive to a differential input signal for conducting a first current, a cascode circuit coupled to the differential input circuit for supplying a second current thereto, and a class AB output stage. A compensation circuit is configured for feeding back mutually complementary compensation signals from an output node to the differential input circuit. Another compensation circuit is configured for feeding back a signal from the output of the output stage to the input of the output stage.

Abstract: A semiconductor device includes a phase compensation circuit 6 using a MOS capacitor with a structure in which an insulating film is disposed between a gate electrode formed on a semiconductor substrate and a diffusion layer. The phase compensation circuit includes first and second MOS capacitors 14, 15. A gate electrode terminal of the first MOS capacitor is connected equivalently to a diffusion layer terminal of the second MOS capacitor that is a terminal opposite to the gate electrode terminal. A potential difference generating element 16 that generates a potential difference by allowing a current to flow therethrough is connected between a diffusion layer terminal of the first MOS capacitor and a gate electrode terminal of the second MOS capacitor. When the MOS capacitors having the voltage dependence are used, e.g.

Abstract: The frequency and transient responses of a CMOS differential amplifier are improved by employing one or more compensating capacitors. A compensating capacitor coupled to a differential input of the CMOS differential amplifier is used to inject current into the differential input, such that the net current flow through the gate-to-drain capacitance of a MOS input transistor approaches zero. Thus, the Miller effect with respect to that MOS input transistor is substantially reduced or eliminated, resulting in increased frequency and transient responses for the CMOS differential amplifier. In one embodiment, the CMOS differential amplifier is a CMOS current mirror differential amplifier.

Abstract: An amplifying circuit having a bias voltage setting mechanism includes: a first amplifying element that amplifies an input signal and outputs the amplified signal as an output signal; a bias voltage setting unit that generates a bias voltage from the output signal on the basis of a control signal, such as an AGC voltage; and a high impedance element (third resistor) by which the bias voltage is applied to an input portion of the first amplifying element and which, when a component for bias voltage setting, such as a fourth resistor, is externally provided in the bias voltage setting unit, prevents a capacitive component of the component for bias voltage setting from being equivalently connected with respect to the input portion.

Abstract: A slew rate enhancement circuit is disclosed for increasing a slew rate in a two stage CMOS amplifier. The slew rate enhancement circuit detects an input signal transition in the two stage CMOS amplifier. Depending on the polarity of the input signal transition the slew rate enhancement circuit turns on either (1) a first current source to charge a first compensation capacitor, or (2) a second current source to charge a second compensation capacitor. The slew rate enhancement circuit increases the slew rate by a factor of four to five and decreases the settling time of a voltage transition by a factor of three.

Abstract: A transistor amplifier circuit has a current to current feedback transformer for neutralization of feedback capacitance and setting the input impedance of the amplifier. IM3 cancellation is implemented by out-of-band terminations at the input, which does not depend on the loading of the output of the amplifier. The IM3 cancellation contributes better linearity, while the capacitance neutralization contributes high and stable gain. These features are more orthogonal than other prior art techniques in terms of gain and linearity over a wide dynamic range. Hence there is less of a trade-off between the desirable properties of high gain and good linearity. Notably they can be implemented to have good efficiency and high levels of integration, which are important for many applications such as wireless transceivers for portable devices or consumer equipment. The amplifier can be a single ended or a differential common emitter amplifier.

Abstract: A Miller-compensated amplifier, having an amplifier input and an amplifier output, comprises a first gain stage, a second gain stage, a third gain stage, and a capacitor. The first gain stage has the amplifier input as a first gain stage input thereto and a first gain stage output. The second gain stage has a second gain stage input, coupled to the first gain stage output, and a second gain stage output. The third gain stage has a third gain stage input, coupled to the second gain stage output, and provides an output voltage at the amplifier output. The capacitor is coupled between the amplifier output and the second gain stage input. The second gain stage amplifies a small signal part of a current received thereby and leaves a DC component thereof substantially the same.

Abstract: Apparatus (10) comprising a level shifter (15) connectable to a signal input (1) for receiving an input signal (s(t)) with a negative signal swing. The level shifter (15) provides for a DC shift of the input signal (s(t)) to provide an output signal (r(t)) with positive signal swing. The level shifter (15) comprises an amplifier (17) with a first input (11), a second input (12), and an output (13). A first capacitor (C1), a second capacitor (C2), a reference voltage supply (16), and a transistor (14; 74) serving as a switch, are arranged in a network as follows: the first capacitor (C1) is arranged between the signal input (1) and the first input (11), the second capacitor (C2) is arranged in a feedback-loop (18) between the output (13) and the first input (11), and the reference voltage supply (16) is connected to the second input (12). The transistor (14) is arranged in a branch (19) that bridges the second capacitor (C2), whereby a control signal (CNTRL) is applicable to a gate (14.

Abstract: The frequency and transient responses of a CMOS differential amplifier are improved by employing one or more compensating capacitors. A compensating capacitor coupled to a differential input of the CMOS differential amplifier is used to inject current into the differential input, such that the net current flow through the gate-to-drain capacitance of a MOS input transistor approaches zero. Thus, the Miller effect with respect to that MOS input transistor is substantially reduced or eliminated, resulting in increased frequency and transient responses for the CMOS differential amplifier. In one embodiment, the CMOS differential amplifier is a CMOS current mirror differential amplifier.

Abstract: A VGA is provided that is designed to reduce or even eliminate entirely variations in phase response/shift with changes in gain. Compensation is made for parasitic capacitances of elements in the VGA that would otherwise cause variation in phase with changes in gain. An additional capacitance is introduced to the VGA to compensate for the sources of the parasitic capacitance. The technique for introducing the additional capacitance depends on the source of the parasitic capacitance being treated. The additional capacitance is introduced to one or more of transistor amplifier circuits in the VGA, wherein each transistor amplifier circuit has a different gain and one of the transistor amplifier circuits is selected depending on the desired gain of the VGA. These compensation techniques equalize the phase response of the transistor amplifier circuits (each having a different gain) so that regardless of which transistor amplifier circuit is selected, the phase shift will be substantially the same.

Abstract: Control loops in a voltage regulator can be stabilized using minimal silicon area. A current limit signal, generated by a current limit control loop in the voltage regulator, can be divided to minimize a zero provided in a compensation set associated with a voltage control loop, thereby stabilizing both loops. The compensation set can include a resistor (the zero) and a capacitor (a pole) connected in series between output and input terminals of an amplifier. Dividing the current limit signal can include injecting a first portion of the current limit signal on a first side of the resistor and injecting a second portion of the current limit signal on a second side of the resistor. The ratio of the first and second portions can be based on a gain of the amplifier, thereby minimizing an effect of the resistor.

Abstract: The effect of input signal frequency on the output of a differential amplifier is reduced by connecting the conductor of each of the input signal components to the respective conductor of the output signal component of opposite phase with a capacitor substantially equal to the parasitic capacitances interconnecting the terminals of the amplifier's transistors.

Abstract: An inductively degenerated low noise amplifier arrangement is shown having a transistor and a bonding pad connected to the input terminal of the transistor, wherein the bonding pad has parasitic capacitance, and wherein the bonding pad includes a metal layer connected to a second terminal of the transistor. In case of a field-effect transistor the second terminal may be the source and in case of a bipolar transistor the second terminal may be the emitter. The metal layer may be the ground plane of the bonding pad or an additional, intermediate layer.

Abstract: A flip around amplifier circuit is provided that includes an amplifier having first and second amplification stages, a Miller capacitor, and a resistive element in series with the Miller capacitor, where an output line of the second amplification stage can be coupled to an output line of the first amplification stage through the Miller capacitor and the series resistive element. The circuit can include a feedback capacitor having a first plate coupled to an input line of the amplifier, and a flip around switch that can be operated so as to connect an output line of the amplifier to a second plate of the feedback capacitor. The circuit's classical transfer function can include a zero associated with the Miller capacitor and the series resistive element, and a pole associated with the feedback capacitor and the on-resistance of the flip around switch, where the zero is substantially equal to the pole.

Abstract: An active tunable filter circuit for use as an integratable active filter in a mobile radio apparatus, comprises an active amplifier circuit (A) including a reactive feedback network including a first tunable element (L1) set to pass with amplification a wanted input signal, and a passive resonant circuit (P) coupled to the active amplifier circuit and including an inductive element (LFB, L3 or L4) and an inactive semiconductor element (FET2, FET3 or FET4) having an interelectrode capacitance which in operation resonates with the inductive element at a harmonic of the wanted signal. In one configuration (FIG. 1) the circuit comprises a band pass filter with amplification and in another configuration (FIG. 6-not shown) the circuit comprises a harmonic notch filter with amplification.

Abstract: A unity gain amplifier has a current mirror. A compensation circuit has an input coupled to an output of the current mirror. An output transistor has a base coupled to the output of the current mirror and a source of the output transistor is coupled to an output of the compensation circuit. The compensation circuit has a resistor in series with a capacitor.

Abstract: An amplifier circuit for receiving an input signal and providing an output signal, comprises a main chain of logic stages with a plurality of nodes therebetween, and at least one auxiliary chain nested between one node in the main chain and another node, which is not the next node, to form a series of feed back or feed forward nested equalisation loops; whereby the input signal is fed serially down the main chain and is also fed through the said at least one auxiliary chain and summed to provide the output signal. The invention overcomes gain-bandwidth limits of the drive stages and bandwidth reductions that occur when analogue stages operating in a linear mode are concatenated.

Abstract: A frequency compensation device for providing added compensation to an operational amplifier, such as a bipolar or MOS rail-to-rail output operational amplifier, when the output device of the operational amplifier is in saturation. The device comprises a detector circuit for detecting those conditions which can cause the output device to go into saturation. When saturation is detected, an auxiliary frequency compensation device provides added frequency. Thereby, in a normal mode of operation, the op-amp is not overcompensated. Yet, when an output device becomes saturated, the auxiliary compensation is added to improve stability and prevent the op-amp from becoming oscillatory.

Abstract: An operational amplifier is dynamically compensated depending on the internal state of the operational amplifier. Compensation is fully enabled only when the internal state indicates a risk of instability. When the internal state of the operational amplifier indicates there is no risk of instability, the compensation is totally or partially turned off.

Abstract: A differential amplifier receives a differential input signal and generates an output signal at an output node. An auxiliary circuit coupled to the differential amplifier operates to improve slew rate response. In quiescent and small signal situations with respect to the differential input signal, the auxiliary circuit does not alter or change operation of the differential amplifier. However, in situations where a large signal change is experienced with respect to the differential input signal, the auxiliary circuit functions to speed up the sourcing and sinking current to/from the output node. A stability compensation capacitor coupled to the output node is accordingly more quickly charged or discharged and an improvement in slew rate performance of the differential amplifier is experienced.

Abstract: The frequency and transient responses of a CMOS differential amplifier are improved by employing one or more compensating capacitors. A compensating capacitor coupled to a differential input of the CMOS differential amplifier is used to inject current into the differential input, such that the net current flow through the gate-to-drain capacitance of a MOS input transistor approaches zero. Thus, the Miller effect with respect to that MOS input transistor is substantially reduced or eliminated, resulting in increased frequency and transient responses for the CMOS differential amplifier. In one embodiment, the CMOS differential amplifier is a CMOS current mirror differential amplifier.

Abstract: A chopper-stabilized current-mode instrumentation amplifier comprises first and second input amplifiers coupled to respective input nodes and arranged to produce respective currents in response to a differential input voltage applied to the input nodes; the currents are coupled to an output node. To reduce gain errors that might otherwise arise due to the parasitic capacitances of the on- and/or off-chip devices and/or structures making up the input amplifiers, the invention includes gain correction circuitry coupled to the IA. The gain correction circuitry replicates at least some of the parasitic capacitances, and provides compensation currents to the IA which reduce both input- and output-referred gain errors that might otherwise arise.

Abstract: The frequency and transient responses of a CMOS differential amplifier are improved by employing one or more compensating capacitors. A compensating capacitor coupled to a differential input of the CMOS differential amplifier is used to inject current into the differential input, such that the net current flow through the gate-to-drain capacitance of a MOS input transistor approaches zero. Thus, the Miller effect with respect to that MOS input transistor is substantially reduced or eliminated, resulting in increased frequency and transient responses for the CMOS differential amplifier. In one embodiment, the CMOS differential amplifier is a CMOS current mirror differential amplifier.

Abstract: The invention provides an amplifier arrangement which is of multistage design. The output transistor in the output stage has a coupling path between its control input and its controlled path. The coupling path comprises a series circuit comprising a Miller compensation capacitance and a resistance with a controllable resistance value. It is thus possible to ensure stable operation of the amplifier regardless of bias and load conditions while simultaneously reducing the quiescent current drawn.

Abstract: An output circuit for a semiconductor amplifier element having an output capacitance (20, 42) that is to be cancelled by a first LC circuit having a first inductance (22, 44) and a first capacitance (24, 46), said output circuit comprising an additional inductance circuit with an additional inductance (30, 52) and an additional capacitance (32, 54), said first inductance circuit and said additional inductance circuit compensating for the output capacitance (20, 42) of the semiconductor amplifier element, while the first inductance (22, 44) and the first capacitance (24, 46) cancel out the second harmonics within the output signal of the semiconductor amplifier element.

Abstract: A voltage-to-current conversion circuit includes an error amplifier (12A) which amplifies a voltage difference between the drains of the first (6) and second (7) transistors of a first current mirror, wherein drain current of the first transistor is proportional to an input voltage (Vin). The output of the error amplifier is connected to the gates of the first and second transistors. A compensation capacitor is coupled between the gate and drain of the first transistor. The drain current of the second transistor flows through a cascode transistor (16) to an input of a second current mirror, an output transistor (31) of which provides a current (Ibias) which is proportional to the input voltage (Vin) as a bias current for the error amplifier, to provide stable operation.

Abstract: Expansion of the bandwidth of a wideband CMOS data amplifier is accomplished using various combinations of shunt peaking, series peaking, and miller capacitance cancellation. These various combinations are employed in any of the amplifier input stage, in intermediate stages, or in the last stage.

Abstract: A CMOS operational amplifier with a Class AB output stage has an output terminal and an input stage driving the output stage. The Class AB output stage includes a pair of p-channel and n-channel output transistors series-connected between the VDD and VSS supply terminals of a power supply. Each of the output transistors has associated biasing circuitry with a pair of positive and negative driving inputs and a biasing input. The input stage has driving outputs connected to corresponding ones of the driving inputs of the output stage. Each driving output is derived from the drain of a MOS transistor connected in series with a diode connected MOS transistor between the VDD and VSS supply terminals. By avoiding the conventional stacked MOSFETs that would set the minimum supply voltage to more than two threshold voltages, the op-amp can be operated over the full range of supply voltage.

Abstract: An Ahuja compensation circuit includes a feedback loop with a high swing cascode biasing circuit. The high swing cascode biasing circuit includes a frequency boosting circuit. The frequency response of the high swing cascode biasing circuit and the Ahuja compensation circuit are improved by the frequency boosting circuit.

Abstract: The present invention pertains to a MOS type differential buffer circuit. The buffer proposed herein utilizes capacitive coupling to apply small AC signals to an amplifying current source to mitigate attenuation owing to body effect and output impedance, among other things, in an associated follower component. The proposed circuit does not, however, promote an increase in current and/or power dissipation. Additionally, the circuit allows a desired gain to be achieved while maintaining a relatively constant output impedance, compared to a simple differential source follower.

Abstract: Provided is a wideband amplifier which can provide an increased operation bandwidth without being limited by manufacturing process. A source follower circuit having a MOS transistor and constant-current supplies is provided in parallel to a MOS transistor serving as an amplifier of the input stage. Furthermore, the sources of the MOS transistor serving as the output of the source follower circuit are connected to the output nodes of the input stage amplifier via phase compensation capacitors, respectively. This configuration provides an increased phase allowance to the wideband amplifier, thereby providing an improved operation bandwidth without being limited by the manufacturing process employed.

Abstract: A technique for minimizing the effect of parasitic capacitance in a resistive gain amplifier. Instead of the resistors being formed directly over the substrate, or over an oxide of the substrate, a semiconductor element (e.g., an n-well) is used between the resistor and the substrate. For resistors in the input circuit, this semiconductor element is connected to the voltage input rather than ground. For the resistors in the feedback loop circuit, the semiconductor element is connected to the voltage output of the operational amplifier. The insertion of this semiconductor element provides the ability to programmably connect the parasitic capacitance to somewhere other than ground. By connecting the parasitic capacitance to the voltage input or voltage output, the ground connection is eliminated, eliminating the pole introduced by the parasitic capacitance.

Abstract: Synthetic circuit elements and amplifier applications for synthetic circuit elements are provided. The synthetic circuit elements disclosed herein may be configured to compensate for some or all of the parasitic capacitance normally associated with circuit elements disposed on a substrate providing a selectable impedance characteristic. Amplifier circuit constructed using such synthetic circuit elements exhibit improved performance characteristics such as improved recovery time, frequency response, and time domain response.

Abstract: This amplifier is intended for amplifying variable signals superimposed on a continuous signal. This continuous signal serves in particular for biasing a component, a magnetoresistive resistor used as a hard disk reading head. To avoid the harmful effects of a sudden fluctuation in the continuous signal, this amplifier comprises a set of switchable reactive elements (70) for acting on said transfer function and a bias drift compensation circuit (80) for controlling the switching of said switchable elements with a view to anticipating the effects of said fluctuation.

Abstract: A monolithic low dropout regulator includes an active capacitor multiplier that is used to form the dominant pole of the regulator, thereby yielding stability. This decouples the system stability from the high-frequency power supply rejection ratio (PSRR). The PSRR at high frequencies is tuned independently using a reasonable on-chip capacitor C2.

Abstract: To an existing class AB amplifier receiving at a gate of one of a NMOS or a PMOS type CMOS transistor an input signal, the gate of this CMOS transistor having a nonlinear gate capacitance with its switched operation, is added another, opposite-type, one of a NMOS or a PMOS type CMOS transistor that also receives at its gate the same input signal. The nonlinear gate capacitance of this other CMOS transistor is essentially opposite to the nonlinear gate capacitance of the existing CMOS transistor that receives the input signal within the class AB amplifier. This other transistor serves to compensate for the nonlinear gate capacitance of the existing CMOS transistor. Any nonlinearity due, in particular, to any nonlinear change in gate capacitance of a CMOS transistor that is used in particular within a class AB amplifier is thus substantially canceled.

Abstract: Circuitry including Miller-effect feedback for use as part of a closed loop system such as a low dropout voltage regulator that provides current to a load at a specified voltage close in value to the power supply voltage. Various aspects of the presently claimed invention include using, within the Miller-effect feedback loop: a buffer amplifier to reduce loading effects upon an internal high impedance circuit node, output compensation circuitry to introduce a transfer function pole for substantially canceling a transfer function zero associated with external load circuitry; and Miller-effect compensation circuitry to introduce a transfer function zero for substantially canceling a transfer function pole associated with the Miller-effect feedback.

Abstract: A high gain amplifier includes a differential amplifier stage having a pair of transistors; first and second input circuits for providing input signals to the pair of transistors; transistor means arranged as a differential-to-single-ended converter driven by the differential amplifier stage to provide a single ended output signal; an intermediate gain stage having an input responsive to the single ended output signal; bias means for the differential amplifier, the bias means including circuit means for maintaining the currents through the pair of transistors in constant ratio independently of changes in load at the intermediate gain stage; and an inverting gain output stage driven by the intermediate gain stage and having an output for driving a load substantially from rail to rail. Also disclosed is a frequency compensation capacitor circuit connected between the input of the intermediate gain stage and the output of the inverting gain output stage.

Abstract: An improved power-off, loop-through return-loss characteristic for a current feedback operational amplifier is provided by adding a positive feedback capacitor between the input and output of the operational amplifier. The positive feedback capacitor results in a negative capacitance input impedance for the operational amplifier that cancels stray capacitances at the input.

Abstract: A high bandwidth operational amplifier architecture has three control loops, which are combined via a voltage-follower-configured field effect transistor. The first control loop is an instantaneous main amplification path and employs positive feedback-based Vgs correction of the output transistor. The second control loop has a bandwidth considerably lower than the first loop and employs negative feedback to correct for long term drift errors. The third control loop, utilizing negative feedback, is a fast path having a bandwidth that overlaps the bandwidth of the first control loop, and corrects for overshoot and undershoot in the main amplification path.

Abstract: An improved power-off, loop-through return-loss characteristic for a current feedback operational amplifier is provided by adding a positive feedback capacitor between the input and output of the operational amplifier. The positive feedback capacitor results in a negative capacitance input impedance for the operational amplifier that cancels stray capacitances at the input.