Abstract: There is provided an amplifier that comprises a plurality of amplifier stages arranged in a cascade; and a frequency-dependent load associated with the output of at least one of the plurality of amplifier stages, the frequency dependent load being adapted to reduce a voltage or current offset in the output of said at least one amplifier stage.

Abstract: A cascade-connected transistor includes a common-source transistor which receives an input signal, and a common-gate transistor which is connected to a drain terminal of the common-source transistor and outputs an output signal. A band-pass filter receives the output signal of the cascade-connected transistors. An adjustment circuit is interposed between the drain terminal and the gate terminal of the common-gate transistor, and adjusts the output impedance of the cascade-connected transistor.

Abstract: A disclosed operational amplifier circuit with a multi-stage amplifier configuration provides fast-response and high withstand-voltage characteristics without using high withstand-voltage transistors as output transistors in its amplifying stages. The output voltage range of a differential amplifier circuit in a first stage is limited by voltage clamping based on a reverse withstand voltage of a bipolar diode. The output voltage range of an amplifier circuit in a second stage is limited by voltage clamping based on a reverse withstand voltage of another bipolar diode. A constant voltage circuit and an apparatus including such an operational amplifier circuit are also disclosed.

Abstract: A power amplifier includes an amplification circuit, an input stage matching circuit, and an output stage matching circuit. The amplification circuit amplifies an input signal in each frequency band by an active element common to the signals in plural types of frequency bans, and outputs the amplified signal. The input stage matching circuit is disposed on an input side of the active element, and performs an impedance-matching between an output impedance of a circuit which supplies the signals of the plural types of frequency bands and an input impedance of the active element. The output stage matching circuit is disposed on an output side of the active element, and performs an impedance-matching between an input impedance of a circuit which receives the signals of the plural types of frequency bands outputted from the active element and an output impedance of the active element.

Abstract: In a high frequency power amplifier circuit that supplies a bias to an amplifying FET by a current mirror method, scattering of a threshold voltage Vth due to the scattering of the channel impurity concentration of the FET, and a shift of a bias point caused by the scattering of the threshold voltage Vth and a channel length modulation coefficient ? due to a short channel effect are corrected automatically. The scattering of a high frequency power amplifying characteristic can be reduced as a result.

Abstract: A multistage amplifier and design method are disclosed. The multistage amplifier has a plurality of amplifier stages, each stage having an amplifier designed and biased to operate at or near the amplifier's power added efficiency (PAE) peak. The PAE peak of each of the amplifier is at or near the amplifiers linear-compression transition region, providing a multistage power amplifier that is power efficient and has desirable amplitude to amplitude and amplitude to phase power transfer characteristics. The amplifier is designed by matching the output impedance of a final stage with a load. Amplifier stages are iteratively designed from the last stage to the first. At each stage, an amplifier and drive circuit are designed. The drive circuit and amplifier are designed to provide each stage with output impedance matched to the input impedance of the following stage and to operate at or near the PAE peak of the amplifier.

Abstract: An overdrive control system includes a voltage controlled current source to deliver a compensation current, and being between a first voltage reference and an internal node, which is connected to an output terminal. The voltage controlled current source has a control terminal connected to an output terminal of an adding block, which has a positive input connected to an input terminal. At least one clamping block is between the output terminal and a second voltage reference, and is connected to a negative input of the adding block. The voltage controlled current source delivers its compensation current to the output terminal when a voltage signal on the input terminal has an higher value than a voltage signal on the output terminal, and forces an output voltage signal to follow an input voltage signal to an extent that depends on a clamping voltage provided by the clamping block.

Abstract: A negative-feedback type ultra-wideband signal amplification circuit is proposed, which is designed for integration to an ultra-wideband (UWB) signal processing circuit system for providing a low-noise amplification function to UWB signals. The proposed circuit architecture is characterized by the provision of a dual-step filter circuit on the input side, the provision of a resistive-type feedback circuit in the transistor-based amplification circuitry, and the provision of a common-source transistor-based amplification circuit on the output side. These features allow the proposed signal amplification circuit to have flat power gain, lower power consumption, low noise figure, and higher operational stability.

Abstract: An apparatus comprising a first stage and a second stage. The first stage generally comprises a first transistor configured as a common-emitter amplifier. The second stage generally comprises a second and third transistor configured as a low voltage Darlington transistor pair. The first stage may be directly coupled to the second stage. The second transistor generally comprises a field effect (FET) input transistor. The third transistor generally comprises a bipolar output transistor. In one example, the apparatus may comprise a 2-stage RF amplifier operating from DC to microwave frequencies.

Abstract: A transmitter includes a first variable gain amplifier (VGA) and a second VGA coupled to an output of the first VGA. The first and second VGAs each comprise a plurality of parallel gain stages. Gains of the first and second VGAs are equal to the sum of the gains of the activated parallel amplifiers within each corresponding plurality of parallel amplifiers. Each parallel amplifier comprises a parallel differential amplifier controlled by a pair of switches to activate and deactivate the parallel differential amplifier. The gains of the first and second VGAs are increased by activating additional parallel amplifiers. The gains of the first and second VGAs are decreased by deactivating additional parallel amplifiers. The variable gains of the first and second VGAs provide an extended gain control with improved local oscillator (LO) leakage interference rejection.

Abstract: A small size power amplifier includes a first amplifier provided for a first signal path; a second amplifier provided for said first signal path; and a third amplifier provided for a second signal path parallel to said first signal path. A voltage control circuit configured to bias one of a first set of said first amplifier and said second amplifier, and a second set of said third amplifier, based on an output power.

Abstract: A dual supply amplifier without using an inter-stage capacitor is disclosed. The dual supply amplifier has an input stage coupled to a lower supply voltage VDD1 for generating a voltage signal V3 proportion to a difference between a pair of inputs. A conversion stage is coupled a higher supply voltage VDD2 and a third supply voltage VDD3, which can be ground or a negative potential, for generating a signal V1 with reference to VDD2 and a signal V2 with reference to VDD3. An output stage receives V1 and V2 for generating an output signal Vo with a swing between VDD2 and VDD3.

Abstract: A low-noise amplifier is provided according to the present invention. The low-noise amplifier includes a first amplifier stage, a second amplifier stage, a third amplifier stage, an input matching network, inter-stage matching networks, and an output matching network. The impedance of the input matching network and the input impedance of the first amplifier stage are conjugate matched, thereby decreasing system power consumption and noise factor. The system gain is enhanced by cascading three stages of amplifiers.

Abstract: A power amplifier according to the present invention is operated by switching a main power amplifier and a subsidiary power amplifier. The idle current of the subsidiary power amplifier is smaller than the idle current of the main power amplifier. Each of the main power amplifier and the subsidiary power amplifier has a former amplification element for amplifying RF signals, a latter amplification element for amplifying output signals from the former amplification element, a former bias circuit for driving the former amplification elements, and a latter bias circuit for driving the latter amplification elements, respectively. The interval between the latter amplification element of the main power amplifier and the latter amplification element of the subsidiary power amplifier is not more than 100 ?m. The interval between the latter amplification element of the main power amplifier and the latter bias circuit of the subsidiary power amplifier is not less than 200 ?m.

Abstract: A single-stage amplifier includes (1) first and second “gain” transistors coupled in a common source configuration, (2) first and second resistors providing self-biasing for the first and second transistors, respectively, (3) first and second current sources providing bias currents for the first and second transistors, respectively, and (4) a load impedance coupled between the drains of the first and second transistors. The amplifier may further include (5) third and fourth “compensation” transistors coupled in parallel with, and used to compensate parasitic capacitances of, the first and second transistors, respectively, and (6) third and fourth resistors providing self-biasing for the third and fourth transistors, respectively. Variable gain may be achieved by varying the bias currents for the gain transistors. A two-stage amplifier may be formed with two stages coupled in cascade, with each stage including most or all of the circuit elements of the single-stage amplifier.

Abstract: Provided herein is a power amplifier having a multiple stage power amplifier section and an output matching network section. The multiple stage power amplifier section can include multiple power amplifier stages with interstage matching circuits located therebetween. The output matching network can be configured to match the multiple stage power amplifier section at multiple different frequencies or frequency bands. The power amplifier device is capable of selective operation within one of multiple different frequencies or frequency bands.

Abstract: A magnetic field tolerant amplifier having an amplifier stage, a differential to single-ended output amplifier stage and a first and second delay line. In another embodiment the invention relates to a magnetic gradient cancellation delay line including two coils connected in series at a junction and non-inductively wound to cancel induced currents from magnetic gradient. In another embodiment the invention relates to a patient lead including a flexible circuit substrate having a flexible conductor having distributed impedance. In still yet another embodiment the invention relates to a wireless transceiver system including an RF cancellation delay line; a differential amplifier stage; a differential to single ended output amplifier stage; an A/D converter; an RF transceiver and an antenna.

Abstract: A multistage amplifier and design method are disclosed. The multistage amplifier has a plurality of amplifier stages, each stage having an amplifier designed and biased to operate at or near the amplifier's power added efficiency (PAE) peak. The PAE peak of each of the amplifier is at or near the amplifiers linear-compression transition region, providing a multistage power amplifier that is power efficient and has desirable amplitude to amplitude and amplitude to phase power transfer characteristics. The amplifier is designed by matching the output impedance of a final stage with a load. Amplifier stages are iteratively designed from the last stage to the first. At each stage, an amplifier and drive circuit are designed. The drive circuit and amplifier are designed to provide each stage with output impedance matched to the input impedance of the following stage and to operate at or near the PAE peak of the amplifier.

Abstract: A bias circuit 22 in a power amplifier 1 is provided with a VBE-controlled voltage source circuit 20 and a Nagata current mirror circuit 21. The Nagata current mirror circuit 21 includes a transistor Tr5 and a transistor Tr6. The transistor Tr5 has its emitter grounded, its base connected to a control input terminal 17 via a resistor R3, and its collector connected to that base via a resistor R4. The transistor Tr6 has its emitter grounded, its base connected to the collector of the transistor Tr5, and its collector connected to the base of the transistor Tr3. The arrangement is capable of compensating both the temperature characteristics of the gain of the power amplifier 1 and the control input voltage characteristics of the gain of the power amplifier 1. In other words, the arrangement is capable of reducing the temperature dependence and control input voltage dependence of the gain of the power amplifier 1.

Abstract: A cascode-connected amplifier circuit including two transistors cascode-connected to each other, where a first transistor having a grounded emitter or a first field-effect transistor having a grounded source, and (a) a second transistor, having a grounded base, which is cascode-connected to the first transistor or to the first field-effect transistor, or (b) a second field-effect transistor, having a grounded gate, which is cascode-connected to the first transistor or to the first field-effect transistor. The cascode-connected amplifier circuit includes a switching element causing a collector of the first transistor or a drain of the first field-effect transistor to be grounded.

Abstract: A low-noise amplifier is provided according to the present invention. The low-noise amplifier includes a first amplifier stage, a second amplifier stage, a third amplifier stage, an input matching network, inter-stage matching networks, and an output matching network. The impedance of the input matching network and the input impedance of the first amplifier stage are conjugate matched, thereby decreasing system power consumption and noise factor. The system gain is enhanced by cascading three stages of amplifiers.

Abstract: Example embodiments of the invention may provide systems and methods for a power amplifier. The systems and methods may include a first common-source device having a first source, a first gate, a first drain, and a first body, where the first source is connected to the first body, and wherein the first gate is connected to an input port. The systems and methods may further include a second common-gate device having a second source, a second gate, a second drain, and a second body, where the second source is connected to the first drain, where the second source is further connected to the second body, and where the second drain is connected to an output port.

Abstract: An H.F. power amplifier is disclosed having a plurality of branches (10, 11, 12) switched in parallel. Each branch comprises a plurality of amplifier elements (T1, T4) switched in series. Resistors (R2, R5) enable the voltage (U_DS) applied to the amplifier elements (T1, T4) to be set at a fraction of a supply voltage (Ud) applied to the branches (10, 11, 12). Capacitors (C2, C4) are used to adjust the source impedance of the amplifier elements (T2, T4). In order to prevent the gate-drain voltage (U_GD) from exceeding the breakdown voltage of an amplifier element (T1, T4) and damaging the amplifier element (T1, T4), a limiting path (7) is connected according to the invention between the gate terminal (G) and the drain terminal (D) of the amplifier element (T1, T4), the limiting path (7) being switchable between a conducting state and a blocking state depending on the gate-drain voltage (U_GD).

Abstract: The invention is a high-power transconductance circuit (HVTC) comprising three direct-coupled stages which can be substituted for a final-stage power-amplifying vacuum tube in an audio amplifier. The HVTC consists of an input stage, a driver stage, an output stage, and a power conditioner. The input to the HVTC is a composite signal consisting of an AC component and a DC component. The input stage conditions the input composite signal for input to the driver stage. The driver stage transforms the input composite signal into the driving signal for the output stage. The output stage utilizes one or more power transistors to drive a load. The power conditioner supplies regulated power to the HVTC. The input composite signal is direct-coupled through the input stage and the driver stage to the output stage.

Abstract: The invention relates to a method and apparatus for shaping an input signal Son which is input to a multi-stage amplifier arrangement, to provide a definable output signal contour Soff. Individual amplifier stages are controlled by a control signal generated by a pulsed current source of a definable pulse length T. According to the invention, successive amplifier stages are each controlled (switched on) after a definable delay time ?ton 1, ?ton 2 following the preceding stage. Each amplifier stage has an assigned pulsed current source for generating the control signals of definable pulse length T. One such pulse generator respectively is assigned to each current source.

Abstract: An amplifier includes an input terminal, an output terminal, a cascode circuit with a first and a second transistor serially coupled between an output terminal and a terminal of a predefined potential with a control terminal of the first transistor being coupled to the input terminal, a first bipolar transistor having a collector/emitter path, forming a series circuit coupled to the terminal of a predefined potential with the first transistor, a power supply circuit for providing power supply voltages over a cascode circuit and a series circuit and a second bipolar transistor coupled between the output terminal and the terminal of the predefined potential with bases of the first bipolar transistor and the second bipolar transistor being coupled to each other and a current source.

Abstract: In an example embodiment, an apparatus, such as a two stage operational amplifier, comprising a first stage amplifier having an input and an output, and a second stage amplifier having an input and an output, the input of the second stage amplifier is coupled to the output of the first stage amplifier. A first bias circuit is operable to set a common mode voltage of the first amplifier. A second bias circuit is operable to set a common mode voltage of the second amplifier. A first feedback circuit is coupled to the first bias circuit and the output of the first stage. The first feedback circuit is operable to control the common mode voltage of the first stage amplifier based on the common mode voltage set by the first bias circuit and the output of the first stage amplifier.

Abstract: This disclosure relates to load compensating multi-stage amplifier structures at an output of one of the amplifier stages.

Abstract: A high-frequency electronic switch includes a signal input terminal to which a high-frequency signal to be switched is input, a plurality of amplifying circuits with transistors, to respectively amplify the high-frequency signal to be switched sequentially, the amplifying circuits being cascade-connected in a plurality of stages to the signal input terminal, a signal output terminal which is connected to an output section of an amplifying circuit at final stage among the plurality of amplifying circuits, and which outputs the high-frequency signal to be switched sequentially amplified, a control terminal to which a pulse signal serving as a switching signal having a period of a first level and a period of a second level is input, and a supply current control circuit which makes the plurality of amplifying circuits be in an amplification-operational state by supplying operational current to each of the transistors of the plurality of amplifying circuits in a period when the pulse signal input to the control te

Abstract: A multi-mode RF amplifier is disclosed having high and low output power modes composed of two power paths. When the multi-mode RF amplifier is biased into the high power, HP, mode, substantial power is delivered via both (first and second) paths. While in the low power, LP, mode, power is delivered via second path only which is designed to reduce current consumption and improve efficiency under low power (backoff) operation. The multi-mode RF amplifier has power amplifiers in one embodiment, but no mechanical or electronic switches. The multi-mode amplifier utilizes impedance matching circuits where the impedances change under different power amplifier bias conditions in order to optimize current consumption under both modes of operations and is power efficient for portable applications. Note that, in a preferred embodiment, even in the HP mode more power is delivered to the second power path than to the first power path.

Abstract: Method and systems related to obstructing a first predefined portion of at least one defined wavelength of light incident upon a first photo-detector array; and detecting the at least one defined wavelength of light with a photo-detector in a second photo-detector array.

Abstract: An RF amplifier can include multiple gain stages, wherein each gain stage can be DC coupled to an adjacent gain stage. Each input gain stage can include either n-type gain transistors or p-type gain transistors. Multiple input gain stages can be designed/built by interleaving input gain stages of different types. Notably, an input gain stage including n-type gain transistors has a p-type bias transistor. Similarly, an input gain stage including p-type gain transistors has an n-type bias transistor. In this configuration, the bias transistor is the same type as the downstream gain transistors. Therefore, each bias transistor can accurately track the behavior of the transconductance devices of the next gain stage.

Abstract: An amplifier circuit comprises an amplifier circuit input and a first amplifier having an input that communicates with the amplifier circuit input and an output. A second amplifier has an input that communicates with the output of the first amplifier and an output. A first resistance has one end that communicates with the input of the first amplifier. An inverter that has an input that communicates with the output of the second amplifier and an output that communicates with an opposite end of the first resistance.

Abstract: A high-power amplifier changes matching conditions of an output matching circuit 5 connected between a final stage amplifying element 3 and an output terminal 8 in response to the output power of the amplifying element 3. Thus, the efficiency at low output power can be greatly improved without reducing the efficiency at the maximum output. Besides, since it is not necessary to load a DC-DC converter, an increase in size or cost can be prevented.

Abstract: The summing comparator includes: a first integrator; a second integrator for receiving an output of the first integrator; and a comparator for switching when the output of the first integrator is greater than the output of the second integrator. The outputs of the first and second integrators are directly compared by the comparator without the necessity of a summing amplifier.

Abstract: Multi-segment gain control system. Apparatus is provided for a multi-segment gain control. The apparatus includes logic to convert a gain control signal to an exponential signal, and logic to map the exponential signal to multiple control signals that are used to control multiple gain stages to produce linear multi-segment gain control.

Abstract: A low noise amplifier including a first-stage signal amplifier, a second-stage signal amplifier and a gain control unit is disclosed. The first-stage signal amplifier is for receiving an input signal and outputting a first output signal accordingly. The second-stage signal amplifier is coupled to the first-stage signal amplifier for outputting a second output signal according to the first output signal. The second-stage signal amplifier includes a first output transistor for outputting the second output signal. The gain control unit includes a first variable resistance device coupled to an input terminal of the first output transistor for adjusting voltage gain of the second output signal.

Abstract: A gain compensation circuit, applied to a microwave transceiver, includes a gain adjuster, a first attenuator and a second attenuator. The gain adjuster is disposed between a first amplifier and a filter for adjusting a nominal gain of the microwave transceiver. The first attenuator is disposed between the filter and a second amplifier for providing a first gain compensation. The second attenuator is electrically connected to the output of the second amplifier for providing a second gain compensation. The first and second gain compensations keep the gain of the microwave transceiver at a constant value under varying temperature conditions, and the first and second attenuators are used to reduce the degradation of return loss and noise figure of the microwave transceiver.

Abstract: A gain compensation circuit comprises a first amplifier, a second amplifier, a filter, a first attenuator, a second attenuator and a third attenuator. The first amplifier is configured to amplify an input signal of the microwave signal processor. The filter is disposed between the first and second amplifiers. The first attenuator is disposed between the first amplifier and the filter for reducing return loss of the microwave signal processor. The second attenuator is disposed between the second amplifier and the filter for reducing return loss of the microwave signal processor. The third attenuator is electrically connected to the output of the second amplifier for reducing noise figure of the microwave signal processor and providing first and second gain compensations. The first gain compensation keeps the gain of the microwave signal processor constant under various temperatures, and the second gain compensation adjusts a nominal gain of the microwave signal processor.

Abstract: An RF transmitting device (10) includes an RF amplifier (22) formed having components formed on a common semiconductor substrate (14). RF amplifier (22) includes MOS transistors (42) and (44) and an RF choke (46) stacked between a ground node (32) and a Vdd node (36). Transistors (42) and (44) are directly connected together and are biased by a control terminal bias network (58) so that the voltages appearing across their conduction terminals are about equal. Control terminals (56) and (62) of transistors (42) and (44) are driven by in-phase versions of an RF input signal (20).

Abstract: A radio-frequency amplifier is provided. The radio-frequency amplifier includes a transistor having an input terminal, an output terminal, a control terminal, and a transconductance gm. A series-connected feed-through resistance Rf and feed-through capacitance Cf is connected in parallel with the input terminal and the output terminal of the transistor. A load resistance RL is connected to the output terminal. The control terminal of the transistor is biased at a fixed voltage. Part of the transistor noise follows the looped path through the feed-through resistor instead of passing on to the load, which reduces the noise figure of the amplifier. The value of gm, Rf and RL are chosen in a way to keep the input impedance of the amplifier matched to a well-defined signal source impedance.

Abstract: Disclosed is a gain boosting technique for use with millimeter-wave cascode amplifiers. The exemplary technique may be implemented using a 0.18 ?m SiGe process (FT=140 GHz). It has also been shown that the technique is effective for CMOS processes with comparable FT. An exemplary gain-enhanced cascode stage was measured to have higher than 9 dB gain with a 1-dB bandwidth above 6 GHz with a DC power consumption of 13 mW. In addition, one cascode stage without gain boosting may be cascaded with two gain-boosted cascode amplifier stages to implement a three-stage LNA. The measured stable gain is higher than 24 dB at 60 GHz with a 3-dB bandwidth of 3.1 GHz for 25 mW of DC power consumption. It is believed that this is the first 60 GHz LNA with a higher than 20 dB gain using a 0.18 ?m SiGe process.

Abstract: A circuit and method for protecting a radio frequency power amplifier against peak drain voltage. A detector circuit has an input connected to a drain of a power transistor of an amplification stage of the power amplifier to detect a peak drain voltage therefrom. The detector circuit outputs a protection signal when the detected peak drain voltage exceeds a predetermined reference level. A shutdown circuit is coupled to the detector circuit and inputs the protection signal therefrom. The protection signal is used to remove a gate bias of at least one amplification stage of the power amplifier. High frequency components are used in the detector and protection circuits to immediately reduce the drain voltage from one or more of the amplification stages.

Abstract: A radio frequency power amplifier, having a first amplifying transistor 103-1 and a second amplifying transistor 103-2, comprises a detection circuit 101 that detects an output power and outputs a voltage according to the output power, and a protection transistor 102, controlled by an output of the detection circuit 101, for shunting a current flowing into the base terminal of the first amplifying transistor 103-1. The influence of a circuit for protecting against output load abnormalities on RF characteristics is suppressed.

Abstract: A multi-mode RF amplifier is disclosed having high and low output power modes and two power paths. A first RF amplifier delivers power to both paths. When the multi-mode RF amplifier is biased into the high power, HP, mode, substantial power is delivered via both (first and second) paths. While in the low power, LP, mode, an RF switch is turned off, creating a high input impedance, open circuit for the first path, and effectively isolating the two paths. Therefore, power is delivered by the first RF amplifier to the second path only. The impedance presented to the output of the first RF amplifier is equal to the input impedance of the second path which may be optimally set for maximizing power added efficiency or output power in LP mode. Note that, in a preferred embodiment, even in the HP mode more power is delivered to the second power path than to the first power path.

Abstract: In a broadband communication system there are multi-stage power amplifier systems for amplifying the power of radio-frequency (RF) communication signals. Each stage of the amplifier system results in composite triple beat (CTB) distortion, and if the phase of the CTB distortions are approximately the same (i.e. are in-phase), then the amplitudes of the distortions are added (i.e. “20 dB” rule). The amplifier system of the invention includes one or more phase filters positioned in series between the power amplifier stages. The phase filters are adapted to shift the phase of the communication signals, so that the phase of CTB distortions, resulting from the amplification of the communication signals in the amplifier stages between the phase filters, are substantially different (i.e. are out-of-phase). Thus, only the power of the CTB distortions are added (i.e. “10 dB” rule).

Abstract: The present invention is a dual mode LNA that can operate in either normal mode or low-gain mode, which has been designed to maintain a constant input impedance when switching between the two modes of operation. Maintaining constant input impedance is called a dynamic match. The LNA has been designed to maintain a constant bandwidth when switching between normal and low-gain modes of operation. Also, the LNA has been designed to consume much less average current when operating in the low-gain mode.

Abstract: An ultra wideband low noise amplifier (UWB LNA) and amplification method thereof, providing a substantially achieved bandwidth extension by pole-zero cancellation and utilized to transform input impedance matching up to 50 ohm for gaining low noise figure. The ultra-wideband low noise amplifier is composed of a capacitive-feedback amplifier, a resistive-feedback amplifier, an inductive-feedback amplifier, and a buffer amplifier.

Abstract: A differential transimpedance amplifier (TIA) circuit comprises first, second, third, fourth, fifth and sixth transconductance amplifiers having an input, an output and first, second, third, fourth, fifth and sixth transconductance gains, respectively. A first resistance communicates with said third transconductance amplifier and with said second transconductance amplifier. A second resistance communicates with said third transconductance amplifier and said third transconductance amplifier. A third resistance communicates with said sixth transconductance amplifier and said fifth transconductance amplifier. A fourth resistance communicates with said sixth transconductance amplifier and with said sixth transconductance amplifier. A fifth resistance communicates with said third transconductance amplifier and said fourth transconductance amplifier. A sixth resistance communicates with said sixth transconductance amplifier and said first transconductance amplifier.

Abstract: A radio frequency power amplifier 1 includes a former-stage transistor 2, a latter-stage transistor 3, and an inter-stage matching circuit 4 for connecting the former-stage transistor 2 and the latter-stage transistor 3. The inter-stage matching circuit 4 includes a high-pass filter circuit including a transfer line m1, a capacitor C1 and a capacitor C2; and a transfer line m2 with which a passage phase of a secondary harmonic signal is 15 degrees or greater.