Abstract: An ultra wideband low noise amplifier (UWB LNA) and amplification method thereof, providing a substantially achieved bandwidth extension by pole-zero cancellation and utilized to transform input impedance matching up to 50 ohm for gaining low noise figure. The ultra-wideband low noise amplifier is composed of a capacitive-feedback amplifier, a resistive-feedback amplifier, an inductive-feedback amplifier, and a buffer amplifier.

Abstract: A method and a low noise amplifier are provided such that the low noise amplifier has a power dissipation that is adaptive to the noise interference levels. The low noise amplifer includes (i) first, second and third differential amplifiers connected in series each having a terminal for receiving a power supply current; and (ii) first and second switches responsive to a control signal, the first and second switches configured such that, (a) when the control signal is in a first state, the first switch and the second switch enable independent currents to flow in the terminals for receiving a power supply current; and (b) otherwise, the first switch and the second switch enable the terminal for receiving a power supply current of the second differential amplifier to reuse a current provided to the terminal for receiving a power supply current of the third differential amplifier. The control signal is provided by a radio frequency noise power detector, which senses an output signal of the low noise amplifier.

Abstract: An amplifier comprises a carrier amplifier which performs signal amplification at all times, a peak amplifier which operates only at a time when the high electric power is outputted, a combiner which combines the output from the carrier amplifier and the peak amplifier, and a distributor which distributes an input signal to the carrier amplifier and the peak amplifier. The carrier amplifier and the peak amplifier are included in a single package transistor.

Abstract: An H.F. power amplifier is disclosed having a plurality of branches (10, 11, 12) switched in parallel. Each branch comprises a plurality of amplifier elements (T1, T4) switched in series. Resistors (R2, R5) enable the voltage (U_DS) applied to the amplifier elements (T1, T4) to be set at a fraction of a supply voltage (Ud) applied to the branches (10, 11, 12). Capacitors (C2, C4) are used to adjust the source impedance of the amplifier elements (T2, T4). In order to prevent the gate-drain voltage (U_GD) from exceeding the breakdown voltage of an amplifier element (T1, T4) and damaging the amplifier element (T1, T4), a limiting path (7) is connected according to the invention between the gate terminal (G) and the drain terminal (D) of the amplifier element (T1, T4), the limiting path (7) being switchable between a conducting state and a blocking state depending on the gate-drain voltage (U_GD).

Abstract: An amplifier circuit responsive to a power mode signal improves efficiency at low power levels without compromising efficiency at high power levels. At low power levels, high impedance is presented with suitable adjustment in the phase of the signal. Also, providing for predistortion linearization improves high power efficiency and switching the predistortion linearizer OFF at low power levels contributes little more than a small insertion loss. The power amplifier also uses a bias circuit incorporating a dual harmonic resonance filter to provide high impedance at a fundamental frequency and low impedance at a second harmonic. These properties are of particularly advantageous since amplifiers in cell-phones are used in low power modes most of the time although they are designed to be most efficient at primarily the highest power levels.

Abstract: In a high frequency power amplifier circuit that supplies a bias to an amplifying FET by a current mirror method, scattering of a threshold voltage Vth due to the scattering of the channel impurity concentration of the FET, and a shift of a bias point caused by the scattering of the threshold voltage Vth and a channel length modulation coefficient ? due to a short channel effect are corrected automatically. The scattering of a high frequency power amplifying characteristic can be reduced as a result.

Abstract: Methods and systems for amplifying signals are provided. Embodiments include a three-to-one multiplexer, a multiband RF variable gain amplifier (VGA), a multiband power amplifier driver (PAD), and a one-to three multiplexer. The three-to-one multiplexer receives three input signals from an RF frequency source and outputs an output signal corresponding one input signal. The multiband RF VGA receives the output signal of the three-to-one multiplexer, provides a first level of amplification to the signal received from the three-to-one multiplexer, and outputs an amplified version of the signal. The multiband PAD receives the signal output by the multiband RF variable gain amplifier and provides a second level of amplification to the signal and outputs an amplified version of the signal. The one-to-three multiplexer receives a signal output by the multiband PAD produces three output signals that correspond to each of the three input signals.

Abstract: An apparatus comprising a Darlington transistor pair comprising a first transistor and a second transistor. The first transistor may have a gate configured to receive an input signal. The second transistor may have a gate coupled to a source of the first transistor. The Darlington transistor pair may be configured to generate an output signal at a drain of the first transistor and a drain of the second transistor in response to the input signal. The first transistor may be implemented as an enhancement mode device and the second transistor may be implemented as a depletion mode device.

Abstract: There are provided an RF power amplifier transistor (2), a bias supply circuit (51) which supplies a bias current to the base of the RF power amplifier transistor and a bias control circuit (52) connected between the base of the RF power amplifier transistor and bias supply circuit, and the bias control circuit is connected to the power supply (32) of the RF power amplifier transistor, thus realizing high efficiency of the RF power amplifier when the power level is low and improving the temperature characteristic of the power amplifier when the power level is low.

Abstract: Provided is a power amplifier of a low-power consumption system that has linearity at a peak output power while increasing efficiency in a most frequently used range, and thereby enables a battery to last longer. The power amplifier includes an input impedance matcher for impedance-matching a signal input from the outside; a high-power amplifier and a low-power amplifier for amplifying the signal having passed through the input impedance matcher; an amplification controller controlling the high-power amplifier and low-power amplifier according to the power level of the input signal; an output impedance matcher for impedance-matching the signal amplified by the high-power amplifier and low-power amplifier; and a dynamic voltage supplier for supplying the low-power amplifier with a variable driving voltage. With the constitution set forth above, linearity at peak output power is maintained, and efficiency increases in the most frequently used range, thereby enabling the battery of a handheld to last longer.

Abstract: An amplifier circuit for amplifying a high-frequency input signal comprises an amplifier stage, which amplifies the high-frequency input signal as a function of an operating point of the amplifier stage and generates an operating point-dependent signal, an observer stage, which replicates the amplifier stage and generates an observation signal, a regulator, which is supplied with the operating point-dependent signal and the observation signal, and an control element, which influences the operating point of the amplifier stage and is driven by the regulator, whereby the regulator drives the control element in such a way that the operating point of the amplifier stage is substantially independent of a level of the high-frequency input signal.

Abstract: A multistage amplifier and design method are disclosed. The multistage amplifier has a plurality of amplifier stages, each stage having an amplifier designed and biased to operate at or near the amplifier's power added efficiency (PAE) peak. The PAE peak of each of the amplifier is at or near the amplifiers linear-compression transition region, providing a multistage power amplifier that is power efficient and has desirable amplitude to amplitude and amplitude to phase power transfer characteristics. The amplifier is designed by matching the output impedance of a final stage with a load. Amplifier stages are iteratively designed from the last stage to the first. At each stage, an amplifier and drive circuit are designed. The drive circuit and amplifier are designed to provide each stage with output impedance matched to the input impedance of the following stage and to operate at or near the PAE peak of the amplifier.

Abstract: Out-of-range conditions are detected in amplifier CMOS or BiCMOS circuitry that includes a control transistor (MS) connected in series with a cascode transistor (MSC), and a differential amplifier (A1) with an inverting input connected to the node between the control transistor and the cascode transistor, a non-inverting input connected to a reference voltage source (VRDS) and an output connected to the gate of the cascode transistor (MSC). The voltage at the output of the differential amplifier (A1) is monitored, and an error condition is determined when the voltage exceeds or drops below a predetermined threshold value. The invention considerably widens the useful operating range, without requiring sophisticated or complex detection circuitry.

Abstract: Disclosed herein is a power amplifier which is used in a wireless communication system and is capable of improving efficiency in an entire output power range and extending the dynamic range without additional switches, by including a drive amplification unit and a power amplification unit, connecting the drive amplification and the power amplification unit to a matching circuit, and a power coupler included in a transmission line transformer such that the drive amplification unit drives the power amplification unit, or directly outputs power to an output terminal, through the transmission line transformer, that is, the output power of the drive amplification unit is outputted to a load by switching on/off the power amplification unit and the drive amplification unit.

Abstract: There are provided a power amplifying transistor, a bias circuit which supplies a bias current to the base of the power amplifying transistor, a current mirror circuit which detects a peak value of the collector voltage of the power amplifying transistor, and a control circuit which, when the peak value of the collector voltage becomes higher than a voltage set in advance, controls the bias circuit to increase the bias current.

Abstract: A signal processing system and method utilizes a multi-stage amplifier to amplify an input signal. The multi-stage amplifier uses a mixed set of voltage rails to improve the operating efficiency of at least one of the amplification stages while allowing other amplification stages to operate in a predetermined operating mode. Efficiency of at least one of the stages is improved by supplying at least one variable voltage rail to an amplification stage of the multi-stage amplifier. The variable voltage rail varies in response to changes in an input signal voltage to the amplification stage. Accordingly, at least one amplification stage utilizes a variable voltage rail, and all amplification stages are supplied with a set of voltage rails that provides sufficient input signal headroom, thus, providing amplification stage efficiency and adequate voltage to allow operation of all amplification stages.

Abstract: Power amplifier circuits which constitute an RF power module used for a digital device capable of handling high frequency signals in two frequency bands are disposed over the same IC chip. The power amplifier circuits are disposed around the IC chip, and a secondary circuit is disposed between the power amplifier circuits. Thus, the power amplifier circuits are provided within the same IC chip to enable a size reduction. Further, the distance between the power amplifier circuits is ensured even if the power amplifier circuits are provided within the same IC chip. It is therefore possible to suppress the coupling between the power amplifier circuits and restrain crosstalk between the power amplifier circuits.

Abstract: The invention provides an amplifying circuit for reducing electric power consumption at a standby mode time. Therefore, in DMOS and NMOS transistors constituting a cascode amplifier, the gate of the DMOS transistor of an initial stage is biased to a grounding voltage through a resistor, and the source of the DMOS transistor is connected to the output side of an inverter through an inductor. When a control signal is set to a level “H”, the output of the inverter becomes a level “L”, and the DMOS transistor attains a turning-on state and a sufficient operating electric current is flowed to the cascode amplifier. Thus, an input signal is amplified and is outputted as an output signal. In contrast to this, when the control signal is set to the level “L”, the output of the inverter becomes the level “H”, and the DMOS transistor attains a turning-off state and the operating electric current of the cascode amplifier is stopped.

Abstract: An adaptive tuning circuit to maximize the output signal amplitude of a band-pass amplifier, comprising a control circuit to tune the peak frequency of the amplifier by monitoring the change in the output signal amplitude over two successive time sampling intervals. In some embodiments, the control circuit comprises an envelope detector and a switched capacitor circuit to provide voltages indicative of the difference in the output signal amplitude over two successive time intervals. Other embodiments are described and claimed.

Abstract: By using a radio-frequency power amplifier which turns off an Nth stage radio-frequency amplifying transistor when the level of radio-frequency output power falls below a predetermined value, it is possible to improve the linearity when the level of the radio-frequency output power is so low.

Abstract: Satellite set-top boxes (STB) are increasingly being designed with multiple tuners, making them capable of receiving more than one program at a time. In addition, satellite STBs are increasingly being designed with multiple inputs, to permit reception of additional channels that will not fit within the conventional satellite intermediate frequency (IF) band (950-2150 MHz). Often, the STB must route these multiple inputs to the multiple tuners with some form of switching function, to allow each tuner to receive all channel bands. Accordingly, the invention includes an RFIC with two RF inputs and three RF outputs, and a crossbar switch that can route any input to any output. The two inputs are amplified by low-noise amplifier stages.

Abstract: Embodiments of the present invention include circuits and methods with wide bandwidths. In one embodiment, parasitic capacitances of the output of a first stage and the input of a second stage are included in a network. The output of the first stage is coupled to the input of the network, and the input of the second stage is coupled to an intermediate node of the network. In one embodiment, the parasitic capacitance of the second stage is the largest capacitance in the network.

Abstract: A method and system to use voltage isolated and floating differential output amplifiers wired in series and parallel to achieve arbitrary output drive voltage and current for the applications load. A second embodiment uses multiple matched voltage-isolated and floating differential output amplifiers in a single chassis to enable selection between a multi-channel amplifier and a high current and/or high voltage mono amplifier. A third embodiment uses a step-up transformer and paralleled unity-gain buffer amplifiers, on input and/or output stages, to produce a zero feedback, high performance, high drive amplifier. A fourth embodiment uses a high voltage unity-gain driver amplifier to bias a unity-gain buffer amplifier and its power supply to achieve an ultra low distortion high voltage buffer amplifier. A fifth embodiment uses multiple voltage-isolated and linearized devices to enable dynamically modifiable, Class A, Class B, and Class AB topologies of predetermined voltage and current performance.

Abstract: Low distortion is implemented even in a high input level, and a smooth change in gain is maintained. A first amplifier (10) with high gain and low noise that can be gain-controlled by a first gain control signal, and a second amplifier (20) with low gain and low distortion that can be gain-controlled by a second gain control signal are provided, and a third amplifier (30) is further coupled with an outputs of the first and the second amplifiers (10, 20). An input terminal of the first amplifier (10) and an input terminal of the second amplifier (20) are coupled with each other, and an output terminal of the first amplifier (10) and an output terminal of the second amplifier (20) are coupled with each other. The output of the first amplifier (10) is then turned on or off by a mode switching signal. A change in gain resulting from turning on and off the first amplifier (10) is corrected by the third amplifier (30).

Abstract: An amplifier has a main amplifier circuit with multiple amplification stages, including a driving stage and an auxiliary amplifier circuit with multiple amplification stages, including a driving stage. A splitter circuit splits an input signal to provide path asymmetry in splitting the input signal between the main amplifier path and auxiliary amplifier path. The driving stage of the auxiliary amplifier circuit has a power rating higher than the power rating of the driving stage of the main amplifier circuit to provide a gain asymmetry in the amplifier circuit paths.

Abstract: A circuit having multiple overlapped feedback loops for DC offset cancellation is provided with applying in one of multistage amplifier, multistage filter, and the combination thereof. The circuit includes a plurality of negative feedback variable bandwidth switches coupled to each stage of the above mentioned multistage devices, the output of the last stage is coupled to an input of a low-pass filter loop. The circuit includes a plurality of variable gain amplifiers, output of each variable gain amplifier is coupled to the series contact of each stage respectively, and input of each variable gain amplifier is thereof coupled to an output of the low-pass filter loop. Therefore, the circuit achieves to cancel the DC offset for multistage overlapped feedback path with less area and low power consumption.

Abstract: An auto-range current mirror circuit has a current sensing circuit, a front and rear stage current mirrors each has an adjustable amplifying rate. The current sensing circuit presets a threshold current and has an input current of the front stage current mirror. The current sensing current compares the input current with a threshold current and then outputs a controlling signal to the front and rear stage current mirrors to adjust a suitable amplifying rate. Therefore, a bias current of the rear stage current mirror is amplified by the suitable amplifying rate to improve the quality of output current of the rear stage current mirror.

Abstract: A generalized amplifier architecture is described which employs noise-shaping feedback, and for which the output waveform closely resembles the input waveform.

Abstract: Provided is a power amplifier which fits to a deep-submicron technology in radio frequency wireless communication. The power amplifier includes a cascode including a first transistor which receives and amplifies an input signal, and a second transistor which is connected to the first transistor in series and operated by a DC bias voltage; a third transistor which is connected between the cascode and an output end, operated by a dynamic gate bias and outputting a signal; and a voltage divider which includes first and second capacitors that are connected between the output end, i.e. a drain of the third transistor, and a ground in series, and provides the dynamic bias to a gate of the third transistor.

Abstract: Power amplifier circuits which constitute an RF power module used for a digital device capable of handling high frequency signals in two frequency bands are disposed over the same IC chip. The power amplifier circuits are disposed around the IC chip, and a secondary circuit is disposed between the power amplifier circuits. Thus, the power amplifier circuits are provided within the same IC chip to enable a size reduction. Further, the distance between the power amplifier circuits is ensured even if the power amplifier circuits are provided within the same IC chip. It is therefore possible to suppress the coupling between the power amplifier circuits and restrain crosstalk between the power amplifier circuits.

Abstract: A system for efficient power amplification of an electromagnetic signal includes a switchplexer having at least two inputs and an output. The switchplexer may be configured to provide communication between a selected switchplexer input and the switchplexer output. The system also may include two or more amplifier stages, each having an input and an output, and one or more output matching circuits. Each of the output matching circuits may include an input in communication with one of the amplifier stage outputs, as well as an output in communication with one of the switchplexer inputs. A control unit may be configured to control selection of the selected switchplexer input and to selectively activate at least one of the amplifier stages.

Abstract: A radiofrequency amplifier device includes a transconductor stage having an input for receiving a radiofrequency signal, and a cascode stage connected to the output of the transconductor stage. The device also includes an auxiliary radiofrequency amplifier compensation stage connected as a negative-feedback loop between the output of the transconductor stage and the base or the gate of the cascode stage.

Abstract: An amplifier circuit includes a feedback loop; a former stage amplifier unit coupled to an input node of the amplifier circuit and the feedback loop for amplifying the difference between an input signal received from the input node and an output signal which comes back through the feedback loop, and outputting a first output signal; a compensating amplifier unit coupled to the former stage amplifier unit for amplifying the first output signal and outputting a second output signal; and an output stage amplifier unit coupled to the compensating amplifier unit and the feedback loop for outputting a third output signal according to the second output signal.

Abstract: Systems and methods are disclosed for providing automatic gain control of a multi-stage system. A method can include defining at least one parameter that is adapted to at least one of maximize hardware capacity of each of a plurality of gain stages and mitigate part-to-part variations of the multi-stage system. An order is selected for training the plurality of stages based on relative noise dominance for the plurality of stage. For a given stage of the plurality of stages, which is selected according to the selected order, output signals of the multi-stage system are measured over a plurality of gain settings for the given stage. A gain setting of the given stage of the multi-stage system also is configured based on the measured output signals relative to the at least one parameter defined for the given stage. The plurality of gain stages can include an analog equalizer as well programmable gain amplifiers connected in series.

Abstract: A flip around amplifier circuit is provided that includes an amplifier having first and second amplification stages, a Miller capacitor, and a resistive element in series with the Miller capacitor, where an output line of the second amplification stage can be coupled to an output line of the first amplification stage through the Miller capacitor and the series resistive element. The circuit can include a feedback capacitor having a first plate coupled to an input line of the amplifier, and a flip around switch that can be operated so as to connect an output line of the amplifier to a second plate of the feedback capacitor. The circuit's classical transfer function can include a zero associated with the Miller capacitor and the series resistive element, and a pole associated with the feedback capacitor and the on-resistance of the flip around switch, where the zero is substantially equal to the pole.

Abstract: In some embodiments, an apparatus includes an amplifier circuit and a bias circuit coupled to the amplifier. The amplifier circuit includes an input port and an output port, an input port circuit element coupled to the input port, an output port circuit element coupled to the output port, and an internal signal path to couple the input port circuit element to the output port circuit element. The output port is coupled to the input port, the bias circuit, and the internal signal path.

Abstract: An amplifier arrangement is provided having a first differential amplifier stage and a second differential amplifier stage, which are connected to one another with negative feedback. The second differential amplifier stage has a first voltage divider that is connected to the controlled path of the second differential amplifier stage and has at least two signal taps. The second differential amplifier stage also has a second voltage divider with at least two signal taps. Furthermore, a switching device is provided, and is connected to the at least two signal taps of the first voltage divider and to the at least two signal taps of the second voltage divider. The switching device is used to connect one of the at least two signal taps of the first voltage divider to a first output tap of the amplifier arrangement, and one of the at least two signal taps of the second voltage divider to a second output tap of the amplifier arrangement. The overall input impedance can thus be adjusted in a suitable preferred manner.

Abstract: This invention controls and modulates switched-mode power amplifiers to enable the production of signals that include amplitude modulation (and possibly, but not necessarily, phase modulation), the average power of which may be controlled over a potentially wide range.

Abstract: Receiver comprising a cascade of first to N resonance amplifiers (SA1, SA2, SA3), an output thereof being coupled to signal processing means (TO, SD, PK, LP1, S) for deriving a baseband modulation signal. To improve the signal to noise ratio said cascade is included in an RF input stage of the receiver for a distributed selective amplification of an RF reception signal, preferably with an impedance level of the individual resonance amplifiers within said cascade of first to N resonance amplifiers increasing in signal downstream direction.

Abstract: A transimpedance amplifier circuit includes a first amplifier with an input, an output and a first transconductance. A second amplifier has an input that communicates with the output of the first amplifier, an output and a second transconductance. A first resistance has one end that communicates with the input of the first amplifier. An inverter has an input that communicates with the output of the second amplifier and an output that communicates with an opposite end of the first resistance. A second resistance has one end that communicates with the input of the second amplifier and an opposite end that communicates with the output of the second amplifier. A third resistance has one end that is connected to the output of the second amplifier. A first capacitance has one end that communicates with the one end of the first resistance and an opposite end that communicates with the opposite end of the first resistance.

Abstract: Provided is a power amplifier which fits to a deep-submicron technology in radio frequency wireless communication. The power amplifier includes a cascode including a first transistor which receives and amplifies an input signal, and a second transistor which is connected to the first transistor in series and operated by a DC bias voltage; a third transistor which is connected between the cascode and an output end, operated by a dynamic gate bias and outputting a signal; and a voltage divider which includes first and second capacitors that are connected between the output end, i.e. a drain of the third transistor, and a ground in series, and provides the dynamic bias to a gate of the third transistor.

Abstract: In a high frequency power amplifier circuit in which bias voltages are applied to the transistors for amplification by current mirroring, this invention enables preventing waveform distortion near the peak output power level by allowing sufficient idle currents to flow through the transistors for amplification, while enhancing the power efficiency in a low output power region. The power amplifier includes a detection circuit comprising a transistor for detection which receives the AC component of an input signal to the last-stage transistor for amplification at its control terminal, a current mirror circuit which mirrors current flowing through that transistor, and a current-voltage conversion means which converts current flowing in the slave side of the current mirror circuit into a voltage.

Abstract: Principles of the present invention provide improved amplifiers such as low-noise amplifiers. While such amplifiers may be suitable in many applications, such amplifiers may provide improved noise, gain and stability performance at millimeter-wave frequencies. In a first aspect of the invention, an amplifier includes a first amplifying stage including a common-base transistor, and a second amplifying stage, coupled to the first amplifying stage, including a cascode transistor pair. The amplifier may be implemented in accordance with a silicon-based technology (e.g., silicon germanium) and may employ microstrip shunt-stub transmission lines as matching networks.

Abstract: The present invention, generally speaking, provides an RF power amplifier that exhibits high PAE at high output powers. The design of the power amplifier is based on the observation that the switching transistor is controlled by either voltage (for a FET) or current (for bipolar transistors), but not both. Thus, it is not necessary to develop power from the driver amplifier in order to operate the final stage as a switch. This recognition runs exactly counter to conventional wisdom, i.e., the concept of impedance matching for interstage design of high efficiency power amplifiers. It is impossible to develop solely a voltage waveform or a current waveform in a passband (resonant) network such as an RF power amplifier—both voltages and current must exist. In accordance with one aspect of the invention, however, instead of maximizing power transfer, power consumption is reduced while maintaining the magnitude of the voltage (or current) waveform.

Abstract: A method for cascading a first amplifier stage and a second amplifier stage includes coupling the output terminal of the first amplifier stage to the power supply reference point of the second amplifier stage, modulating the power supply reference point of the second amplifier stage using the output current of the first amplifier stage, and generating a final output voltage at the output terminal of the second amplifier stage having a first voltage value relative to the power supply reference point of the first amplifier stage. The first voltage value is the sum of the output voltage of the first amplifier stage relative to its own power supply reference point and the output voltage of the second amplifier stage relative to its own power supply reference point. In one embodiment, the power supply reference point is the ground reference of the power source in the amplifier stage.

Abstract: A plurality of variable gain amplifier stages are coupled by an attenuation circuit that receives a voltage input to be amplified. A control circuit activates each of the variable gain amplifier stages in a seamless manner in accordance with a control signal applied to a voltage control node, while maintaining no more than one of the stages active at any time. Fractions of the reference signal voltage level are set to define boundaries between control voltage level ranges of the amplifier stages. A unique control voltage level range is thus established for each amplifier stage. A control voltage hysteresis range can be provided to avoid oscillations between stages at the transition voltages.

Abstract: A power amplifier includes amplifier stages. An amplifier stage includes a transistor, and at least one amplifier stage comprises a driver stage. The amplifier stages include a first amplifier stage having a first transistor and associated with a first output power, and a second amplifier stage having a second transistor and associated with a second output power. A current sharing coupling couples the first amplifier stage and the second amplifier stage. The first amplifier stage and the second amplifier stage share a current through the current sharing coupling. The current sharing coupling facilitates scaling of the first output power and the second output power.

Abstract: A low distortion amplifier. The novel amplifier includes a first transistor Q1 having first and second output terminals and an input terminal adapted to receive an input signal, and a second transistor Q2 having first and second output terminals and an input terminal adapted to receive a signal from the first output terminal of Q1, wherein the second output terminal of Q1 is connected to the second output terminal of Q2 in order to eliminate a nonlinear current component in Q2. In an illustrative embodiment, the amplifier also includes a cascode Darlington pair Q3, Q4 for holding the second output terminals of Q1 and Q2 at a desired voltage to further reduce distortion and to maintain a wide bandwidth.

Abstract: Methods of and apparatus for distributing power and biasing RF PAs. A power distribution network includes a pre-final amplifier stage power distribution network and a final amplifier stage power distribution network. The pre-final amplifier stage power distribution network includes one or more pre-final amplifier stage power distribution branches, which may be configured to distribute power from one or more pre-final amplifier power supplies to one or more pre-final amplifier stages. Each pre-final amplifier stage power distribution branch comprises a ? C-R-C network coupled to an inductive load. A final amplifier stage power distribution network is configured to distribute power from a final amplifier stage power supply to a final stage of the amplifier circuit.

Abstract: A power amplifier with a multi-mode digital bias control circuit is provided. The power amplifier utilizes a complementary reference voltage generation circuit and a bias current-control circuit to generate a plurality of bias current levels for different output power levels. In an embodiment of the present invention, the power amplifier circuit is connected to a reference voltage and two control signals. Depending on the desired output power level, the control signals set the corresponding bias current in the amplifying transistors, to ensure sufficient linearity. The power amplifier is capable of operating at a very low quiescent current level, for example, 5 mA. As a result, a significant improvement in the power amplifier's overall efficiency is achieved, and the battery talk time of a wireless communication device is increased. The invention finds application in wireless communication devices such as CDMA, WCDMA, EDGE and WLAN mobile devices.