Abstract: There is provided a system for comparing the phase characteristics of three generated clock signals, each having a unique phase relationship with an original clock signal, with the original clock signal and to select a signal based on the proximity of the phase characteristic of the three signals to the original signal. The selection of a clock signal that most closely approximates the original significantly reduces lock time when attempting to synchronize an internal clock with an external clock. Additionally, there is provided a method for comparing three clock signals with an original clock signal and selecting from the three clock signals one that is approximately in phase with the original clock signal.

Abstract: An auto trimming oscillator includes a Successive Approximation Register (SAR), a frequency detector and an n-bit comparator. The SAR is used to iteratively trim the oscillator output clock frequency based on a difference between a reference clock frequency and the oscillator output clock frequency. The oscillator is trimmed to deliver a clock frequency which is a closest match to the reference clock frequency.

Abstract: A phase-locked loop circuit having a dual-reference input and a phase detector. The dual-reference input is configured to accept both a rising edge of an input clock having a first phase and a falling edge of the input clock having a second phase. The phase detector is coupled to the dual-reference input and is configured to produce a center phase signal based upon and centered in phase between the first and second phases. The phase detector is further configured with a feedback loop to adjust any tracking error and provide a tracking output signal. The phase detector system maintains both a high tracking bandwidth and a bounded jitter amplification based as a result of the dual reference signal. The high tracking bandwidth and the bounded jitter amplification are independent of an applied loop gain.

Abstract: An optical transmission apparatus according to the present invention connects a terminal apparatus side in which a transmission line is formed by, for example, SONET/SDH, and a WDM side in which a transmission line is formed by, for example, OTU3. The optical transmission apparatus according to the present invention includes a selector that, when an input signal is interrupted or switched, controls a PLL unit so as to switch and obtain a clock signal of a predetermined frequency oscillated by an OSC, corresponding to a frequency of a clock signal of the input signal before being divided to input into the PLL unit, as a clock signal to generate a PLL reference frequency.

Abstract: A signal processing module with a timing comparator such as a time to digital converter is provided. The module may be part of a phase locked loop with a fractional frequency divider that acts to produce a divided down signal modulated with jitter in its timing. The timing comparator comprises an error cancellation stage (30, 24.1, 2060) to remove a predicted effect of the imparted jitter from the timing comparator output signal. A jitter detector (80, 1046, 2064) is used to detect the jitter from the comparator output signal, preferably residual jitter after the predicted effect of the jitter has been removed. Synchronous detection, such as correlation with the predicted jitter may be used to detect the jitter. The jitter detector (80, 1046, 2064) adjusts a calibration factor of the timing comparator dependent on the detected jitter.

Abstract: A charge pump circuit includes at least one switching transistor and a level-shifter. The level-shifter has a cross-coupled pair of transistors. The level-shifter shifts a voltage of a first input signal to generate a level-shifted signal. The level-shifted signal controls a conductive state of the switching transistor to regulate an output voltage of the charge pump. A feedback loop circuit includes a detector and a charge pump. The detector compares an input signal to a feedback signal to generate first and second output signals. The charge pump includes at least two thin-oxide switching transistors and a level-shifter in another embodiment. The level-shifter shifts a voltage of the first output signal of the detector to generate a level-shifted signal. The two switching transistors are driven by the level-shifted signal and the second output signal of the detector to regulate an output voltage of the charge pump.

Abstract: A digital PLL frequency synthesizer characterized by fast-locking and low-jitters is presented. The PLL comprises a phase detector, a controllable oscillator, a loop filter having an automatically-adjusted loop gain, a feedback phase integration circuit, and a reference phase integration circuit. Fast-locking is achieved by dynamically adjusting forward-path gain and integral-path gain according to the output of the phase detector and the output of the integral-path during phase tracking. A skew-compensated counter circuit is proposed, which incorporates an asynchronous counter, a data register and a sample phase generator and features high-speed and low-power operation.

Abstract: An object is to provide a PLL having a wide operating range. Another object is to provide a semiconductor device or a wireless tag which has a wide operating range in a communication distance or temperature by incorporating such a PLL. The semiconductor device or the wireless tag includes a first divider circuit; a second divider circuit; a phase comparator circuit to which an output of the first divider circuit and an output of the second divider circuit are provided; a loop filter to which an output of the phase comparator circuit is supplied and in which a time constant is switched in accordance with an inputted signal; and a voltage controlled oscillator circuit to which an output of the loop filter is supplied and which supplies an output to the second divider circuit.

Abstract: A voltage controlled oscillator comprising first and second differential delay cells. The first differential delay cell has a first control voltage input terminal. The second differential delay cell is coupled to the first differential delay cell in a loop and has a second control voltage input terminal. The second voltage input terminal is disconnected from the first voltage control input terminal. The first voltage control input terminal receives a first voltage signal, and the second voltage control input terminal receives a second voltage signal different from the first voltage signal.

Abstract: The present relates to a fractional-N frequency synthesizer improving noise characteristics and a method thereof.

Abstract: A phase locked loop circuit is provided comprising a voltage controlled oscillator (VCO), frequency divider, phase frequency detector (PFD), charge pump, waveform generator, loop filter, switching circuit, and lock detector. The VCO generates an oscillation signal. The frequency divider multiplies the frequency of the oscillation signal. The PFD compares the frequency-multiplied oscillation signal and an externally inputted reference signal to generate an error signal. The charge pump generates a signal according to the error signal. The loop filter controls the VCO to modulate the frequency of the oscillation signal and generate a spread spectrum clock based on the signal of the charge pump or waveform generator. The lock detector controls the switching circuit to selectively connect the charge pump to the loop filter during a non-lock state and the waveform generator to the loop filter during a lock state.

Abstract: A phase locked loop includes a digital controlled oscillator and a number of phase detectors, each having a first input connected to a reference source and a second input coupled to the output of the digital controlled oscillator, and an output for producing a phase error signal. A loop filter coupled to the output of each phase detector has an output and a feedback input. An adjustment unit for derives an adjustment signal for the digital controlled oscillator from one or more of the loop filters by selecting or combining output signals from the loop filters taking into account the stability of said reference sources. The adjustment signal for the digital controlled oscillator produced by the adjustment unit is coupled to each of the feedback inputs of the loop filters. This arrangement results in hitless reference switching.

Abstract: A digital phase detector is provided that can be easily implemented in gate array or FPGA, to accurately quantize a phase difference of two clocks and convert to a digital value without using delay elements. The digital phase detector includes: a multiplier for, when two clocks have frequencies close to an integer ratio, receiving a first clock and multiplying by M/N; F/F for latching a second clock by an output clock of the multiplier; a differential circuit for differentiating an output of the F/F; a counter for receiving the output clock of the multiplier; a latch circuit for holding an output of the counter according to an output of the differential circuit; a first adder for adding an output of the latch circuit; a second adder for subtracting an output of the first adder from a fixed value; and an accumulator for sequentially integrating an output of the second adder.

Abstract: A frequency synthesizer includes a fractional N phase locked loop (PLL), a sigma delta modulator, a phase adjustor and an adjust signal generator. The fractional N PLL generates an output signal according to an adjusted reference signal. A frequency of the output signal is a multiple of a frequency of a reference signal. The fractional N PLL includes a crystal oscillator generating the reference signal and a divider frequency dividing the output signal according to the multiple to generate a feedback signal. The sigma delta modulator generates a control signal to adjust the multiple accordingly. The phase adjustor adjusts a phase of the reference signal according to an adjust signal to generate the adjusted reference signal. The adjust signal generator generates the adjust signal according to an accumulation result of the sigma delta modulator.

Abstract: A circuit includes phase detection circuitry, a clock signal generation circuit, a first frequency divider, and a second frequency divider. The phase detection circuitry compares an input clock signal to a feedback signal to generate a control signal. The clock signal generation circuit generates a periodic output signal in response to the control signal. The first frequency divider divides a frequency of the periodic output signal by a first value to generate a first frequency divided signal. The second frequency divider divides the frequency of the periodic output signal by a second value to generate a second frequency divided signal. The first and the second frequency divided signals are routed to the phase detection circuitry as the feedback signal during different time intervals.

Abstract: A design structure for a hybrid phase locked loop (PLL) circuit that obtains stabilized dynamic response and independent adjustment of damping factor and loop bandwidth is provided. The hybrid PLL circuit of the illustrative embodiments includes the resistance/capacitance (RC) filter elements of a conventional RC PLL and the feed-forward path from the output of the phase frequency detector to the voltage controlled oscillator (VCO). The hybrid PLL essentially enhances the performance of the conventional feed-forward PLL by providing the RC filter whose components can be weighted to provide a dynamic response that is significantly less sensitive to parameter variation and which allows loop bandwidth optimization without sacrificing damping.

Abstract: A phase detecting circuit includes a first node that outputs a pull-up control signal, a second node that outputs a pull-down control signal, an initializing unit that initializes voltage levels of the first and second nodes in response to a pre-charge signal, a data input unit to which receives a receiver data, a phase comparison unit that compares a phase of a receiver clock and a phase of the receiver data input to the data input unit to control the voltage levels of the first and second nodes, and a charging/discharging unit that charges or discharges electric charges that are applied to the first and second nodes.

Abstract: The invention relates to a method for carrying out a frequency change whilst retaining the phase relationship between several devices, in particular, network analyzers. Each device has at least one signal generator for stimulating an object for measurement and at least one local oscillator, connected to at least one mixer, for receiving a measuring signal obtained from the object for measurement by the superposition principle. On changing frequency, in a first step, only the frequency of the local oscillators of all devices is changed and the frequency of the signal generators of all devices remains unchanged. In a second step, only the frequency of at least one signal generator is changed and the frequency of the local oscillators of all devices remains unchanged.

Abstract: Systems and techniques to calibrate a control loop include, in at least one implementation, a system including the control loop configured to generate a clock signal and lock the clock signal to timing marks detected on a machine readable medium, a repetitive error correction module configured to receive a predicted phase and a corrected phase error for the clock signal, generate a predicted repetitive phase disturbance using the predicted phase and the corrected phase error for the clock signal, and calibrate a phase error to compensate for variations in repetitive phase errors in the clock signal using the predicted repetitive phase disturbance; and a servo track generator configured to generate servo tracks using the clock signal.

Abstract: This disclosure relates to a Phase-Locked Loop (PLL) device and a method for providing a stable free-running voltage signal to a voltage controlled oscillator.

Abstract: Apparatus and methods detect missing clock edges. An improved phase frequency detector (PFD) can be used in, for example, a phase locked loop (PLL) or a delay locked loop (DLL). Conventional PFDs can miss clock edges. Disclosed is a missing clock edge detection circuit that reliably detects these missing clock edges to correctly activate switches of a charge pump of the PLL or DLL. Embodiments exhibit relatively little of the characteristic polarity reversal of conventional PLL or DLL circuits, which then enables embodiments to operate faster and acquire phase lock quicker than conventional circuits. Such techniques are useful in clock synthesis, clock recovery, and the like. The invention can further include an optional circuit that detects when the missing clock edge detection circuit may have inaccurately determined (false positive) that a clock edge had been missed, to override the corrective action by the missing clock edge detection circuit.

Abstract: In a voltage-controlled oscillator capable of broadening a variable frequency range while suppressing increase of conversion gain, a converter (12) converts an input voltage to a first physical quantity, a variable converter (13) supplies a second physical quantity that accords with the status of each switch of a switch group (13a). another variable converter (14), when the input voltage is contained within a prescribed voltage range, supplies a third physical quantity that accords with the input voltage and the status of each switch of another switch group (14a), and a variable-frequency oscillator (15) supplies a signal of a frequency that accords with the first physical quantity, the second physical quantity, and the third physical quantity.

Abstract: A phase-locked loop circuit. The phase-locked loop circuit comprises a phase detector, a proportional charge pump, a decimator, an integral charge pimp, and a voltage-controlled oscillator. The phase detector obtains an phase error information according to a phase difference between a reference signal and a clock signal input to the phase detector. The proportional charge pump coupled to the phase detector generates a first voltage according to the phase error information. The decimator generates a decimated version of the phase error information by a decimation factor of N. The integral charge pump generates a second voltage according to the decimated version of the phase error information. The voltage-controlled oscillator generating the clock signal according to a combination of the first and second voltages.

Abstract: A frequency synthesizer includes: a frequency source generating a reference signal that includes a plurality of pulses having periodicity based on a reference frequency; a feedback loop that includes, a phase detector circuit, a loop filter, a controlled oscillator that generates an output signal at an output, and a loop divide circuit; a non-linear circuit element at an input of the phase detector circuit, which generates intermodulation distortion that causes at least one spurious signal at the output; and a controller controlling the loop divide circuit and the non-linear circuit element. The frequency synthesizer further includes a dither circuit that adjusts the timing of some of the pulses of the reference signal based on a parameter provided by the controller to the non-linear circuit element, thereby, providing a jittered reference signal to the non-linear circuit element for attenuating the at least one spurious signal at the output.

Abstract: Certain aspects of a method and system for simultaneous FM transmission and FM reception using a shared antenna and a direct digital frequency synthesizer (DDFS) may be disclosed. In a FM transceiver that receives FM signals at a frequency f1 and transmits FM signals at a frequency f2, aspects of the method may include generating via a DDFS, a signal corresponding to a difference between f1 and f2 to enable simultaneous transmission and reception of FM signals via shared antenna.

Abstract: A method for operating a micro-electro-mechanical system (MEMS) scanner on a resonant mode frequency is provided. The method includes generating a drive signal for a MEMS scanner. A sensor signal is received from the MEMS scanner. The drive signal is compared to the sensor signal. An accumulated correction signal is generated based on the comparison of the drive signal and the sensor signal. The drive signal for the MEMS scanner is then adjusted based on the accumulated correction signal.

Abstract: A phase-locked loop circuit. The phase-locked loop circuit comprises a phase detector, a proportional charge pump, a decimator, an integral charge pimp, and a voltage-controlled oscillator. The phase detector obtains an phase error information according to a phase difference between a reference signal and a clock signal input to the phase detector. The proportional charge pump coupled to the phase detector generates a first voltage according to the phase error information. The decimator generates a decimated version of the phase error information by a decimation factor of N. The integral charge pump generates a second voltage according to the decimated version of the phase error information. The voltage-controlled oscillator generating the clock signal according to a combination of the first and second voltages.

Abstract: One well known problem associated with voltage controlled oscillators or VCOs is phase noise, and it is desirable to reduce phase noise in order to improve VCO performance. Here, a VCO is provided where gain elements are provided that reduce phase noise. These gain elements are generally comprised of oscillator tanks.

Abstract: A phase-locked loop frequency synthesizer including phase detector circuitry and divider circuitry producing a divided signal. The phase detector circuitry receives a reference signal, a divided signal fed back from the divider circuitry, and generates control pulses which control a charge pump in accordance with a frequency and phase relationship between the reference signal and the divided signal. The divider circuitry has a main divider which divides an input signal by a division ratio selected from a pair of dual modules division ratios, and outputs the divided input signal as an output signal and an auxiliary divider which produces serial output data, each bit of which serves as a dual modules selection signal to cause the main divider to operate using one of the pair of dual modules main division ratios. The auxiliary divider produces the divided signal once per cycle and outputs the pulse to the phase detector circuitry.

Abstract: The present invention relates to a calibrated phase-locked loop (PLL), which has a calibration mode for measuring a tuning gain of a variable frequency oscillator (VFO) and a PLL mode for normal operation. Calibration information based on the tuning gain is used during the PLL mode to regulate a PLL loop gain. During the calibration mode, the calibrated PLL operates as a frequency-locked loop (FLL) for low frequency lock times, and during the PLL mode the calibrated PLL operates as a PLL for high frequency accuracy and low noise. By regulating the PLL loop gain, the desired noise spectrum and dynamic behavior of the PLL may be maintained in spite of variations in the operating characteristics or in the characteristics of the PLL components.

Abstract: A method and apparatus controlling the output phase of a VCO (Voltage Controlled Oscillator). The apparatus has a phase locked loop 20 having a first input 21 for receiving a reference signal and a second input 22 for receiving a feedback signal and the output for controlling of a VCO. A phase shifter 50 is provided on the feedback path between the VCO and the second input of the phase locked loop. The phase shifter is arranged for shifting the phase for feedback signal by controlled amount. The phase shifter may be a variable phase shifter for controlling and varying the amount by which the phase feedback signal is shifted.

Abstract: A method for calibrating a phase locked loop begins by determining a gain offset of a voltage controlled oscillator of the phase locked loop. The processing then continues by adjusting current of a charge pump of the phase locked loop based on the gain offset.

Abstract: A system and method of loading a programmable counter includes storing a first digital divide value in a register. The first digital divide value is then loaded from the register to a programmable counter. The method further includes writing a second digital divide value to the register at a time responsive to a time remaining to complete a counting cycle of the programmable counter.

Abstract: A discrete-time phase lock loop (DTPLL) includes an analog section comprising a digital-to-analog converter (DAC) and an oscillator, operative to provide a clock signal based on an input from the DAC. The DTPLL also includes a digital signal processor (DSP). The DSP includes a loop controller state machine; a phase detector; a counter, operative to receive clock signals from the oscillator and to provide a count value to the phase detector; a divider, operative to receive a reference signal and to provide a reference pulse output to the phase detector; and a loop filter operative to provide a control effort value based on an output from the phase detector. Based on the phase error value, an output of the oscillator is changed to reduce the phase error to a steady state value.

Abstract: An object of the present invention provides a frequency synthesizer having a broad frequency entraining range which can finely set a frequency over a broad band by a novel principle. As a specific solving means, a sinusoidal signal of an output frequency of a voltage-controlled oscillator is subjected to orthogonal detection, a vector rotating at the differential frequency (speed) between the output frequency and the frequency of the frequency signal used for the detection is created, and the frequency of a vector when the output frequency of the voltage-controlled oscillator is equal to a set value is calculated in advance. The voltage signal corresponding to the difference between the frequency of the vector and the calculated frequency is fed back to the voltage-controlled oscillator when the voltage-controlled oscillator is driven, and PLL is formed so that the difference is equal to zero.

Abstract: An improved method of cycle slip prevention in a frequency synthesizer is achieved by determining phase error between a divided VCO and reference, determining whether a phase error of a full cycle slip has occurred and in which direction and altering the phase of the VCO divided signal in the amount and direction to reduce the phase error to less than one reference cycle. The result is an improved transfer function of the PFD, proportional to the phase error in the region ?2*pi to 2*pi, and fixed close to maximum when the phase error exceeds the above interval. This invention is achieved with the addition of digital circuitry to monitor and control the PFD and the VCO divider, and does not require additional analog charge pump circuitry.

Abstract: A phase locked loop (PLL) includes a detector, a charge pump, a loop filter, a voltage controlled oscillator (VCO), a divider, and a frequency change module. The detector provides a phase difference based on a reference signal and a feedback signal. The charge pump provides a charge based on the phase difference. The loop filter provides a voltage based on the charge. The VCO provides an output signal based on the voltage received from the loop filter. The divider divides a frequency of the output signal by a value to provide the feedback signal. The frequency change module processes an input signal having a first frequency to provide a processed signal having a second frequency that is different from the first frequency. The frequency change module selects the input signal or the processed signal to provide as the reference signal to the detector. Changing the frequency of the reference signal can change a frequency of a spur.

Abstract: An embodiment of the invention provides a clock and data recovery circuit. The clock and data recovery circuit comprises a phase detector, a pre-accumulator, a register, an accumulator and a digital controlled oscillator. By using the transmission path formed by the pre-accumulator, the output of the phase detector can be transmitted to the digital controlled oscillator in advance to adjust the frequency of its output clock signal and the latency due to the accumulator can be reduced.

Abstract: An embodiment of the present invention provides a system for detecting a phase-shifted signal at high frequencies in data and clock recovery circuitry. An up-pulse generator, in one embodiment, provides output pulses having a duration exceeding the duration of input pulses upon detection of a phase-shifted signal leading the reference signal. A down-pulse generator provides output pulses having a duration exceeding the duration of input pulses upon detection of a phase-shifted signal lagging the reference signal.

Abstract: One delay circuit is inserted in open loop inside a clock recovery circuit for improving the accuracy of clock recovery. One oscillator signal ?(0) to ?(2i?1) is provided with a basic Step of Time. A rational number of Step of Time corresponding to a bit-duration is measured inside a received flow of bits. The oscillator signal ?(0) to j(2i?1) is transformed into a clock signal CK having active edges of said clock signal in phase with at least one oscillator signal ?(0) to ?(2i?1), two consecutive active edges being separated by a time duration proportional to the integer part of the number of Step of Time. A time delay is computed proportional to the fractional part of the number of Step of Time. The next active edge of the clock signal CK is delayed of said computed delay.

Abstract: There is provided an analog phase locked oscillator comprising a sampling phase detector, a loop filter, a voltage controlled oscillator, a frequency multiplier and a feedback loop where the feedback loop connects the output of said oscillator with the input of said phase detector through said frequency multiplier. The sampling phase detector is adapted to perform a discrete phase comparison between a reference frequency and the multiplied feedback signal. The voltage controlled oscillator is adapted to give out a constant frequency at a multiply of the reference frequency divided with the multiplication factor of the multiplier.

Abstract: A cosine wave over one period is stored as waveform data in a memory, and address shift values based on a phase lag in transfer characteristics from a speaker to a microphone are stored in a memory. An address shift value is read from the memory by referring to the frequency, and waveform data are read from the memory at addresses that are produced by shifting the addresses from which the reference cosine wave signal and the reference sine wave signal are read, by the address shift value. The read waveform data are used as a first reference signal and a second reference signal, which are applied to adaptive notch filters, to suppress vibratory noise.

Abstract: An integrated circuit radio transceiver and method therefor includes capacitive loop filter with selectable capacitive elements that are operable to adjust a signal level provided to a voltage controlled oscillator to control a frequency of an output signal of the oscillator. A plurality of switches are controlled by logic to define a discharge mode, a charge mode and charge sharing mode in which a plurality of capacitive elements share charge while generating the input voltage to the oscillator.

Abstract: A variance correction method includes generating a reference current depending on a resistance within a lowpass filter and outputting the reference current to a voltage controlled oscillator, and correcting characteristics of the lowpass filter and a gain of the voltage controlled oscillator based on an output clock of the voltage controlled oscillator.

Abstract: Embodiments of the invention include a method for use in a device having a local oscillator. The method includes performing, for the local oscillator that is disciplined by an external reference signal, while locked to the external reference signal, training at least two mathematical models of the oscillator to determine a predicted correction signal for each mathematical model based at least in part on a correction signal that is a function of the external reference signal and which is used to discipline drift in the oscillator. The method also includes selecting a mathematical model of the at least two mathematical models that results in a smallest time error when disciplining the oscillator to use when the external reference signal is unavailable and an alternative correction signal is to be used to discipline drift in the oscillator.

Abstract: In an ADPLL composed of a digital circuit, a technique improving phase difference detection in a vicinity of a phase difference of 0 (zero) is provided. A feedback loop comprises a PFD comparing phases and frequencies of a reference signal and a feedback signal, a TDC converting an output of the PFD into a digital value, a DLF removing a high frequency noise component from an output of the TDC, a DCO controlled based on an output of the DLF and a DIV frequency-dividing an output the DCO and outputting the feedback signal. An offset value is added at any portion of the feedback loop, a phase of the feedback signal is controlled and a value other than 0 is inputted to the TDC even when the ADPLL is locked.

Abstract: An oscillator includes a reference stage and multiple phase stages. The reference stage has a reference transistor having a gate coupled to a voltage reference and a drain coupled to a reference current source. Each phase stage includes a transistor, two current sources, a capacitor, switch, inverter, and latch. The transistor has a drain coupled to a first current source, a gate coupled to a node and a source coupled to the reference transistor's source. The capacitor and switch couple between the node and ground. The second current source couples to the node. The transistor's drain couples to the inverter's input. The inverter's output couples to the latch's set input. The latch's output couples to the switch. The inverter output also couples to the reset input of a subsequent phase stage's latch. The inverter output for a last stage couples to the reset input of a first stage latch.

Abstract: A phase lock loop (PLL) circuit is provided. A voltage controlled oscillator (VCO) generates an output clock signal based on a control voltage. A controller provides a first digital control word, a second digital control word and a loop factor. A frequency modifier is coupled to the output clock signal, controlled by the controller to divide the output clock signal by the loop factor to generate a feedback frequency. A charge pump is controlled by the up signal and down signal to generate a charge pump current, comprising a first digital to analog converter (DAC) to generate a first current based on the first digital control word when the up signal is asserted. A second DAC generates a second current based on a second digital control word when the down signal is asserted. The controller defines a first relationship between the first digital control word and the loop factor, and the controller defines a second relationship between the second digital control word and the loop factor.

Abstract: The present relates to a fractional-N frequency synthesizer improving noise characteristics and a method thereof.

Abstract: A phase comparator includes an edge detecting unit to which a reference signal is input and to which a referred signal based on the reference signal is input as a feedback signal. The edge detecting unit detects an edge of the reference signal and an edge of the referred signal. The phase comparator also includes a phase-difference detecting unit that detects a phase difference between the edge of the reference signal and the edge of the referred signal. The phase comparator also includes a phase-difference-signal output unit that outputs a phase-difference signal for current control based on the phase difference. The phase comparator also includes an input-break detecting unit that detects an input break of the reference signal when an edge of the referred signal is again detected after an edge of the referred signal is detected and before an edge of the reference signal is detected.