Abstract: Disclosed are a digital phase-frequency detector and a method of operating a digital phase-frequency detector. The detector includes an input circuit, an output circuit and a reset circuit. In use, the input circuit receives first and second input signals during a plurality of cycles, and during a given one of the cycles, generates a first intermediate signal or a second intermediate signal depending on which of the first and second input signals was received first during that given one of said cycles. The output circuit receives these intermediate signals, and outputs, during said one cycle, a first output signal or a second output signal depending on which one of intermediate signals was received by the output circuit during said one cycle. The reset circuit applies a reset signal to the input circuit under defined conditions to begin a new one of said plurality of cycles.

Abstract: In an embodiment, a circuit is provided comprising a multi-phase oscillator configured to output a plurality of output signals having the same frequency and different phase offsets. A feedback value is generated based on at least two of said output signals. A reference value is generated based on a reference clock and a predetermined value. The reference value and the feedback value are combined.

Abstract: Disclosed herein is a clock regeneration apparatus, including: an oscillator including n (an integer of two or more) gating groups connected in cascade connection to each other forming an oscillation loop, the gating groups being controlled to gate an internal clock signal with first to nth gating signals different from one another, respectively, the oscillator outputting a clock signal at least from the nth one of the gating groups; an edge detection section adapted to detect an edge of a reception data signal; a phase decision section adapted to decide a phase of the clock signal for each edge of the reception data signal and output a result of the decision as a phase decision signal; and a gating signal generation section adapted to generate the first to nth gating signals and output the gating signals to first to nth ones of the gating groups, respectively.

Abstract: The disclosure provides systems and methods for programmable fixed frequency digitally controlled oscillators for multirate low jitter frequency synthesis. The present invention utilizes a digital control element, such as a complex programmable logic device (CPLD) or field programmable gate array (FPGA), to monitor the frequency offset of a DCO with respect to one or more timing module (TM) references. The frequency offset is measured by aligning the phase of a DCO feedback divider to the phase of a reference divider, and then counting the number of pulses in the DCO between the falling edges of the feedback to determine a frequency error. Falling edge detection is used to determine a sign of the error. The digital control element then calculates a frequency correction based on a linear scaling factor to send a new control word to the DCO to reduce the frequency error.

Abstract: A phase detector includes transistors that generate first and second phase error signals. The phase detector resets the first phase error signal in response to at least one of the first and the second phase error signals through a first reset path having a maximum reset delay that is equal to or less than a sum of switching delays of three transistors in the first reset path. The phase detector resets the second phase error signal in response to at least one of the first and the second phase error signals through a second reset path having a maximum reset delay that is equal to or less than a sum of switching delays of three transistors in the second reset path.

Abstract: In a circuit having a runaway detector coupled to a phase-locked loop (PLL), the PLL may include a loop filter to receive a control voltage within the PLL and provide a filtered control voltage and a voltage-controlled oscillator to receive the filtered control voltage and provide an output clock signal. The runaway detector may provide a control signal for adjusting the filtered control voltage in response to a predetermined PLL condition. The runaway detector may include a comparator to receive a first and second input voltages, where the second input voltage is based on the output clock signal. When the predetermined PLL condition exists, the runaway detector may be active to adjust the filtered control voltage, thereby enabling the PLL to return to a lock condition.

Abstract: Described is circuitry for improving the acquisition/locking time of phase-locked loops (PLL). The circuitry includes a node for tapping voltage from a PLL, with an analog-to-digital converter (ADC) to convert the voltage to a digital signal. A memory module stores the digital signal. A digital-to-analog converter (DAC) converts the digital signal to an analog output. A comparator/threshold detector is included to compare the voltage from the node to the analog signal from the DAC. Based on the comparison, the comparator/threshold detector provides a signal to the memory module to cause the memory module to update its stored digital signal. Upon power-up, the saved voltage is forced into the PLL to force the PLL nodes to the saved values as an initial condition, thereby decreasing acquisition time in the phased locked loop.

Abstract: An oscillation frequency control circuit controls a second oscillation circuit, which generates and outputs a second clock signal of a second frequency according to a received control signal, to control the second frequency. The oscillation frequency control circuit includes a frequency difference detection circuit unit configured to detect a difference between a predetermined first frequency of a first clock signal generated by an external first oscillation circuit and the second frequency, and generate and output an output signal indicating a detection result, and a frequency control circuit unit configured to control, according to the output signal of the frequency difference detection circuit unit, the second oscillation circuit to control the second frequency of the second clock signal to make an absolute value of the difference between the first frequency and the second frequency greater than a predetermined value.

Abstract: In at least some embodiments, a communication system includes a receiver having a local oscillator (LO) for each of a plurality of frequency bands. Each LO is controlled by a separate phase-locked loop (PLL) that tracks carrier frequency offset (CFO) using a common phase error (CPE). The CPE is selectively weighted based on at least one inter-band frequency correlation (IFC) coefficient.

Abstract: An object of the present invention provides a frequency synthesizer having a broad frequency entraining range which can finely set a frequency over a broad band by a novel principle. As s specific solving means, a sinusoidal signal of an output frequency of a voltage-controlled oscillator is subjected to orthogonal detection, a vector rotating at the differential frequency (speed) between the output frequency and the frequency of the frequency signal used for the detection is created, and the frequency of a vector when the output frequency of the voltage-controlled oscillator is equal to a set value is calculated in advance. The voltage signal corresponding to the difference between the frequency of the vector and the calculated frequency is fed back to the voltage-controlled oscillator when the voltage-controlled oscillator is driven, and PLL is formed so that the difference is equal to zero.

Abstract: A frequency phase locked loop (FPLL) includes a first feedback loop coupled to a second feedback loop. The first feedback loop is configured to correct a phase offset of an output signal of the FPLL. The second feedback loop is configured to correct a frequency offset of the output signal of the FPLL.

Abstract: Aspects of a method and system for implementing a low power, high performance fractional-N PLL synthesizer are provided. The synthesizer comprises a reference generator/buffer, a charge pump, a divider, a VCO, a loop filter, and a phase-frequency detector (PFD). The reference generator/buffer may increase the frequency of the input reference signal to the PFD. The PFD may generate a single signal for controlling the charge pump utilizing the increased frequency input reference signal and a divider signal generated by the divider whose input frequency may be substantially the same as that of a VCO output signal. The single signal charges a charge up portion of the charge pump and a charge down portion is charged by a leakage current. The VCO signal may be generated based on a filtered output of the charge pump generated by the loop filter. The divider may utilize true single phase clock (TSPC) logic.

Abstract: An apparatus includes phase detection circuitry that generates control signals in response to an input clock signal and a feedback clock signal. The apparatus also includes a clock signal generation circuit that includes fine and coarse capacitors. The clock signal generation circuit changes a capacitance of the capacitors that are affecting the output clock signal in response to a change in the control signals. The apparatus also includes measurement circuitry that determines a calibration number of the fine capacitors having a combined capacitance that most closely matches a capacitance of one of the coarse capacitors.

Abstract: A clock distribution circuit, which is provided in IC that has a first sequential circuit receiving first clock through a first branch node on a first clock network, a second sequential circuit receiving second clock through a second branch node on a second clock network, and a data transfer path between the first and second sequential circuits, includes: a first PLL receiving a first feedback clock that is the first clock branched at the first branch node and outputting the first clock to the first clock network based on the first feedback clock; and a second PLL receiving a second feedback clock that is the second clock branched at the second branch node and outputting the second clock to the second clock network based on the second feedback clock. A branch node is provided at least one of between the first PLL and the first branch node and between the second PLL and the second branch node.

Abstract: A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF frequencies. The LO generation schemes presented are operative to generate I and Q square waves at a designated frequency while avoiding the well known issue of harmonic pulling. An input baseband signal is interpolated and upconverted in the digital domain to an IF. The LO operates at a frequency which is a n/m division of the target RF frequency fRF. The IF frequency is configured to ½ of the LO frequency. The upconverted IF signal is then converted to the analog domain via digital power amplifiers followed by voltage combiners. The output of the combiners is band pass filtered to extract the desired replica.

Abstract: A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF frequencies. The LO generation schemes presented are operative to generate I and Q square waves at a designated frequency while avoiding the well known issue of harmonic pulling. The signal is input to a synthesizer timed to a rational multiplier of the RF frequency fRF. The signal is then divided to generate a plurality of phases of the divided signal. A plurality of combination signals are generated which are then multiplied by a set of weights and summed to cancel out some undersired products. The result is filtered to generate the LO output signal.

Abstract: In an exemplary embodiment, a free running VCO has two modes: a normal operating mode and a calibration mode. In the calibration mode, the free running VCO is phase lock looped with itself instead of a calibration VCO. Furthermore, in an exemplary embodiment, a tuning voltage for the free running VCO is adjusted to offset any tuning error. In addition, in various embodiments a reference crystal oscillator used in the phase lock loop is located on a DSP module instead of on the RF module. In yet another exemplary embodiment, the free running VCO is the only high frequency VCO on a radio frequency module.

Abstract: A digital phase detector includes a quantization unit that quantizes a frequency of a reference signal to generate reference delay information and reference integer phase information, and quantizes a frequency of an oscillation signal to generate oscillation delay information and oscillation integer phase information. A first conversion unit converts the frequency of the reference signal into reference frequency information based upon the reference delay information and the reference integer phase information. A second conversion unit converts the frequency of the oscillation signal into oscillation frequency information based upon the oscillation delay information and the oscillation integer phase information. A calculation unit converts the reference frequency information and the oscillation frequency information into first and second phase information, respectively, and outputs a digital phase difference between the first phase information and the second phase information.

Abstract: A digital controlled oscillator including a programmable current source, a first variable capacitor and a second variable capacitor. A comparator compares the voltage across the variable capacitors with a reference voltage level and generates a DCO output clock signal. A switching means alternately switches the variable capacitors to either charge from a programmable current source or discharge in response to an output signal of the comparator. A clock divider divides the DCO output clock signal by a factor N substantially greater than 1. A frequency monitor receives the divided clock signal, determines the time difference of successive clock periods of the divided clock signal and generates a feedback signal to adapt the frequency of the DCO output clock signal.

Abstract: A novel mechanism that is operative to observe and compare the differentiated phase of the reference and variable PLL loop signals using a frequency detector. The resultant phase differentiated error is then accumulated to yield the phase error. The operation of the loop with the frequency detector is mathematically equivalent to that of the phase detector. A frequency error accumulator is used to generate the integral of the frequency error. The frequency error accumulator also enables stopping the accumulation of the frequency upon detection of a sufficiently large perturbation, effectively freezing the operation of the loop as subsequent frequency error updates are not accumulated. Upon removal of the phase freeze event, accumulation of the frequency error and consequently normal loop operation resumes.

Abstract: A mixed-mode PLL is disclosed. The mixed-mode PLL comprises an analog phase correction path and a digital frequency correction path. The analog phase correction path comprises a linear phase correction unit (LPCU). The digital frequency correction path comprises a digital integral path circuit.

Abstract: A PLL circuit which can absorb variation of phase noise characteristic due to temperature and individual difference and has a phase noise suppression characteristic stable in a wide frequency band is provided. The PLL circuit comprises, at the succeeding stage, a first register for storing a first parameter for controlling the loop gain, a first multiplier for multiplying the output of the phase comparator by a first parameter, a second register for storing a second parameter for controlling the response characteristic, a second multiplier for multiplying the output of the first multiplier by a second parameter, and a CPU for setting optimum parameters in the first and second registers depending on the use frequency band, the ambient temperature, and the device individual difference. By controlling the loop gain and the response characteristic to optimum values, a good suppression characteristic in a wide frequency band is achieved.

Abstract: A phase locked loop with a current leakage adjustment function is provided. The phase locked loop includes a phase locked loop unit having a compensation voltage node, a digitalized leakage-detection circuit generating a plurality of digital control signals based upon the phase error between a reference clock signal and a feedback signal, and a compensation circuit generating a compensation current based upon the plurality of digital control signals. When there exist current leakages of the MOS capacitors, the current leakage adjustment circuits provided by the present invention may prevent the conventional phase locked loop from un-locking due to jittering.

Abstract: A digital phase locked loop has a digital controlled oscillator, a feedback loop coupled to the output of said digital controlled oscillator, a phase detector for comparing a feedback signal from said feedback loop with a reference signal to produce a phase error signal, and a low pass filter for filtering the phase error signal for controlling said digital controlled oscillator. A bandwidth calculation unit calculates the required filter bandwidth based on the phase error. The bandwidth calculation unit then controls the bandwidth of said low pass filter, which is thus adaptively adjusted in accordance with the phase error.

Abstract: A phase locked loop circuit includes an oscillator part configured to generate a reference signal by amplifying a signal generated by an oscillator, and a phase locked loop part configured to include a filter that outputs a control signal to a clock transmitting circuit that generates a clock signal in accordance with a phase difference between the reference signal and a feedback signal, wherein a drive capability of the oscillator part is controlled in accordance with the control signal.

Abstract: An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A programmable filter is connected to receive the phase error samples and connected to provide a filtered output having a gain and a phase margin to the controllable oscillator. The programmable filter includes a proportional loop gain control having a programmable loop gain coefficient (alpha—?) and an integral loop gain control having a programmable loop gain coefficient (rho—?). Alpha and rho are configured to be programmatically changed simultaneously and are selected such that the gain is changed and the phase margin remains substantially unchanged.

Abstract: An oscillator is disclosed that is tunable to discrete values, and includes a tuning element which can be connected via a switching device. A rectifier circuit is connected to the output of the oscillator and forms a clock signal from the oscillator signal. The oscillator circuit contains a phase delay circuit having a switching input, a clock signal input which is coupled to the output of the rectifier circuit, and a switching output coupled to the switching device. The phase delay circuit has a comparison circuit for comparison of a phase of the clock signal that is applied to the signal input with a reference phase. This phase delay circuit is designed to emit a switching signal after application of an activation signal to the switching input and after the phase of the clock signal which is applied to the signal input matches the reference phase.

Abstract: In a method and apparatus for controlling damping and bandwidth in a phase locked loop (PLL), a loop filter is configured to have a dual path for charge pump current. A 3 dB bandwidth of the PLL is controlled by adjusting gain of a proportional current path. An integral current path includes a gating circuit to digitally control an amount of time an integral charge pump current received is passed through as an effective integral charge pump current. A resistor and capacitor (RC) circuit filters the proportional and effective integral charge pump currents, thereby providing a filtered input to a voltage controlled oscillator. Damping and hence peaking of the PLL is precisely controlled by sampling one of every p samples of the integral charge pump current to provide the effective integral charge pump current, p being an integer.

Abstract: A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF frequencies. The LO generation schemes presented are operative to generate I and Q square waves at a designated frequency while avoiding the well known issue of harmonic pulling. The use of analog mixers of the prior art is avoided and replaced with an XOR gate configured to generate the correct average frequency. The edges are dynamically adjusted by ±T/12 or zero based on the state of the controlled oscillator down-divided clock.

Abstract: There is provided an oscillator including: a reference signal generator that generates a reference signal having a reference frequency; a phase comparator that outputs a voltage in accordance with a phase difference between the reference signal and a feedback signal; a loop filter that receives a voltage output from the phase comparator, and gain-adjusts a voltage output from the phase comparator by means of an external control signal; a voltage controlled oscillator that oscillates an output signal at a frequency in accordance with an adjusted signal having been gain-adjusted by the loop filter; and a frequency divider that feeds back a frequency-divided signal resulting from frequency-dividing the output signal, to the phase comparator as the feedback signal.

Abstract: A frequency detection circuit and a detection method thereof suitable for a clock data recovery (CDR) circuit are provided. The frequency detection circuit includes a phase detector, a first delayer, a frequency detector, and a logic circuit. The phase detector samples a data signal according to a first clock signal provided by the CDR circuit and provides a phase instruction signal according to the sampling. The first delayer delays the first clock signal to obtain a second clock signal. The frequency detector samples the data signal according to the second clock signal and provides a frequency instruction signal according to the sampling. The logic circuit generates a clock instruction signal according to the phase instruction signal and the frequency instruction signal. The CDR circuit adjusts the frequency of the first clock signal according to the status of the clock instruction signal.

Abstract: A delay locked loop (DLL) circuit includes a clock signal dividing unit that can divide a reference clock signal by a predetermined division ratio and generate a division clock signal, a feedback loop that can perform a delay locked operation on the division clock signal and generate a delay clock signal, a half period delay unit that can delay the delay clock signal by a half period of the reference clock signal and generate a half period delay clock signal, and an operation unit that can combine the delay clock signal and the half period delay clock signal and generate an output clock signal.

Abstract: The phase detection circuit may allow an operating speed of a semiconductor circuit to be increased irrespective of whether a combinational logic circuit within the semiconductor circuit operates at lower operating speeds. The phase detection circuit may adjust a data rate of an input data signal and selectively enable reference signals and error signals. The phase detection circuit may be included within a clock data recovery circuit.

Abstract: A delay locked loop (DLL) circuit includes a first delay control unit configured to generate a first delay control signal in response to a first phase detection signal to control a delay amount of a first delay line and to output a first delay amount information signal, a second delay control unit configured to generate a second delay control signal in response to a second phase detection signal to control a delay amount of a second delay line and to output a second delay amount information signal, and to control the delay amount of the second delay line again in response to the first delay control signal and a half cycle information signal, a half cycle detecting unit configured to receive the first delay amount information signal and the second delay amount information signal to extract half cycle information of a reference clock signal, thereby generating the half cycle information signal, and a duty cycle correcting unit configured to combine an output clock signal from the first delay line and an output

Abstract: Provided is a PLL apparatus outputting a frequency signal from a voltage-controlled oscillation unit in synchronization with an external reference frequency signal, in which the fluctuation of the frequency is reduced even when the external reference signal has a trouble For solving the problem, as a result of monitoring the signal level of the external reference frequency signal, when its signal level falls within a set range, data regarding a phase difference created by a phase difference data creating means is used for the PLL control, but when the signal level does not fall within the set range, it is recognized that the supply of the signal has been stopped or the supplied signal has abnormality and the data regarding the phase difference stored in a storage unit, for example, the stored latest data or the pre-created data is used instead for the PLL control.

Abstract: Methods and apparatus are provided for digital phase detection with improved frequency locking. A phase detector is disclosed for evaluating a phase difference between a clock signal and a reference signal. The disclosed phase detector samples the clock signal and the reference signal on positive edges of one or more of the clock signal and the reference signal, samples the clock signal and the reference signal on negative edges of one or more of the clock signal and the reference signal, and generates one or more error signals indicating a phase difference between the clock signal and the reference signal. A clock signal that is phase aligned with a reference signal can be generated by generating an error signal indicating a phase difference between the clock signal and the reference signal and applying the error signal to an oscillator to produce the clock signal.

Abstract: An All Digital PLL (ADPLL) and oscillation signal generation method using the ADPLL is provided for generating a spur-free oscillation signal by improving the frequency resolution of the ADPLL.

Abstract: A first embodiment of the present invention relates to a frequency and phase locked loop (FPLL) synthesizer having a frequency-locked loop (FLL) operating mode and a phase-locked loop (PLL) operating mode. The FLL operating mode is used for rapid coarse tuning of the FPLL synthesizer and is followed by the PLL operating mode for fine tuning and stabilization of the frequency of an output signal from the FPLL synthesizer. A second embodiment of the present invention relates to a high resolution frequency measurement circuit that is capable of directly measuring the frequency of a high frequency signal to provide a high resolution frequency measurement using a lower frequency reference signal, and may include linear feedback shift register (LFSR) circuitry and LFSR-to-binary conversion circuitry. A third embodiment of the present invention relates to an FPLL having an FLL that includes the high resolution frequency measurement circuit.

Abstract: The present invention relates to a digital offset phase-locked loop (DOPLL), which may have advantages of size, simplicity, performance, design portability, or any combination thereof, compared to analog-based phase-locked loops (PLLs). The DOPLL may include a digital controlled oscillator (DCO), which provides a controllable frequency output signal based on a digital control signal, a radio frequency (RF) mixer circuit, which provides a reduced-frequency feedback signal based on the controllable frequency output signal without reducing loop gain, a time-to-digital converter (TDC), which provides a digital feedback signal that is a time representation of the reduced-frequency feedback signal, and digital PLL circuitry, which provides the digital control signal based on the digital feedback signal and a digital setpoint signal.

Abstract: Self-biased bipolar ring-oscillator phase-locked loops with a wide tuning range are disclosed. In a particular example, an apparatus to provide a phase-locked loop is described, comprising a voltage-controlled oscillator (VCO) to provide an output clock signal having a frequency, a quantizer, a phase-frequency detector to generate an adjustment signal, and a charge pump to modify the control voltage. The example VCO includes several ring-oscillator stages, where each ring-oscillator stage includes several gain stages to provide several output currents based on a comparison of a control voltage and several corresponding threshold voltages. The example quantizer includes several comparators to generate digital signals based on the output currents. The example charge pump modifies the control voltage based on the digital signals and the adjustment signal, and includes several switching elements to increase or decrease current to the charge pump based on the digital signals.

Abstract: This invention relates to a phase-locked loop circuit and a data reproduction apparatus, which can reduce a processing time that is required for initial adjustment in the data reproduction apparatus. In a digital data reproduction apparatus having two control functions, i.e., phase and duty adjustments for binarized data, the phase comparison with one edge is performed only at the phase adjustment by means of a phase-locked loop circuit 33 having an edge switching means 4 which controls the phase comparator 1. The phase comparator 1 inputs the binarized and a bit synchronous clock, and switches the output between a comparison result with one edge, i.e., a rising edge or a falling edge of binarized data, and a comparison result with both edges.

Abstract: A voltage controlled oscillator and a method of operating a voltage-controlled oscillator are disclosed. The oscillator comprises a current controlled oscillator having a variable frequency current output, a first control path for generating a first control current having a first adjustable gain, and a second control path for generating a second control current having a second adjustable gain. A summer is provided for adding the first and second control currents to obtain a summed control current, and for applying the summed control current as an input current to the current controlled oscillator. A control sub-circuit is used for controlling the gain of the first control current as a function of a defined voltage on the second control path to maintain constant the gain of the current output of the current controlled oscillator over a given operating range of the current controlled oscillator.

Abstract: Methods, systems, and apparatus, including computer program products, are described for calibrating control loops, specifically phase-locked loops. In one aspect, an apparatus is provided that includes an oscillator model that generates a predicted phase based on an input, a first averaging submodule that generates an average predicted phase over a predetermined number of samples, and a first summing submodule that receives a first corrected phase error and generates a predicted repetitive phase disturbance using the first corrected phase error, the predicted phase, and the average predicted phase.

Abstract: A phase difference detector having concurrent fine and coarse capabilities synchronizes operations of coarse and fine phase detectors. In one embodiment, clusters of fine timing markers are generated by delay stages of a delay locked loop. The K'th one of every cluster of J fine timing markers is designated as a coarse marker. A first timer determines which of J fine markers in a first cluster is closest to a rising edge of a reference signal. A second timer determines which of J fine markers in a second cluster is closest to a rising edge of a follower signal. A third timer determines how many coarse markers separate the rising edges of the reference and follower signals. Temporal displacement values obtained from the determinations of the first though third timers are combined to produce a phase displacement measurement signal of broad range and high precision across its operating range.

Abstract: A design structure including a system. The system includes a fractional-N phase-locked loop (PLL). The PLL includes a PLL input and a PLL output. The fractional-N PLL further includes a multiplexer. The multiplexer includes a multiplexer output electrically coupled to the PLL input. The multiplexer further includes M multiplexer inputs, M being an integer greater than 1. Two or more reference frequencies are applied to the inputs of the multiplexer, by the selection of one from the reference frequencies, the low spur can be reached.

Abstract: A phase locked loop has a digitally controlled oscillator (DCO) for generating a DCO output signal (fOSC), a clock divider coupled to the DCO and receiving the DCO output signal and outputting a feedback clock signal (fN), and a phase frequency detector (PFD) coupled to the DCO and controlling the DCO by a DCO control signal (dCNTL).

Abstract: A floating DC-offset circuit for a phase detector. The circuit may provide a floating DC-offset to the phase detector, or to the voltage-controlled oscillator of the phase-locked loop. The circuit includes a voltage comparator, clock, digital resistor, and offset line to a DC-offset branch of the phase detector. The voltage comparator detects when the voltage at the output of the loop filter of the phase-locked loop has gone outside of a designated range, and activates the clock when the voltage is outside the designated range. The clock emits impulses that are counted by the digital resistor. The digital resistor shifts DC-offset at the DC-offset branch of the phase detector. The new DC-offset level is maintained once the loop filter output voltage has returned within the designated range. In an alternate embodiment, the DC-offset branch is connected to rough-tuning input of a wide-tuned voltage-controlled oscillator.

Abstract: System and methods of synchronizing reference frequencies are disclosed. In an exemplary implementation, a method may comprise providing separate reference frequencies for each of a plurality of operational components. The method may also comprise connecting the separate reference frequencies to one another in a modular, fault-tolerant circuit topology. The method may also comprise synchronizing the separate reference frequencies so that each of the operational components operate at the same frequency.

Abstract: Disclosed herein is a phase lock loop (PLL) circuit capable of executing digital control of an oscillation circuit thereof by using a dividing ratio represented by a digital value obtained by dividing an oscillation frequency by a reference frequency. The PLL circuit includes a phase comparator for comparing the digital value obtained by converting the dividing ratio with a digital value representing each cumulative addition value of a clock count expressed in a decimal-point format representing the oscillation signal in each period of a reference signal, a loop-gain control section configured to control the loop gain of the PLL circuit, and an output converging section configured to converge an output by the phase comparator.

Abstract: A method of eliminating a runaway condition in a PLL includes the steps of: determining whether the PLL is locked to an input reference signal; when the PLL is not locked to the input reference signal, determining whether a frequency of an output signal generated by the PLL exceeds a prescribed maximum frequency; and when the frequency of the output signal generated by the PLL exceeds the prescribed maximum frequency, resetting the PLL to thereby eliminate the runaway condition.